ARM: dts: stm32: Add ST MIPID02 bindings to AV96

Add DT bindings for ST MIPID02 and DCMI to Avenger96 base DT.
Both the ST MIPID02 and DCMI are disabled by default, as the
AV96 camera module is optional.

Signed-off-by: Marek Vasut <[e-mail]>
Cc: Alexandre Torgue <[e-mail]>
Cc: Manivannan Sadhasivam <[e-mail]>
Cc: [e-mail]
To: [e-mail]
Signed-off-by: Alexandre Torgue <[e-mail]>

arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi

···
 	};
 };
 
+&dcmi {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&dcmi_pins_c>;
+	pinctrl-1 = <&dcmi_sleep_pins_c>;
+	status = "disabled";
+
+	port {
+		dcmi_0: endpoint {
+			remote-endpoint = <&stmipi_2>;
+			bus-type = <5>;
+			bus-width = <8>;
+			pclk-sample = <0>;
+		};
+	};
+};
+
 &ethernet0 {
 	status = "okay";
 	pinctrl-0 = <&ethernet0_rgmii_pins_c>;
···
 };
 
 &i2c4 {
+	stmipi: stmipi@14 {
+		compatible = "st,st-mipid02";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&mco1_pins_a>;
+		pinctrl-1 = <&mco1_sleep_pins_a>;
+		reg = <0x14>;
+		clocks = <&rcc CK_MCO1>;
+		clock-names = "xclk";
+		assigned-clocks = <&rcc CK_MCO1>;
+		assigned-clock-parents = <&rcc CK_HSE>;
+		assigned-clock-rates = <24000000>;
+		VDDE-supply = <&v1v8>;
+		VDDIN-supply = <&v1v8>;
+		reset-gpios = <&gpioz 0 GPIO_ACTIVE_LOW>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				stmipi_0: endpoint {
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				stmipi_2: endpoint {
+					bus-width = <8>;
+					hsync-active = <0>;
+					vsync-active = <0>;
+					pclk-sample = <0>;
+					remote-endpoint = <&dcmi_0>;
+				};
+			};
+		};
+	};
+
 	hdmi-transmitter@3d {
 		compatible = "adi,adv7513";
 		reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>;