tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

igb: remove unused defines

This patch removes all of the unused defines from the .h files contained in
igb. For some defines there was a use and so I plugged them into the correct
locations.

Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Alexander Duyck and committed by
David S. Miller cbd347ad bc1cbd34

+11 -175
+2 -14
drivers/net/igb/e1000_82575.h
··· 58 58 E1000_EICR_RX_QUEUE2 | \ 59 59 E1000_EICR_RX_QUEUE3) 60 60 61 - #define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE 62 - #define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE 63 - 64 61 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 65 62 66 63 /* Receive Descriptor - Advanced */ ··· 91 94 92 95 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 93 96 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 94 - 95 - /* RSS Hash results */ 96 - 97 - /* RSS Packet Types as indicated in the receive descriptor */ 98 - #define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ 99 - #define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 100 97 101 98 /* Transmit Descriptor - Advanced */ 102 99 union e1000_adv_tx_desc { ··· 141 150 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ 142 151 143 152 /* Direct Cache Access (DCA) definitions */ 144 - #define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 145 - #define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 146 - 147 - #define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 148 - #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 153 + #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */ 154 + #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 149 155 150 156 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 151 157 #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
-113
drivers/net/igb/e1000_defines.h
··· 42 42 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 43 43 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 44 44 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 45 - #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 46 - #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 47 - #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 48 - #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 49 - #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 50 - #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 51 - #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 52 - #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 53 - 54 - /* Wake Up Status */ 55 - 56 - /* Wake Up Packet Length */ 57 - 58 - /* Four Flexible Filters are supported */ 59 - #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 60 - 61 - /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 62 - #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 63 - 64 45 65 46 /* Extended Device Control */ 66 - #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 67 - #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ 68 - #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ 69 47 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ 70 - #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 71 - #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 72 48 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 73 49 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 74 50 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 ··· 79 103 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 80 104 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 81 105 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 82 - #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 83 106 #define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */ 84 - #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 85 - #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 86 - #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 87 - #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 88 - #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 89 - #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 90 107 91 108 #define E1000_RXDEXT_STATERR_CE 0x01000000 92 109 #define E1000_RXDEXT_STATERR_SE 0x02000000 ··· 88 119 #define E1000_RXDEXT_STATERR_TCPE 0x20000000 89 120 #define E1000_RXDEXT_STATERR_IPE 0x40000000 90 121 #define E1000_RXDEXT_STATERR_RXE 0x80000000 91 - 92 - /* mask to determine if packets should be dropped due to frame errors */ 93 - #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 94 - E1000_RXD_ERR_CE | \ 95 - E1000_RXD_ERR_SE | \ 96 - E1000_RXD_ERR_SEQ | \ 97 - E1000_RXD_ERR_CXE | \ 98 - E1000_RXD_ERR_RXE) 99 122 100 123 /* Same mask, but for extended and packet split descriptors */ 101 124 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ ··· 107 146 /* Management Control */ 108 147 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 109 148 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 110 - #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 111 149 /* Enable Neighbor Discovery Filtering */ 112 150 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 113 151 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 114 152 /* Enable MAC address filtering */ 115 153 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 116 - /* Enable MNG packets to host memory */ 117 - #define E1000_MANC_EN_MNG2HOST 0x00200000 118 - /* Enable IP address filtering */ 119 - 120 154 121 155 /* Receive Control */ 122 156 #define E1000_RCTL_EN 0x00000002 /* enable */ ··· 119 163 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 120 164 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 121 165 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 122 - #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 123 166 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 124 167 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 125 168 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 126 169 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 127 170 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 128 - #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 129 - #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 130 171 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 131 172 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 132 173 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ ··· 180 227 /* enable link status from external LINK_0 and LINK_1 pins */ 181 228 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 182 229 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 183 - #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 184 - #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 185 230 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 186 - #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 187 - #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 188 231 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 189 232 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 190 233 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ ··· 258 309 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 259 310 260 311 /* LED Control */ 261 - #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 262 312 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 263 - #define E1000_LEDCTL_LED0_IVRT 0x00000040 264 313 #define E1000_LEDCTL_LED0_BLINK 0x00000080 265 314 266 315 #define E1000_LEDCTL_MODE_LED_ON 0xE ··· 305 358 306 359 #define MAX_JUMBO_FRAME_SIZE 0x3F00 307 360 308 - /* Extended Configuration Control and Size */ 309 - #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 310 - 311 361 /* PBA constants */ 312 - #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 313 - #define E1000_PBA_24K 0x0018 314 362 #define E1000_PBA_34K 0x0022 315 363 #define E1000_PBA_64K 0x0040 /* 64KB */ 316 364 ··· 321 379 322 380 /* Interrupt Cause Read */ 323 381 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 324 - #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 325 382 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 326 383 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 327 384 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 328 - #define E1000_ICR_RXO 0x00000040 /* rx overrun */ 329 385 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 330 - #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 331 - #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ 332 - #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 333 - #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 334 - #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 335 - #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 336 - #define E1000_ICR_TXD_LOW 0x00008000 337 - #define E1000_ICR_SRPD 0x00010000 338 - #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 339 - #define E1000_ICR_MNG 0x00040000 /* Manageability event */ 340 - #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ 341 386 /* If this bit asserted, the driver should claim the interrupt */ 342 387 #define E1000_ICR_INT_ASSERTED 0x80000000 343 - /* queue 0 Rx descriptor FIFO parity error */ 344 - #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 345 - /* queue 0 Tx descriptor FIFO parity error */ 346 - #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 347 - /* host arb read buffer parity error */ 348 - #define E1000_ICR_HOST_ARB_PAR 0x00400000 349 - #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 350 - /* queue 1 Rx descriptor FIFO parity error */ 351 - #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 352 - /* queue 1 Tx descriptor FIFO parity error */ 353 - #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 354 - /* FW changed the status of DISSW bit in the FWSM */ 355 - #define E1000_ICR_DSW 0x00000020 356 388 /* LAN connected device generates an interrupt */ 357 - #define E1000_ICR_PHYINT 0x00001000 358 - #define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ 359 389 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 360 390 361 391 /* Extended Interrupt Cause Read */ ··· 339 425 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 340 426 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 341 427 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 342 - #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 343 428 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 344 429 /* TCP Timer */ 345 430 ··· 368 455 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 369 456 370 457 /* Extended Interrupt Mask Set */ 371 - #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 372 458 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 373 459 374 460 /* Interrupt Cause Set */ 375 461 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 376 462 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 377 - #define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 378 463 379 464 /* Extended Interrupt Cause Set */ 380 465 ··· 408 497 #define E1000_ERR_MAC_INIT 5 409 498 #define E1000_ERR_RESET 9 410 499 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 411 - #define E1000_ERR_HOST_INTERFACE_COMMAND 11 412 500 #define E1000_BLK_PHY_RESET 12 413 501 #define E1000_ERR_SWFW_SYNC 13 414 502 #define E1000_NOT_IMPLEMENTED 14 ··· 427 517 /* Flow Control */ 428 518 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 429 519 430 - /* Transmit Configuration Word */ 431 - #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 432 - 433 - /* Receive Configuration Word */ 434 - 435 - /* PCI Express Control */ 436 - #define E1000_GCR_RXD_NO_SNOOP 0x00000001 437 - #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 438 - #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 439 - #define E1000_GCR_TXD_NO_SNOOP 0x00000008 440 - #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 441 - #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 442 - 443 - #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 444 - E1000_GCR_RXDSCW_NO_SNOOP | \ 445 - E1000_GCR_RXDSCR_NO_SNOOP | \ 446 - E1000_GCR_TXD_NO_SNOOP | \ 447 - E1000_GCR_TXDSCW_NO_SNOOP | \ 448 - E1000_GCR_TXDSCR_NO_SNOOP) 449 - 450 520 /* PHY Control Register */ 451 521 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 452 522 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 453 - #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 454 523 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 455 524 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 456 525 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ ··· 559 670 #define IGP_LED3_MODE 0x07000000 560 671 561 672 /* PCI/PCI-X/PCI-EX Config space */ 562 - #define PCI_HEADER_TYPE_REGISTER 0x0E 563 673 #define PCIE_LINK_STATUS 0x12 564 674 565 - #define PCI_HEADER_TYPE_MULTIFUNC 0x80 566 675 #define PCIE_LINK_WIDTH_MASK 0x3F0 567 676 #define PCIE_LINK_WIDTH_SHIFT 4 568 677
-5
drivers/net/igb/e1000_mac.h
··· 82 82 #define E1000_FWSM_MODE_MASK 0xE 83 83 #define E1000_FWSM_MODE_SHIFT 1 84 84 85 - #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 86 85 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 87 - 88 - #define E1000_HICR_EN 0x01 /* Enable bit - RO */ 89 - /* Driver sets this bit when done to put command in RAM */ 90 - #define E1000_HICR_C 0x02 91 86 92 87 extern void e1000_init_function_pointers_82575(struct e1000_hw *hw); 93 88 extern u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
-3
drivers/net/igb/e1000_phy.c
··· 39 39 /* Cable length tables */ 40 40 static const u16 e1000_m88_cable_length_table[] = 41 41 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 42 - #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 43 - (sizeof(e1000_m88_cable_length_table) / \ 44 - sizeof(e1000_m88_cable_length_table[0])) 45 42 46 43 static const u16 e1000_igp_2_cable_length_table[] = 47 44 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
-14
drivers/net/igb/e1000_regs.h
··· 73 73 #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ 74 74 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 75 75 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 76 - #define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n))) 77 76 #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ 78 77 79 78 /* IEEE 1588 TIMESYNCH */ ··· 177 178 : (0x0E018 + ((_n) * 0x40))) 178 179 #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \ 179 180 : (0x0E028 + ((_n) * 0x40))) 180 - #define E1000_TARC(_n) (0x03840 + (_n << 8)) 181 181 #define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) 182 182 #define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) 183 183 #define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \ ··· 299 301 #define E1000_MANC 0x05820 /* Management Control - RW */ 300 302 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 301 303 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 302 - #define E1000_HOST_IF 0x08800 /* Host Interface */ 303 304 304 - #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ 305 305 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 306 306 #define E1000_CCMCTL 0x05B48 /* CCM Control Register */ 307 307 #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ ··· 307 311 #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 308 312 #define E1000_SWSM 0x05B50 /* SW Semaphore */ 309 313 #define E1000_FWSM 0x05B54 /* FW Semaphore */ 310 - #define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ 311 314 #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ 312 - #define E1000_HICR 0x08F00 /* Host Inteface Control */ 313 315 314 316 /* RSS registers */ 315 317 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ ··· 316 322 #define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */ 317 323 /* MSI-X Allocation Register (_i) - RW */ 318 324 #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) 319 - /* MSI-X Table entry addr low reg 0 - RW */ 320 - #define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) 321 - /* MSI-X Table entry addr upper reg 0 - RW */ 322 - #define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) 323 - /* MSI-X Table entry message reg 0 - RW */ 324 - #define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) 325 - /* MSI-X Table entry vector ctrl reg 0 - RW */ 326 - #define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) 327 325 /* Redirection Table - RW Array */ 328 326 #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) 329 327 #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
+3 -14
drivers/net/igb/igb.h
··· 40 40 41 41 struct igb_adapter; 42 42 43 - /* Interrupt defines */ 44 - #define IGB_MIN_DYN_ITR 3000 45 - #define IGB_MAX_DYN_ITR 96000 46 - 47 43 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */ 48 44 #define IGB_START_ITR 648 49 - 50 - #define IGB_DYN_ITR_PACKET_THRESHOLD 2 51 - #define IGB_DYN_ITR_LENGTH_LOW 200 52 - #define IGB_DYN_ITR_LENGTH_HIGH 1000 53 45 54 46 /* TX/RX descriptor defines */ 55 47 #define IGB_DEFAULT_TXD 256 ··· 84 92 #define IGB_RXBUFFER_512 512 85 93 #define IGB_RXBUFFER_1024 1024 86 94 #define IGB_RXBUFFER_2048 2048 87 - #define IGB_RXBUFFER_4096 4096 88 - #define IGB_RXBUFFER_8192 8192 89 95 #define IGB_RXBUFFER_16384 16384 90 96 91 97 /* Packet Buffer allocations */ ··· 276 286 }; 277 287 278 288 #define IGB_FLAG_HAS_MSI (1 << 0) 279 - #define IGB_FLAG_MSI_ENABLE (1 << 1) 280 - #define IGB_FLAG_DCA_ENABLED (1 << 2) 281 - #define IGB_FLAG_QUAD_PORT_A (1 << 3) 282 - #define IGB_FLAG_NEED_CTX_IDX (1 << 4) 289 + #define IGB_FLAG_DCA_ENABLED (1 << 1) 290 + #define IGB_FLAG_QUAD_PORT_A (1 << 2) 291 + #define IGB_FLAG_NEED_CTX_IDX (1 << 3) 283 292 284 293 enum e1000_state_t { 285 294 __IGB_TESTING,
+1 -5
drivers/net/igb/igb_ethtool.c
··· 1366 1366 wr32(E1000_RDH(0), 0); 1367 1367 wr32(E1000_RDT(0), 0); 1368 1368 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1369 - rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 | 1370 - E1000_RCTL_RDMTS_HALF | 1369 + rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 1371 1370 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 1372 1371 wr32(E1000_RCTL, rctl); 1373 1372 wr32(E1000_SRRCTL(0), 0); ··· 1853 1854 1854 1855 return 0; 1855 1856 } 1856 - 1857 - /* toggle LED 4 times per second = 2 "blinks" per second */ 1858 - #define IGB_ID_INTERVAL (HZ/4) 1859 1857 1860 1858 /* bit defines for adapter->led_status */ 1861 1859 #define IGB_LED_ON 0
+5 -7
drivers/net/igb/igb_main.c
··· 1305 1305 hw->fc.original_type = e1000_fc_default; 1306 1306 hw->fc.type = e1000_fc_default; 1307 1307 1308 - adapter->itr_setting = 3; 1308 + adapter->itr_setting = IGB_DEFAULT_ITR; 1309 1309 adapter->itr = IGB_START_ITR; 1310 1310 1311 1311 igb_validate_mdi_setting(hw); ··· 1366 1366 dev_info(&pdev->dev, "DCA enabled\n"); 1367 1367 /* Always use CB2 mode, difference is masked 1368 1368 * in the CB driver. */ 1369 - wr32(E1000_DCA_CTRL, 2); 1369 + wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 1370 1370 igb_setup_dca(adapter); 1371 1371 } 1372 1372 #endif ··· 1498 1498 dev_info(&pdev->dev, "DCA disabled\n"); 1499 1499 dca_remove_requester(&pdev->dev); 1500 1500 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 1501 - wr32(E1000_DCA_CTRL, 1); 1501 + wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 1502 1502 } 1503 1503 #endif 1504 1504 ··· 3058 3058 return __igb_maybe_stop_tx(netdev, tx_ring, size); 3059 3059 } 3060 3060 3061 - #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1) 3062 - 3063 3061 static int igb_xmit_frame_ring_adv(struct sk_buff *skb, 3064 3062 struct net_device *netdev, 3065 3063 struct igb_ring *tx_ring) ··· 3584 3586 break; 3585 3587 /* Always use CB2 mode, difference is masked 3586 3588 * in the CB driver. */ 3587 - wr32(E1000_DCA_CTRL, 2); 3589 + wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 3588 3590 if (dca_add_requester(dev) == 0) { 3589 3591 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3590 3592 dev_info(&adapter->pdev->dev, "DCA enabled\n"); ··· 3599 3601 dca_remove_requester(dev); 3600 3602 dev_info(&adapter->pdev->dev, "DCA disabled\n"); 3601 3603 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3602 - wr32(E1000_DCA_CTRL, 1); 3604 + wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3603 3605 } 3604 3606 break; 3605 3607 }