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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
xtensa: move built-in PIC to drivers/irqchip
Extract xtensa built-in interrupt controller implementation from
xtensa/kernel/irq.c and move it to other irqchips, providing way to
instantiate it from the device tree.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
authored by
Max Filippov
and committed by
Chris Zankel
cbd1de2e
c8f3a7dc
+165
-108
+1
-1
arch/xtensa/boot/dts/xtfpga.dtsi
+1
-1
arch/xtensa/boot/dts/xtfpga.dtsi
+7
arch/xtensa/include/asm/irq.h
+7
arch/xtensa/include/asm/irq.h
···
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}
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struct irqaction;
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+
struct irq_domain;
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+
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int xtensa_irq_domain_xlate(const u32 *intspec, unsigned int intsize,
49
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unsigned long int_irq, unsigned long ext_irq,
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unsigned long *out_hwirq, unsigned int *out_type);
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int xtensa_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw);
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unsigned xtensa_map_ext_irq(unsigned ext_irq);
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#endif /* _XTENSA_IRQ_H */
+30
-107
arch/xtensa/kernel/irq.c
+30
-107
arch/xtensa/kernel/irq.c
···
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/xtensa-pic.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <asm/uaccess.h>
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#include <asm/platform.h>
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-
static unsigned int cached_irq_mask;
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-
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atomic_t irq_err_count;
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-
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static struct irq_domain *root_domain;
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-
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/*
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* do_IRQ handles all normal device IRQ's (the special
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* SMP cross-CPU interrupts have their own specific
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* handlers).
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*/
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asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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-
int irq = irq_find_mapping(root_domain, hwirq);
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int irq = irq_find_mapping(NULL, hwirq);
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if (hwirq >= NR_IRQS) {
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printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
···
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return 0;
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}
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-
static void xtensa_irq_mask(struct irq_data *d)
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int xtensa_irq_domain_xlate(const u32 *intspec, unsigned int intsize,
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unsigned long int_irq, unsigned long ext_irq,
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unsigned long *out_hwirq, unsigned int *out_type)
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{
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cached_irq_mask &= ~(1 << d->hwirq);
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set_sr (cached_irq_mask, intenable);
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if (WARN_ON(intsize < 1 || intsize > 2))
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return -EINVAL;
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if (intsize == 2 && intspec[1] == 1) {
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int_irq = xtensa_map_ext_irq(ext_irq);
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if (int_irq < XCHAL_NUM_INTERRUPTS)
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*out_hwirq = int_irq;
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else
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return -EINVAL;
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} else {
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*out_hwirq = int_irq;
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}
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*out_type = IRQ_TYPE_NONE;
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return 0;
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}
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-
static void xtensa_irq_unmask(struct irq_data *d)
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{
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cached_irq_mask |= 1 << d->hwirq;
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set_sr (cached_irq_mask, intenable);
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}
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-
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static void xtensa_irq_enable(struct irq_data *d)
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{
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variant_irq_enable(d->hwirq);
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xtensa_irq_unmask(d);
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}
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static void xtensa_irq_disable(struct irq_data *d)
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{
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xtensa_irq_mask(d);
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variant_irq_disable(d->hwirq);
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}
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static void xtensa_irq_ack(struct irq_data *d)
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{
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set_sr(1 << d->hwirq, intclear);
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}
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static int xtensa_irq_retrigger(struct irq_data *d)
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{
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set_sr(1 << d->hwirq, intset);
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return 1;
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}
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static struct irq_chip xtensa_irq_chip = {
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.name = "xtensa",
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.irq_enable = xtensa_irq_enable,
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.irq_disable = xtensa_irq_disable,
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.irq_mask = xtensa_irq_mask,
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.irq_unmask = xtensa_irq_unmask,
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.irq_ack = xtensa_irq_ack,
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.irq_retrigger = xtensa_irq_retrigger,
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};
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static int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
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int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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struct irq_chip *irq_chip = d->host_data;
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u32 mask = 1 << hw;
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if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) {
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irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
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irq_set_chip_and_handler_name(irq, irq_chip,
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handle_simple_irq, "level");
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irq_set_status_flags(irq, IRQ_LEVEL);
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} else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) {
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irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
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irq_set_chip_and_handler_name(irq, irq_chip,
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handle_edge_irq, "edge");
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irq_clear_status_flags(irq, IRQ_LEVEL);
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} else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) {
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irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
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irq_set_chip_and_handler_name(irq, irq_chip,
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handle_level_irq, "level");
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irq_set_status_flags(irq, IRQ_LEVEL);
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} else if (mask & XCHAL_INTTYPE_MASK_TIMER) {
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irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
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handle_edge_irq, "edge");
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irq_set_chip_and_handler_name(irq, irq_chip,
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handle_percpu_irq, "timer");
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irq_clear_status_flags(irq, IRQ_LEVEL);
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} else {/* XCHAL_INTTYPE_MASK_WRITE_ERROR */
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/* XCHAL_INTTYPE_MASK_NMI */
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irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
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irq_set_chip_and_handler_name(irq, irq_chip,
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handle_level_irq, "level");
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irq_set_status_flags(irq, IRQ_LEVEL);
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}
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return 0;
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}
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static unsigned map_ext_irq(unsigned ext_irq)
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unsigned xtensa_map_ext_irq(unsigned ext_irq)
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{
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unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL;
···
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return XCHAL_NUM_INTERRUPTS;
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}
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/*
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* Device Tree IRQ specifier translation function which works with one or
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* two cell bindings. First cell value maps directly to the hwirq number.
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* Second cell if present specifies whether hwirq number is external (1) or
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* internal (0).
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*/
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int xtensa_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq, unsigned int *out_type)
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-
{
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if (WARN_ON(intsize < 1 || intsize > 2))
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return -EINVAL;
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if (intsize == 2 && intspec[1] == 1) {
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unsigned int_irq = map_ext_irq(intspec[0]);
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if (int_irq < XCHAL_NUM_INTERRUPTS)
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*out_hwirq = int_irq;
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else
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return -EINVAL;
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} else {
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*out_hwirq = intspec[0];
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}
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*out_type = IRQ_TYPE_NONE;
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return 0;
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}
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static const struct irq_domain_ops xtensa_irq_domain_ops = {
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.xlate = xtensa_irq_domain_xlate,
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.map = xtensa_irq_map,
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};
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void __init init_IRQ(void)
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{
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struct device_node *intc = NULL;
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cached_irq_mask = 0;
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set_sr(~0, intclear);
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#ifdef CONFIG_OF
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/* The interrupt controller device node is mandatory */
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intc = of_find_compatible_node(NULL, NULL, "xtensa,pic");
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BUG_ON(!intc);
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root_domain = irq_domain_add_linear(intc, NR_IRQS,
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&xtensa_irq_domain_ops, NULL);
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irqchip_init();
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#else
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root_domain = irq_domain_add_legacy(intc, NR_IRQS, 0, 0,
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&xtensa_irq_domain_ops, NULL);
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xtensa_pic_init_legacy(NULL);
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#endif
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irq_set_default_host(root_domain);
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variant_init_irq();
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}
+1
drivers/irqchip/Makefile
+1
drivers/irqchip/Makefile
+108
drivers/irqchip/irq-xtensa-pic.c
+108
drivers/irqchip/irq-xtensa-pic.c
···
1
+
/*
2
+
* Xtensa built-in interrupt controller
3
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*
4
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* Copyright (C) 2002 - 2013 Tensilica, Inc.
5
+
* Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
6
+
*
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+
* This file is subject to the terms and conditions of the GNU General Public
8
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* License. See the file "COPYING" in the main directory of this archive
9
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* for more details.
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*
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* Chris Zankel <chris@zankel.net>
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* Kevin Chea
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*/
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+
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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+
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#include "irqchip.h"
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+
22
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unsigned int cached_irq_mask;
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+
24
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/*
25
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* Device Tree IRQ specifier translation function which works with one or
26
+
* two cell bindings. First cell value maps directly to the hwirq number.
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* Second cell if present specifies whether hwirq number is external (1) or
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* internal (0).
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*/
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static int xtensa_pic_irq_domain_xlate(struct irq_domain *d,
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struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq, unsigned int *out_type)
34
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{
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return xtensa_irq_domain_xlate(intspec, intsize,
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intspec[0], intspec[0],
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out_hwirq, out_type);
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}
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static const struct irq_domain_ops xtensa_irq_domain_ops = {
41
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.xlate = xtensa_pic_irq_domain_xlate,
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.map = xtensa_irq_map,
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};
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static void xtensa_irq_mask(struct irq_data *d)
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{
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cached_irq_mask &= ~(1 << d->hwirq);
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set_sr(cached_irq_mask, intenable);
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}
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+
51
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static void xtensa_irq_unmask(struct irq_data *d)
52
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{
53
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cached_irq_mask |= 1 << d->hwirq;
54
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set_sr(cached_irq_mask, intenable);
55
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}
56
+
57
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static void xtensa_irq_enable(struct irq_data *d)
58
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{
59
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variant_irq_enable(d->hwirq);
60
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xtensa_irq_unmask(d);
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}
62
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static void xtensa_irq_disable(struct irq_data *d)
64
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{
65
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xtensa_irq_mask(d);
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variant_irq_disable(d->hwirq);
67
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}
68
+
69
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static void xtensa_irq_ack(struct irq_data *d)
70
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{
71
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set_sr(1 << d->hwirq, intclear);
72
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}
73
+
74
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static int xtensa_irq_retrigger(struct irq_data *d)
75
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{
76
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set_sr(1 << d->hwirq, intset);
77
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return 1;
78
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}
79
+
80
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static struct irq_chip xtensa_irq_chip = {
81
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.name = "xtensa",
82
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.irq_enable = xtensa_irq_enable,
83
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.irq_disable = xtensa_irq_disable,
84
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.irq_mask = xtensa_irq_mask,
85
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.irq_unmask = xtensa_irq_unmask,
86
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.irq_ack = xtensa_irq_ack,
87
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.irq_retrigger = xtensa_irq_retrigger,
88
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};
89
+
90
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int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)
91
+
{
92
+
struct irq_domain *root_domain =
93
+
irq_domain_add_legacy(NULL, NR_IRQS, 0, 0,
94
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&xtensa_irq_domain_ops, &xtensa_irq_chip);
95
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irq_set_default_host(root_domain);
96
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return 0;
97
+
}
98
+
99
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static int __init xtensa_pic_init(struct device_node *np,
100
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struct device_node *interrupt_parent)
101
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{
102
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struct irq_domain *root_domain =
103
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irq_domain_add_linear(np, NR_IRQS, &xtensa_irq_domain_ops,
104
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&xtensa_irq_chip);
105
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irq_set_default_host(root_domain);
106
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return 0;
107
+
}
108
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IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init);
+18
include/linux/irqchip/xtensa-pic.h
+18
include/linux/irqchip/xtensa-pic.h
···
1
+
/*
2
+
* Xtensa built-in interrupt controller
3
+
*
4
+
* Copyright (C) 2002 - 2013 Tensilica, Inc.
5
+
* Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
6
+
*
7
+
* This file is subject to the terms and conditions of the GNU General Public
8
+
* License. See the file "COPYING" in the main directory of this archive
9
+
* for more details.
10
+
*/
11
+
12
+
#ifndef __LINUX_IRQCHIP_XTENSA_PIC_H
13
+
#define __LINUX_IRQCHIP_XTENSA_PIC_H
14
+
15
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struct device_node;
16
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int xtensa_pic_init_legacy(struct device_node *interrupt_parent);
17
+
18
+
#endif /* __LINUX_IRQCHIP_XTENSA_PIC_H */