tjh.dev / kernel
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ARM: dts: imx6: RIoTboard explicitly define pad settings

Instead of relying on defaults or bootloader settings, explicitly define
all pad settings.

This resolves reported issues of no analogue audio output.

Signed-off-by: Iain Paton <ipaton0@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

authored by

Iain Paton and committed by
Shawn Guo cb9456b5 e7779620

+16 -16
+16 -16
arch/arm/boot/dts/imx6dl-riotboard.dts
··· 334 334 imx6-riotboard { 335 335 pinctrl_audmux: audmuxgrp { 336 336 fsl,pins = < 337 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x8000000 338 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x8000000 339 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x8000000 340 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x8000000 337 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 338 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 339 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 340 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 341 341 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ 342 342 >; 343 343 }; ··· 375 375 fsl,pins = < 376 376 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 377 377 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 378 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 378 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 379 379 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 380 380 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 381 381 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 ··· 388 388 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */ 389 389 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */ 390 390 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ 391 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 /* GPIO16 -> AR8035 25MHz */ 391 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ 392 392 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ 393 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* AR8035 interrupt */ 393 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ 394 394 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 395 395 >; 396 396 }; ··· 425 425 426 426 pinctrl_led: ledgrp { 427 427 fsl,pins = < 428 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* user led0 */ 429 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x80000000 /* user led1 */ 428 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */ 429 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */ 430 430 >; 431 431 }; 432 432 ··· 492 492 pinctrl_usbotg: usbotggrp { 493 493 fsl,pins = < 494 494 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 495 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ 496 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x80000000 495 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ 496 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 497 497 >; 498 498 }; 499 499 ··· 505 505 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 506 506 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 507 507 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 508 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* SD2 CD */ 509 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* SD2 WP */ 508 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */ 509 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */ 510 510 >; 511 511 }; 512 512 ··· 518 518 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 519 519 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 520 520 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 521 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3 CD */ 522 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x80000000 /* SD3 WP */ 521 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */ 522 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */ 523 523 >; 524 524 }; 525 525 ··· 531 531 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 532 532 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 533 533 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 534 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 /* SD4 RST (eMMC) */ 534 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */ 535 535 >; 536 536 }; 537 537 };