Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amdgpu: fix issue that can't set vce clock gate.

Need to soft reset VCE as part of the clockgating
sequence.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rex Zhu and committed by
Alex Deucher
cb48a13e b6723c8d

+17 -1
+17 -1
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
··· 44 44 static void vce_v2_0_mc_resume(struct amdgpu_device *adev); 45 45 static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev); 46 46 static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev); 47 - 47 + static int vce_v2_0_wait_for_idle(void *handle); 48 48 /** 49 49 * vce_v2_0_ring_get_rptr - get read pointer 50 50 * ··· 339 339 { 340 340 u32 orig, tmp; 341 341 342 + if (gated) { 343 + if (vce_v2_0_wait_for_idle(adev)) { 344 + DRM_INFO("VCE is busy, Can't set clock gateing"); 345 + return; 346 + } 347 + WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK); 348 + WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); 349 + mdelay(100); 350 + WREG32(mmVCE_STATUS, 0); 351 + } else { 352 + WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK); 353 + WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); 354 + mdelay(100); 355 + } 356 + 342 357 tmp = RREG32(mmVCE_CLOCK_GATING_B); 343 358 tmp &= ~0x00060006; 344 359 if (gated) { ··· 377 362 378 363 if (gated) 379 364 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0); 365 + WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); 380 366 } 381 367 382 368 static void vce_v2_0_disable_cg(struct amdgpu_device *adev)