tjh.dev / kernel
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ARM: socfpga: dts: fix qspi node compatible

The QSPI flash node needs to have the required "jedec,spi-nor" in the
compatible string.

Fixes: 1df99da8953 ("ARM: dts: socfpga: Enable QSPI in Arria10 devkit")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

Dinh Nguyen cb25b119 d58071a8

+8 -8
+1 -1
arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
··· 12 12 flash0: n25q00@0 { 13 13 #address-cells = <1>; 14 14 #size-cells = <1>; 15 - compatible = "n25q00aa"; 15 + compatible = "micron,mt25qu02g", "jedec,spi-nor"; 16 16 reg = <0>; 17 17 spi-max-frequency = <100000000>; 18 18
+1 -1
arch/arm/boot/dts/socfpga_arria5_socdk.dts
··· 119 119 flash: flash@0 { 120 120 #address-cells = <1>; 121 121 #size-cells = <1>; 122 - compatible = "n25q256a"; 122 + compatible = "micron,n25q256a", "jedec,spi-nor"; 123 123 reg = <0>; 124 124 spi-max-frequency = <100000000>; 125 125
+1 -1
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
··· 124 124 flash0: n25q00@0 { 125 125 #address-cells = <1>; 126 126 #size-cells = <1>; 127 - compatible = "n25q00"; 127 + compatible = "micron,mt25qu02g", "jedec,spi-nor"; 128 128 reg = <0>; /* chip select */ 129 129 spi-max-frequency = <100000000>; 130 130
+1 -1
arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
··· 169 169 flash: flash@0 { 170 170 #address-cells = <1>; 171 171 #size-cells = <1>; 172 - compatible = "n25q00"; 172 + compatible = "micron,mt25qu02g", "jedec,spi-nor"; 173 173 reg = <0>; 174 174 spi-max-frequency = <100000000>; 175 175
+1 -1
arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
··· 80 80 flash: flash@0 { 81 81 #address-cells = <1>; 82 82 #size-cells = <1>; 83 - compatible = "n25q256a"; 83 + compatible = "micron,n25q256a", "jedec,spi-nor"; 84 84 reg = <0>; 85 85 spi-max-frequency = <100000000>; 86 86 m25p,fast-read;
+1 -1
arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
··· 116 116 flash0: n25q512a@0 { 117 117 #address-cells = <1>; 118 118 #size-cells = <1>; 119 - compatible = "n25q512a"; 119 + compatible = "micron,n25q512a", "jedec,spi-nor"; 120 120 reg = <0>; 121 121 spi-max-frequency = <100000000>; 122 122
+2 -2
arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
··· 224 224 n25q128@0 { 225 225 #address-cells = <1>; 226 226 #size-cells = <1>; 227 - compatible = "n25q128"; 227 + compatible = "micron,n25q128", "jedec,spi-nor"; 228 228 reg = <0>; /* chip select */ 229 229 spi-max-frequency = <100000000>; 230 230 m25p,fast-read; ··· 241 241 n25q00@1 { 242 242 #address-cells = <1>; 243 243 #size-cells = <1>; 244 - compatible = "n25q00"; 244 + compatible = "micron,mt25qu02g", "jedec,spi-nor"; 245 245 reg = <1>; /* chip select */ 246 246 spi-max-frequency = <100000000>; 247 247 m25p,fast-read;