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linux
ARM: dts: STi: Update clocks node location
Move:
_ arm_periph_clk node as child of clockgen-a9@92b0000 node
_ clk_m_a9_ext2f_div2 node as child of clk_s_c0_flexgen node
_ clk-tmdsout-hdmi node outiside soc node
This allows to fix the following warnings when compiling
dtb with W=1 option :
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /clocks/clk-m-a9-periphs missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /clocks/clk-m-a9-ext2f-div2s missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg):
Node /clocks/clk-m-a9-periphs missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg):
Node /clocks/clk-m-a9-ext2f-div2s missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg):
Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg):
Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property
arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /clocks/clk-m-a9-periphs missing or empty reg/ranges property
arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /clocks/clk-m-a9-ext2f-div2s missing or empty reg/ranges property
arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property
arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
+122
-122
+40
-39
arch/arm/boot/dts/stih407-clock.dtsi
+40
-39
arch/arm/boot/dts/stih407-clock.dtsi
···
7
7
*/
8
8
#include <dt-bindings/clock/stih407-clks.h>
9
9
/ {
10
+
/*
11
+
* Fixed 30MHz oscillator inputs to SoC
12
+
*/
13
+
clk_sysin: clk-sysin {
14
+
#clock-cells = <0>;
15
+
compatible = "fixed-clock";
16
+
clock-frequency = <30000000>;
17
+
};
18
+
19
+
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
20
+
#clock-cells = <0>;
21
+
compatible = "fixed-clock";
22
+
clock-frequency = <0>;
23
+
};
24
+
10
25
clocks {
11
26
#address-cells = <1>;
12
27
#size-cells = <1>;
13
28
ranges;
14
-
15
-
/*
16
-
* Fixed 30MHz oscillator inputs to SoC
17
-
*/
18
-
clk_sysin: clk-sysin {
19
-
#clock-cells = <0>;
20
-
compatible = "fixed-clock";
21
-
clock-frequency = <30000000>;
22
-
};
23
-
24
-
/*
25
-
* ARM Peripheral clock for timers
26
-
*/
27
-
arm_periph_clk: clk-m-a9-periphs {
28
-
#clock-cells = <0>;
29
-
compatible = "fixed-factor-clock";
30
-
31
-
clocks = <&clk_m_a9>;
32
-
clock-div = <2>;
33
-
clock-mult = <1>;
34
-
};
35
29
36
30
/*
37
31
* A9 PLL.
···
56
62
<&clockgen_a9_pll 0>,
57
63
<&clk_s_c0_flexgen 13>,
58
64
<&clk_m_a9_ext2f_div2>;
59
-
};
60
65
61
-
/*
62
-
* ARM Peripheral clock for timers
63
-
*/
64
-
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
65
-
#clock-cells = <0>;
66
-
compatible = "fixed-factor-clock";
67
66
68
-
clocks = <&clk_s_c0_flexgen 13>;
67
+
/*
68
+
* ARM Peripheral clock for timers
69
+
*/
70
+
arm_periph_clk: clk-m-a9-periphs {
71
+
#clock-cells = <0>;
72
+
compatible = "fixed-factor-clock";
69
73
70
-
clock-output-names = "clk-m-a9-ext2f-div2";
71
-
72
-
clock-div = <2>;
73
-
clock-mult = <1>;
74
+
clocks = <&clk_m_a9>;
75
+
clock-div = <2>;
76
+
clock-mult = <1>;
77
+
};
74
78
};
75
79
76
80
/*
···
196
204
<CLK_EXT2F_A9>,
197
205
<CLK_ICN_LMI>,
198
206
<CLK_ICN_SBC>;
207
+
208
+
/*
209
+
* ARM Peripheral clock for timers
210
+
*/
211
+
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
212
+
#clock-cells = <0>;
213
+
compatible = "fixed-factor-clock";
214
+
215
+
clocks = <&clk_s_c0_flexgen 13>;
216
+
217
+
clock-output-names = "clk-m-a9-ext2f-div2";
218
+
219
+
clock-div = <2>;
220
+
clock-mult = <1>;
221
+
};
199
222
};
200
223
};
201
224
···
259
252
"clk-s-d2-fs0-ch1",
260
253
"clk-s-d2-fs0-ch2",
261
254
"clk-s-d2-fs0-ch3";
262
-
};
263
-
264
-
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
265
-
#clock-cells = <0>;
266
-
compatible = "fixed-clock";
267
-
clock-frequency = <0>;
268
255
};
269
256
270
257
clockgen-d2@9106000 {
+41
-42
arch/arm/boot/dts/stih410-clock.dtsi
+41
-42
arch/arm/boot/dts/stih410-clock.dtsi
···
7
7
*/
8
8
#include <dt-bindings/clock/stih410-clks.h>
9
9
/ {
10
+
/*
11
+
* Fixed 30MHz oscillator inputs to SoC
12
+
*/
13
+
clk_sysin: clk-sysin {
14
+
#clock-cells = <0>;
15
+
compatible = "fixed-clock";
16
+
clock-frequency = <30000000>;
17
+
clock-output-names = "CLK_SYSIN";
18
+
};
19
+
20
+
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
21
+
#clock-cells = <0>;
22
+
compatible = "fixed-clock";
23
+
clock-frequency = <0>;
24
+
};
25
+
10
26
clocks {
11
27
#address-cells = <1>;
12
28
#size-cells = <1>;
13
29
ranges;
14
30
15
31
compatible = "st,stih410-clk", "simple-bus";
16
-
17
-
/*
18
-
* Fixed 30MHz oscillator inputs to SoC
19
-
*/
20
-
clk_sysin: clk-sysin {
21
-
#clock-cells = <0>;
22
-
compatible = "fixed-clock";
23
-
clock-frequency = <30000000>;
24
-
clock-output-names = "CLK_SYSIN";
25
-
};
26
-
27
-
/*
28
-
* ARM Peripheral clock for timers
29
-
*/
30
-
arm_periph_clk: clk-m-a9-periphs {
31
-
#clock-cells = <0>;
32
-
compatible = "fixed-factor-clock";
33
-
clocks = <&clk_m_a9>;
34
-
clock-div = <2>;
35
-
clock-mult = <1>;
36
-
};
37
32
38
33
/*
39
34
* A9 PLL.
···
59
64
<&clockgen_a9_pll 0>,
60
65
<&clk_s_c0_flexgen 13>,
61
66
<&clk_m_a9_ext2f_div2>;
62
-
};
63
-
64
-
/*
65
-
* ARM Peripheral clock for timers
66
-
*/
67
-
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
68
-
#clock-cells = <0>;
69
-
compatible = "fixed-factor-clock";
70
-
71
-
clocks = <&clk_s_c0_flexgen 13>;
72
-
73
-
clock-output-names = "clk-m-a9-ext2f-div2";
74
-
75
-
clock-div = <2>;
76
-
clock-mult = <1>;
67
+
/*
68
+
* ARM Peripheral clock for timers
69
+
*/
70
+
arm_periph_clk: clk-m-a9-periphs {
71
+
#clock-cells = <0>;
72
+
compatible = "fixed-factor-clock";
73
+
clocks = <&clk_m_a9>;
74
+
clock-div = <2>;
75
+
clock-mult = <1>;
76
+
};
77
77
};
78
78
79
79
/*
···
204
214
<CLK_EXT2F_A9>,
205
215
<CLK_ICN_LMI>,
206
216
<CLK_ICN_SBC>;
217
+
218
+
/*
219
+
* ARM Peripheral clock for timers
220
+
*/
221
+
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
222
+
#clock-cells = <0>;
223
+
compatible = "fixed-factor-clock";
224
+
225
+
clocks = <&clk_s_c0_flexgen 13>;
226
+
227
+
clock-output-names = "clk-m-a9-ext2f-div2";
228
+
229
+
clock-div = <2>;
230
+
clock-mult = <1>;
231
+
};
207
232
};
208
233
};
209
234
···
269
264
"clk-s-d2-fs0-ch1",
270
265
"clk-s-d2-fs0-ch2",
271
266
"clk-s-d2-fs0-ch3";
272
-
};
273
-
274
-
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
275
-
#clock-cells = <0>;
276
-
compatible = "fixed-clock";
277
-
clock-frequency = <0>;
278
267
};
279
268
280
269
clockgen-d2@9106000 {
+41
-41
arch/arm/boot/dts/stih418-clock.dtsi
+41
-41
arch/arm/boot/dts/stih418-clock.dtsi
···
7
7
*/
8
8
#include <dt-bindings/clock/stih418-clks.h>
9
9
/ {
10
+
/*
11
+
* Fixed 30MHz oscillator inputs to SoC
12
+
*/
13
+
clk_sysin: clk-sysin {
14
+
#clock-cells = <0>;
15
+
compatible = "fixed-clock";
16
+
clock-frequency = <30000000>;
17
+
clock-output-names = "CLK_SYSIN";
18
+
};
19
+
20
+
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
21
+
#clock-cells = <0>;
22
+
compatible = "fixed-clock";
23
+
clock-frequency = <0>;
24
+
};
25
+
10
26
clocks {
11
27
#address-cells = <1>;
12
28
#size-cells = <1>;
13
29
ranges;
14
30
15
31
compatible = "st,stih418-clk", "simple-bus";
16
-
17
-
/*
18
-
* Fixed 30MHz oscillator inputs to SoC
19
-
*/
20
-
clk_sysin: clk-sysin {
21
-
#clock-cells = <0>;
22
-
compatible = "fixed-clock";
23
-
clock-frequency = <30000000>;
24
-
clock-output-names = "CLK_SYSIN";
25
-
};
26
-
27
-
/*
28
-
* ARM Peripheral clock for timers
29
-
*/
30
-
arm_periph_clk: clk-m-a9-periphs {
31
-
#clock-cells = <0>;
32
-
compatible = "fixed-factor-clock";
33
-
clocks = <&clk_m_a9>;
34
-
clock-div = <2>;
35
-
clock-mult = <1>;
36
-
};
37
32
38
33
/*
39
34
* A9 PLL.
···
59
64
<&clockgen_a9_pll 0>,
60
65
<&clk_s_c0_flexgen 13>,
61
66
<&clk_m_a9_ext2f_div2>;
62
-
};
63
67
64
-
/*
65
-
* ARM Peripheral clock for timers
66
-
*/
67
-
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
68
-
#clock-cells = <0>;
69
-
compatible = "fixed-factor-clock";
70
-
71
-
clocks = <&clk_s_c0_flexgen 13>;
72
-
73
-
clock-output-names = "clk-m-a9-ext2f-div2";
74
-
75
-
clock-div = <2>;
76
-
clock-mult = <1>;
68
+
/*
69
+
* ARM Peripheral clock for timers
70
+
*/
71
+
arm_periph_clk: clk-m-a9-periphs {
72
+
#clock-cells = <0>;
73
+
compatible = "fixed-factor-clock";
74
+
clocks = <&clk_m_a9>;
75
+
clock-div = <2>;
76
+
clock-mult = <1>;
77
+
};
77
78
};
78
79
79
80
/*
···
198
207
"clk-proc-mixer",
199
208
"clk-proc-sc",
200
209
"clk-avsp-hevc";
210
+
211
+
/*
212
+
* ARM Peripheral clock for timers
213
+
*/
214
+
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
215
+
#clock-cells = <0>;
216
+
compatible = "fixed-factor-clock";
217
+
218
+
clocks = <&clk_s_c0_flexgen 13>;
219
+
220
+
clock-output-names = "clk-m-a9-ext2f-div2";
221
+
222
+
clock-div = <2>;
223
+
clock-mult = <1>;
224
+
};
201
225
};
202
226
};
203
227
···
263
257
"clk-s-d2-fs0-ch1",
264
258
"clk-s-d2-fs0-ch2",
265
259
"clk-s-d2-fs0-ch3";
266
-
};
267
-
268
-
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
269
-
#clock-cells = <0>;
270
-
compatible = "fixed-clock";
271
-
clock-frequency = <0>;
272
260
};
273
261
274
262
clockgen-d2@9106000 {