tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge master.kernel.org:/home/rmk/linux-2.6-arm

Linus Torvalds ca98f825 b67c26e4

+51 -10
unified split
+18 -1
arch/arm/configs/spitz_defconfig
··· 897 # 898 # I2C support 899 # 900 - # CONFIG_I2C is not set 901 902 # 903 # Hardware Monitoring support
··· 897 # 898 # I2C support 899 # 900 + CONFIG_I2C=y 901 + # CONFIG_I2C_CHARDEV is not set 902 + 903 + # 904 + # I2C Algorithms 905 + # 906 + # CONFIG_I2C_ALGOBIT is not set 907 + # CONFIG_I2C_ALGOPCF is not set 908 + # CONFIG_I2C_ALGOPCA is not set 909 + 910 + # 911 + # I2C Hardware Bus support 912 + # 913 + CONFIG_I2C_PXA=y 914 + # CONFIG_I2C_PXA_SLAVE is not set 915 + # CONFIG_I2C_PARPORT_LIGHT is not set 916 + # CONFIG_I2C_STUB is not set 917 + # CONFIG_I2C_PCA_ISA is not set 918 919 # 920 # Hardware Monitoring support
+1 -1
arch/arm/mach-ixp4xx/ixdp425-setup.c
··· 85 { 86 .mapbase = IXP4XX_UART2_BASE_PHYS, 87 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, 88 - .irq = IRQ_IXP4XX_UART1, 89 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 90 .iotype = UPIO_MEM, 91 .regshift = 2,
··· 85 { 86 .mapbase = IXP4XX_UART2_BASE_PHYS, 87 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, 88 + .irq = IRQ_IXP4XX_UART2, 89 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 90 .iotype = UPIO_MEM, 91 .regshift = 2,
+2
arch/arm/mach-pxa/Kconfig
··· 77 depends PXA_SHARPSL_27x 78 select PXA_SHARP_Cxx00 79 select MACH_SPITZ 80 81 config MACH_SPITZ 82 bool "Enable Sharp Zaurus SL-3000 (Spitz) Support"
··· 77 depends PXA_SHARPSL_27x 78 select PXA_SHARP_Cxx00 79 select MACH_SPITZ 80 + select I2C 81 + select I2C_PXA 82 83 config MACH_SPITZ 84 bool "Enable Sharp Zaurus SL-3000 (Spitz) Support"
+6 -1
arch/arm/mm/flush.c
··· 155 * space mappings, we can be lazy and remember that we may have dirty 156 * kernel cache lines for later. Otherwise, we assume we have 157 * aliasing mappings. 158 */ 159 void flush_dcache_page(struct page *page) 160 { 161 struct address_space *mapping = page_mapping(page); 162 163 if (mapping && !mapping_mapped(mapping)) 164 set_bit(PG_dcache_dirty, &page->flags); 165 - else { 166 __flush_dcache_page(mapping, page); 167 if (mapping && cache_is_vivt()) 168 __flush_dcache_aliases(mapping, page);
··· 155 * space mappings, we can be lazy and remember that we may have dirty 156 * kernel cache lines for later. Otherwise, we assume we have 157 * aliasing mappings. 158 + * 159 + * Note that we disable the lazy flush for SMP. 160 */ 161 void flush_dcache_page(struct page *page) 162 { 163 struct address_space *mapping = page_mapping(page); 164 165 + #ifndef CONFIG_SMP 166 if (mapping && !mapping_mapped(mapping)) 167 set_bit(PG_dcache_dirty, &page->flags); 168 + else 169 + #endif 170 + { 171 __flush_dcache_page(mapping, page); 172 if (mapping && cache_is_vivt()) 173 __flush_dcache_aliases(mapping, page);
-5
include/asm-arm/semaphore.h
··· 47 sema_init(sem, 0); 48 } 49 50 - static inline int sema_count(struct semaphore *sem) 51 - { 52 - return atomic_read(&sem->count); 53 - } 54 - 55 /* 56 * special register calling convention 57 */
··· 47 sema_init(sem, 0); 48 } 49 50 /* 51 * special register calling convention 52 */
+24 -2
include/asm-arm/spinlock.h
··· 30 __asm__ __volatile__( 31 "1: ldrex %0, [%1]\n" 32 " teq %0, #0\n" 33 " strexeq %0, %2, [%1]\n" 34 " teqeq %0, #0\n" 35 " bne 1b" ··· 68 smp_mb(); 69 70 __asm__ __volatile__( 71 - " str %1, [%0]" 72 : 73 : "r" (&lock->lock), "r" (0) 74 : "cc"); ··· 94 __asm__ __volatile__( 95 "1: ldrex %0, [%1]\n" 96 " teq %0, #0\n" 97 " strexeq %0, %2, [%1]\n" 98 " teq %0, #0\n" 99 " bne 1b" ··· 132 smp_mb(); 133 134 __asm__ __volatile__( 135 - "str %1, [%0]" 136 : 137 : "r" (&rw->lock), "r" (0) 138 : "cc"); ··· 162 "1: ldrex %0, [%2]\n" 163 " adds %0, %0, #1\n" 164 " strexpl %1, %0, [%2]\n" 165 " rsbpls %0, %1, #0\n" 166 " bmi 1b" 167 : "=&r" (tmp), "=&r" (tmp2) ··· 186 " strex %1, %0, [%2]\n" 187 " teq %1, #0\n" 188 " bne 1b" 189 : "=&r" (tmp), "=&r" (tmp2) 190 : "r" (&rw->lock) 191 : "cc");
··· 30 __asm__ __volatile__( 31 "1: ldrex %0, [%1]\n" 32 " teq %0, #0\n" 33 + #ifdef CONFIG_CPU_32v6K 34 + " wfene\n" 35 + #endif 36 " strexeq %0, %2, [%1]\n" 37 " teqeq %0, #0\n" 38 " bne 1b" ··· 65 smp_mb(); 66 67 __asm__ __volatile__( 68 + " str %1, [%0]\n" 69 + #ifdef CONFIG_CPU_32v6K 70 + " mcr p15, 0, %1, c7, c10, 4\n" /* DSB */ 71 + " sev" 72 + #endif 73 : 74 : "r" (&lock->lock), "r" (0) 75 : "cc"); ··· 87 __asm__ __volatile__( 88 "1: ldrex %0, [%1]\n" 89 " teq %0, #0\n" 90 + #ifdef CONFIG_CPU_32v6K 91 + " wfene\n" 92 + #endif 93 " strexeq %0, %2, [%1]\n" 94 " teq %0, #0\n" 95 " bne 1b" ··· 122 smp_mb(); 123 124 __asm__ __volatile__( 125 + "str %1, [%0]\n" 126 + #ifdef CONFIG_CPU_32v6K 127 + " mcr p15, 0, %1, c7, c10, 4\n" /* DSB */ 128 + " sev\n" 129 + #endif 130 : 131 : "r" (&rw->lock), "r" (0) 132 : "cc"); ··· 148 "1: ldrex %0, [%2]\n" 149 " adds %0, %0, #1\n" 150 " strexpl %1, %0, [%2]\n" 151 + #ifdef CONFIG_CPU_32v6K 152 + " wfemi\n" 153 + #endif 154 " rsbpls %0, %1, #0\n" 155 " bmi 1b" 156 : "=&r" (tmp), "=&r" (tmp2) ··· 169 " strex %1, %0, [%2]\n" 170 " teq %1, #0\n" 171 " bne 1b" 172 + #ifdef CONFIG_CPU_32v6K 173 + "\n cmp %0, #0\n" 174 + " mcreq p15, 0, %0, c7, c10, 4\n" 175 + " seveq" 176 + #endif 177 : "=&r" (tmp), "=&r" (tmp2) 178 : "r" (&rw->lock) 179 : "cc");