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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: qcom-ufs: add support for 14nm phy
This change adds a support for a 14nm qcom-ufs phy that is
required in platforms that use ufs-qcom controller.
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Reviewed-by: Dov Levenglick <dovl@codeaurora.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
authored by
Yaniv Gardi
and committed by
Christoph Hellwig
ca14ab55
39e794bf
+379
+1
drivers/phy/Makefile
+1
drivers/phy/Makefile
+201
drivers/phy/phy-qcom-ufs-qmp-14nm.c
+201
drivers/phy/phy-qcom-ufs-qmp-14nm.c
···
1
+
/*
2
+
* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify
5
+
* it under the terms of the GNU General Public License version 2 and
6
+
* only version 2 as published by the Free Software Foundation.
7
+
*
8
+
* This program is distributed in the hope that it will be useful,
9
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
10
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11
+
* GNU General Public License for more details.
12
+
*
13
+
*/
14
+
15
+
#include "phy-qcom-ufs-qmp-14nm.h"
16
+
17
+
#define UFS_PHY_NAME "ufs_phy_qmp_14nm"
18
+
#define UFS_PHY_VDDA_PHY_UV (925000)
19
+
20
+
static
21
+
int ufs_qcom_phy_qmp_14nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
22
+
bool is_rate_B)
23
+
{
24
+
int tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);
25
+
int tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
26
+
int err;
27
+
28
+
err = ufs_qcom_phy_calibrate(ufs_qcom_phy, phy_cal_table_rate_A,
29
+
tbl_size_A, phy_cal_table_rate_B, tbl_size_B, is_rate_B);
30
+
31
+
if (err)
32
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dev_err(ufs_qcom_phy->dev,
33
+
"%s: ufs_qcom_phy_calibrate() failed %d\n",
34
+
__func__, err);
35
+
return err;
36
+
}
37
+
38
+
static
39
+
void ufs_qcom_phy_qmp_14nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
40
+
{
41
+
phy_common->quirks =
42
+
UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
43
+
}
44
+
45
+
static int ufs_qcom_phy_qmp_14nm_init(struct phy *generic_phy)
46
+
{
47
+
struct ufs_qcom_phy_qmp_14nm *phy = phy_get_drvdata(generic_phy);
48
+
struct ufs_qcom_phy *phy_common = &phy->common_cfg;
49
+
int err;
50
+
51
+
err = ufs_qcom_phy_init_clks(generic_phy, phy_common);
52
+
if (err) {
53
+
dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
54
+
__func__, err);
55
+
goto out;
56
+
}
57
+
58
+
err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common);
59
+
if (err) {
60
+
dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
61
+
__func__, err);
62
+
goto out;
63
+
}
64
+
phy_common->vdda_phy.max_uV = UFS_PHY_VDDA_PHY_UV;
65
+
phy_common->vdda_phy.min_uV = UFS_PHY_VDDA_PHY_UV;
66
+
67
+
ufs_qcom_phy_qmp_14nm_advertise_quirks(phy_common);
68
+
69
+
out:
70
+
return err;
71
+
}
72
+
73
+
static
74
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void ufs_qcom_phy_qmp_14nm_power_control(struct ufs_qcom_phy *phy, bool val)
75
+
{
76
+
writel_relaxed(val ? 0x1 : 0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
77
+
/*
78
+
* Before any transactions involving PHY, ensure PHY knows
79
+
* that it's analog rail is powered ON (or OFF).
80
+
*/
81
+
mb();
82
+
}
83
+
84
+
static inline
85
+
void ufs_qcom_phy_qmp_14nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
86
+
{
87
+
/*
88
+
* 14nm PHY does not have TX_LANE_ENABLE register.
89
+
* Implement this function so as not to propagate error to caller.
90
+
*/
91
+
}
92
+
93
+
static inline void ufs_qcom_phy_qmp_14nm_start_serdes(struct ufs_qcom_phy *phy)
94
+
{
95
+
u32 tmp;
96
+
97
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tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
98
+
tmp &= ~MASK_SERDES_START;
99
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tmp |= (1 << OFFSET_SERDES_START);
100
+
writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
101
+
/* Ensure register value is committed */
102
+
mb();
103
+
}
104
+
105
+
static int ufs_qcom_phy_qmp_14nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
106
+
{
107
+
int err = 0;
108
+
u32 val;
109
+
110
+
err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
111
+
val, (val & MASK_PCS_READY), 10, 1000000);
112
+
if (err)
113
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dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
114
+
__func__, err);
115
+
return err;
116
+
}
117
+
118
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static struct phy_ops ufs_qcom_phy_qmp_14nm_phy_ops = {
119
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.init = ufs_qcom_phy_qmp_14nm_init,
120
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.exit = ufs_qcom_phy_exit,
121
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.power_on = ufs_qcom_phy_power_on,
122
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.power_off = ufs_qcom_phy_power_off,
123
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.owner = THIS_MODULE,
124
+
};
125
+
126
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static struct ufs_qcom_phy_specific_ops phy_14nm_ops = {
127
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.calibrate_phy = ufs_qcom_phy_qmp_14nm_phy_calibrate,
128
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.start_serdes = ufs_qcom_phy_qmp_14nm_start_serdes,
129
+
.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_14nm_is_pcs_ready,
130
+
.set_tx_lane_enable = ufs_qcom_phy_qmp_14nm_set_tx_lane_enable,
131
+
.power_control = ufs_qcom_phy_qmp_14nm_power_control,
132
+
};
133
+
134
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static int ufs_qcom_phy_qmp_14nm_probe(struct platform_device *pdev)
135
+
{
136
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struct device *dev = &pdev->dev;
137
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struct phy *generic_phy;
138
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struct ufs_qcom_phy_qmp_14nm *phy;
139
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int err = 0;
140
+
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
142
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if (!phy) {
143
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dev_err(dev, "%s: failed to allocate phy\n", __func__);
144
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err = -ENOMEM;
145
+
goto out;
146
+
}
147
+
148
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generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
149
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&ufs_qcom_phy_qmp_14nm_phy_ops, &phy_14nm_ops);
150
+
151
+
if (!generic_phy) {
152
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dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
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__func__);
154
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err = -EIO;
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goto out;
156
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}
157
+
158
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phy_set_drvdata(generic_phy, phy);
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+
160
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strlcpy(phy->common_cfg.name, UFS_PHY_NAME,
161
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sizeof(phy->common_cfg.name));
162
+
163
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out:
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return err;
165
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}
166
+
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static int ufs_qcom_phy_qmp_14nm_remove(struct platform_device *pdev)
168
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{
169
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struct device *dev = &pdev->dev;
170
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struct phy *generic_phy = to_phy(dev);
171
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struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
172
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int err = 0;
173
+
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err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);
175
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if (err)
176
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dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",
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__func__, err);
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+
179
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return err;
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}
181
+
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static const struct of_device_id ufs_qcom_phy_qmp_14nm_of_match[] = {
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{.compatible = "qcom,ufs-phy-qmp-14nm"},
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{},
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};
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MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_14nm_of_match);
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+
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static struct platform_driver ufs_qcom_phy_qmp_14nm_driver = {
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.probe = ufs_qcom_phy_qmp_14nm_probe,
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.remove = ufs_qcom_phy_qmp_14nm_remove,
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.driver = {
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.of_match_table = ufs_qcom_phy_qmp_14nm_of_match,
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.name = "ufs_qcom_phy_qmp_14nm",
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.owner = THIS_MODULE,
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},
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};
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module_platform_driver(ufs_qcom_phy_qmp_14nm_driver);
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MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 14nm");
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MODULE_LICENSE("GPL v2");
+177
drivers/phy/phy-qcom-ufs-qmp-14nm.h
+177
drivers/phy/phy-qcom-ufs-qmp-14nm.h
···
1
+
/*
2
+
* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify
5
+
* it under the terms of the GNU General Public License version 2 and
6
+
* only version 2 as published by the Free Software Foundation.
7
+
*
8
+
* This program is distributed in the hope that it will be useful,
9
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
10
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11
+
* GNU General Public License for more details.
12
+
*
13
+
*/
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+
15
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#ifndef UFS_QCOM_PHY_QMP_14NM_H_
16
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#define UFS_QCOM_PHY_QMP_14NM_H_
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+
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#include "phy-qcom-ufs-i.h"
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+
20
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/* QCOM UFS PHY control registers */
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#define COM_OFF(x) (0x000 + x)
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#define PHY_OFF(x) (0xC00 + x)
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#define TX_OFF(n, x) (0x400 + (0x400 * n) + x)
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#define RX_OFF(n, x) (0x600 + (0x400 * n) + x)
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+
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/* UFS PHY QSERDES COM registers */
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#define QSERDES_COM_BG_TIMER COM_OFF(0x0C)
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#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x34)
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#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x3C)
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#define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0x4C)
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#define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0x50)
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#define QSERDES_COM_LOCK_CMP3_MODE0 COM_OFF(0x54)
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#define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0x58)
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#define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0x5C)
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#define QSERDES_COM_LOCK_CMP3_MODE1 COM_OFF(0x60)
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+
#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x78)
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#define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x7C)
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#define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x84)
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#define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x88)
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#define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x90)
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#define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x94)
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#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0xAC)
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#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0xB4)
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#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0xC8)
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#define QSERDES_COM_LOCK_CMP_CFG COM_OFF(0xCC)
46
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#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xD0)
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#define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xD4)
48
+
#define QSERDES_COM_DIV_FRAC_START1_MODE0 COM_OFF(0xDC)
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#define QSERDES_COM_DIV_FRAC_START2_MODE0 COM_OFF(0xE0)
50
+
#define QSERDES_COM_DIV_FRAC_START3_MODE0 COM_OFF(0xE4)
51
+
#define QSERDES_COM_DIV_FRAC_START1_MODE1 COM_OFF(0xE8)
52
+
#define QSERDES_COM_DIV_FRAC_START2_MODE1 COM_OFF(0xEC)
53
+
#define QSERDES_COM_DIV_FRAC_START3_MODE1 COM_OFF(0xF0)
54
+
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 COM_OFF(0x108)
55
+
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 COM_OFF(0x10C)
56
+
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 COM_OFF(0x110)
57
+
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 COM_OFF(0x114)
58
+
#define QSERDES_COM_VCO_TUNE_CTRL COM_OFF(0x124)
59
+
#define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0x128)
60
+
#define QSERDES_COM_VCO_TUNE1_MODE0 COM_OFF(0x12C)
61
+
#define QSERDES_COM_VCO_TUNE2_MODE0 COM_OFF(0x130)
62
+
#define QSERDES_COM_VCO_TUNE1_MODE1 COM_OFF(0x134)
63
+
#define QSERDES_COM_VCO_TUNE2_MODE1 COM_OFF(0x138)
64
+
#define QSERDES_COM_VCO_TUNE_TIMER1 COM_OFF(0x144)
65
+
#define QSERDES_COM_VCO_TUNE_TIMER2 COM_OFF(0x148)
66
+
#define QSERDES_COM_CLK_SELECT COM_OFF(0x174)
67
+
#define QSERDES_COM_HSCLK_SEL COM_OFF(0x178)
68
+
#define QSERDES_COM_CORECLK_DIV COM_OFF(0x184)
69
+
#define QSERDES_COM_CORE_CLK_EN COM_OFF(0x18C)
70
+
#define QSERDES_COM_CMN_CONFIG COM_OFF(0x194)
71
+
#define QSERDES_COM_SVS_MODE_CLK_SEL COM_OFF(0x19C)
72
+
#define QSERDES_COM_CORECLK_DIV_MODE1 COM_OFF(0x1BC)
73
+
74
+
/* UFS PHY registers */
75
+
#define UFS_PHY_PHY_START PHY_OFF(0x00)
76
+
#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04)
77
+
#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x168)
78
+
79
+
/* UFS PHY TX registers */
80
+
#define QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN TX_OFF(0, 0x68)
81
+
#define QSERDES_TX_LANE_MODE TX_OFF(0, 0x94)
82
+
83
+
/* UFS PHY RX registers */
84
+
#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN RX_OFF(0, 0x40)
85
+
#define QSERDES_RX_RX_TERM_BW RX_OFF(0, 0x90)
86
+
#define QSERDES_RX_RX_EQ_GAIN1_LSB RX_OFF(0, 0xC4)
87
+
#define QSERDES_RX_RX_EQ_GAIN1_MSB RX_OFF(0, 0xC8)
88
+
#define QSERDES_RX_RX_EQ_GAIN2_LSB RX_OFF(0, 0xCC)
89
+
#define QSERDES_RX_RX_EQ_GAIN2_MSB RX_OFF(0, 0xD0)
90
+
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0, 0xD8)
91
+
#define QSERDES_RX_SIGDET_CNTRL RX_OFF(0, 0x114)
92
+
#define QSERDES_RX_SIGDET_LVL RX_OFF(0, 0x118)
93
+
#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL RX_OFF(0, 0x11C)
94
+
#define QSERDES_RX_RX_INTERFACE_MODE RX_OFF(0, 0x12C)
95
+
96
+
/*
97
+
* This structure represents the 14nm specific phy.
98
+
* common_cfg MUST remain the first field in this structure
99
+
* in case extra fields are added. This way, when calling
100
+
* get_ufs_qcom_phy() of generic phy, we can extract the
101
+
* common phy structure (struct ufs_qcom_phy) out of it
102
+
* regardless of the relevant specific phy.
103
+
*/
104
+
struct ufs_qcom_phy_qmp_14nm {
105
+
struct ufs_qcom_phy common_cfg;
106
+
};
107
+
108
+
static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
109
+
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
110
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e),
111
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
112
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),
113
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x06),
114
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
115
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a),
116
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x05),
117
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a),
118
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
119
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
120
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
121
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20),
122
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),
123
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00),
124
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
125
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
126
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x14),
127
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
128
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
129
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
130
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
131
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
132
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
133
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
134
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
135
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
136
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
137
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
138
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
139
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
140
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
141
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
142
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
143
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
144
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
145
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
146
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
147
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
148
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
149
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
150
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
151
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
152
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
153
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
154
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
155
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
156
+
157
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45),
158
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x02),
159
+
160
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24),
161
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x02),
162
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
163
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
164
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
165
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B),
166
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
167
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
168
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
169
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0F),
170
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
171
+
};
172
+
173
+
static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
174
+
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x54),
175
+
};
176
+
177
+
#endif