tjh.dev / kernel
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kernel os linux
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clk: qcom: gcc-x1e80100: Don't use parking clk_ops for QUPs

Per Stephen Boyd's explanation in the link below, QUP RCG clocks do not
need to be parked when switching frequency. A side-effect in parking to a
lower frequency can be a momentary invalid clock driven on an in-use serial
peripheral.

This can cause "junk" to spewed out of a UART as a low-impact example. On
the x1e80100-crd this serial port junk can be observed on linux-next.

Apply a similar fix to the x1e80100 Global Clock controller to remediate.

Link: https://lore.kernel.org/all/20240819233628.2074654-3-swboyd@chromium.org/
Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Fixes: 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applicable")
Suggested-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20240823-x1e80100-clk-fix-v1-1-0b1b4f5a96e8@linaro.org
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by Bryan O'Donoghue and committed by Stephen Boyd ca082333 0f6eaf12

+24 -24
unified split
+24 -24
drivers/clk/qcom/gcc-x1e80100.c
··· 670 670 .parent_data = gcc_parent_data_0, 671 671 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 672 672 .flags = CLK_SET_RATE_PARENT, 673 - .ops = &clk_rcg2_shared_ops, 673 + .ops = &clk_rcg2_ops, 674 674 }; 675 675 676 676 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { ··· 687 687 .parent_data = gcc_parent_data_0, 688 688 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 689 689 .flags = CLK_SET_RATE_PARENT, 690 - .ops = &clk_rcg2_shared_ops, 690 + .ops = &clk_rcg2_ops, 691 691 }; 692 692 693 693 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { ··· 719 719 .parent_data = gcc_parent_data_0, 720 720 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 721 721 .flags = CLK_SET_RATE_PARENT, 722 - .ops = &clk_rcg2_shared_ops, 722 + .ops = &clk_rcg2_ops, 723 723 }; 724 724 725 725 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { ··· 736 736 .parent_data = gcc_parent_data_0, 737 737 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 738 738 .flags = CLK_SET_RATE_PARENT, 739 - .ops = &clk_rcg2_shared_ops, 739 + .ops = &clk_rcg2_ops, 740 740 }; 741 741 742 742 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { ··· 768 768 .parent_data = gcc_parent_data_0, 769 769 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 770 770 .flags = CLK_SET_RATE_PARENT, 771 - .ops = &clk_rcg2_shared_ops, 771 + .ops = &clk_rcg2_ops, 772 772 }; 773 773 774 774 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { ··· 785 785 .parent_data = gcc_parent_data_0, 786 786 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 787 787 .flags = CLK_SET_RATE_PARENT, 788 - .ops = &clk_rcg2_shared_ops, 788 + .ops = &clk_rcg2_ops, 789 789 }; 790 790 791 791 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { ··· 802 802 .parent_data = gcc_parent_data_0, 803 803 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 804 804 .flags = CLK_SET_RATE_PARENT, 805 - .ops = &clk_rcg2_shared_ops, 805 + .ops = &clk_rcg2_ops, 806 806 }; 807 807 808 808 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { ··· 819 819 .parent_data = gcc_parent_data_0, 820 820 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 821 821 .flags = CLK_SET_RATE_PARENT, 822 - .ops = &clk_rcg2_shared_ops, 822 + .ops = &clk_rcg2_ops, 823 823 }; 824 824 825 825 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { ··· 836 836 .parent_data = gcc_parent_data_0, 837 837 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 838 838 .flags = CLK_SET_RATE_PARENT, 839 - .ops = &clk_rcg2_shared_ops, 839 + .ops = &clk_rcg2_ops, 840 840 }; 841 841 842 842 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { ··· 853 853 .parent_data = gcc_parent_data_0, 854 854 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 855 855 .flags = CLK_SET_RATE_PARENT, 856 - .ops = &clk_rcg2_shared_ops, 856 + .ops = &clk_rcg2_ops, 857 857 }; 858 858 859 859 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { ··· 870 870 .parent_data = gcc_parent_data_0, 871 871 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 872 872 .flags = CLK_SET_RATE_PARENT, 873 - .ops = &clk_rcg2_shared_ops, 873 + .ops = &clk_rcg2_ops, 874 874 }; 875 875 876 876 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { ··· 887 887 .parent_data = gcc_parent_data_0, 888 888 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 889 889 .flags = CLK_SET_RATE_PARENT, 890 - .ops = &clk_rcg2_shared_ops, 890 + .ops = &clk_rcg2_ops, 891 891 }; 892 892 893 893 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { ··· 904 904 .parent_data = gcc_parent_data_0, 905 905 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 906 906 .flags = CLK_SET_RATE_PARENT, 907 - .ops = &clk_rcg2_shared_ops, 907 + .ops = &clk_rcg2_ops, 908 908 }; 909 909 910 910 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { ··· 921 921 .parent_data = gcc_parent_data_0, 922 922 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 923 923 .flags = CLK_SET_RATE_PARENT, 924 - .ops = &clk_rcg2_shared_ops, 924 + .ops = &clk_rcg2_ops, 925 925 }; 926 926 927 927 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { ··· 938 938 .parent_data = gcc_parent_data_0, 939 939 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 940 940 .flags = CLK_SET_RATE_PARENT, 941 - .ops = &clk_rcg2_shared_ops, 941 + .ops = &clk_rcg2_ops, 942 942 }; 943 943 944 944 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { ··· 955 955 .parent_data = gcc_parent_data_0, 956 956 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 957 957 .flags = CLK_SET_RATE_PARENT, 958 - .ops = &clk_rcg2_shared_ops, 958 + .ops = &clk_rcg2_ops, 959 959 }; 960 960 961 961 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { ··· 972 972 .parent_data = gcc_parent_data_0, 973 973 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 974 974 .flags = CLK_SET_RATE_PARENT, 975 - .ops = &clk_rcg2_shared_ops, 975 + .ops = &clk_rcg2_ops, 976 976 }; 977 977 978 978 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { ··· 989 989 .parent_data = gcc_parent_data_0, 990 990 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 991 991 .flags = CLK_SET_RATE_PARENT, 992 - .ops = &clk_rcg2_shared_ops, 992 + .ops = &clk_rcg2_ops, 993 993 }; 994 994 995 995 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { ··· 1006 1006 .parent_data = gcc_parent_data_0, 1007 1007 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1008 1008 .flags = CLK_SET_RATE_PARENT, 1009 - .ops = &clk_rcg2_shared_ops, 1009 + .ops = &clk_rcg2_ops, 1010 1010 }; 1011 1011 1012 1012 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { ··· 1023 1023 .parent_data = gcc_parent_data_0, 1024 1024 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1025 1025 .flags = CLK_SET_RATE_PARENT, 1026 - .ops = &clk_rcg2_shared_ops, 1026 + .ops = &clk_rcg2_ops, 1027 1027 }; 1028 1028 1029 1029 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { ··· 1040 1040 .parent_data = gcc_parent_data_0, 1041 1041 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1042 1042 .flags = CLK_SET_RATE_PARENT, 1043 - .ops = &clk_rcg2_shared_ops, 1043 + .ops = &clk_rcg2_ops, 1044 1044 }; 1045 1045 1046 1046 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { ··· 1057 1057 .parent_data = gcc_parent_data_0, 1058 1058 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1059 1059 .flags = CLK_SET_RATE_PARENT, 1060 - .ops = &clk_rcg2_shared_ops, 1060 + .ops = &clk_rcg2_ops, 1061 1061 }; 1062 1062 1063 1063 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { ··· 1074 1074 .parent_data = gcc_parent_data_8, 1075 1075 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 1076 1076 .flags = CLK_SET_RATE_PARENT, 1077 - .ops = &clk_rcg2_shared_ops, 1077 + .ops = &clk_rcg2_ops, 1078 1078 }; 1079 1079 1080 1080 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { ··· 1091 1091 .parent_data = gcc_parent_data_0, 1092 1092 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1093 1093 .flags = CLK_SET_RATE_PARENT, 1094 - .ops = &clk_rcg2_shared_ops, 1094 + .ops = &clk_rcg2_ops, 1095 1095 }; 1096 1096 1097 1097 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {