Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
sdhci: use PIO when DMA can't satisfy the request
Some controllers have been designed on the assumption that all transfers
will be 32-bit aligned, both in start address and in size. This is not a
guarantee the SDHCI specification provides and not one we can provide.
Revert back to PIO for individual requests in order to work around the
hardware bug.
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
+29
-3
drivers/mmc/host/sdhci.c
+29
-3
drivers/mmc/host/sdhci.c
···
43
43
#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
44
44
/* Controller has an unusable DMA engine */
45
45
#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
46
+
/* Controller can only DMA from 32-bit aligned addresses */
47
+
#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<6)
48
+
/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
49
+
#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7)
46
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static const struct pci_device_id pci_ids[] __devinitdata = {
48
52
{
···
433
429
434
430
writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
435
431
436
-
if (host->flags & SDHCI_USE_DMA) {
432
+
if (host->flags & SDHCI_USE_DMA)
433
+
host->flags |= SDHCI_REQ_USE_DMA;
434
+
435
+
if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
436
+
(host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
437
+
((data->blksz * data->blocks) & 0x3))) {
438
+
DBG("Reverting to PIO because of transfer size (%d)\n",
439
+
data->blksz * data->blocks);
440
+
host->flags &= ~SDHCI_REQ_USE_DMA;
441
+
}
442
+
443
+
/*
444
+
* The assumption here being that alignment is the same after
445
+
* translation to device address space.
446
+
*/
447
+
if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
448
+
(host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
449
+
(data->sg->offset & 0x3))) {
450
+
DBG("Reverting to PIO because of bad alignment\n");
451
+
host->flags &= ~SDHCI_REQ_USE_DMA;
452
+
}
453
+
454
+
if (host->flags & SDHCI_REQ_USE_DMA) {
437
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int count;
438
456
439
457
count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
···
492
466
mode |= SDHCI_TRNS_MULTI;
493
467
if (data->flags & MMC_DATA_READ)
494
468
mode |= SDHCI_TRNS_READ;
495
-
if (host->flags & SDHCI_USE_DMA)
469
+
if (host->flags & SDHCI_REQ_USE_DMA)
496
470
mode |= SDHCI_TRNS_DMA;
497
471
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writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
···
508
482
data = host->data;
509
483
host->data = NULL;
510
484
511
-
if (host->flags & SDHCI_USE_DMA) {
485
+
if (host->flags & SDHCI_REQ_USE_DMA) {
512
486
pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
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487
(data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
514
488
}
+2
-1
drivers/mmc/host/sdhci.h
+2
-1
drivers/mmc/host/sdhci.h
···
171
171
spinlock_t lock; /* Mutex */
172
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int flags; /* Host attributes */
174
-
#define SDHCI_USE_DMA (1<<0)
174
+
#define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */
175
+
#define SDHCI_REQ_USE_DMA (1<<1) /* Use DMA for this req. */
175
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unsigned int max_clk; /* Max possible freq (MHz) */
177
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unsigned int timeout_clk; /* Timeout freq (KHz) */