Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
[PATCH] ppc32: add 440ep support
Add PPC440EP core support. PPC440EP is a PPC440-based SoC with a classic PPC
FPU and another set of peripherals.
Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
authored by Matt Porter and committed by Linus Torvalds c9cf73ae e8be1c8e
+6
arch/ppc/boot/simple/Makefile
+6
arch/ppc/boot/simple/Makefile
···
61
end-$(CONFIG_EMBEDDEDBOOT) := embedded
62
misc-$(CONFIG_EMBEDDEDBOOT) := misc-embedded.o
63
64
+
zimage-$(CONFIG_BAMBOO) := zImage-TREE
65
+
zimageinitrd-$(CONFIG_BAMBOO) := zImage.initrd-TREE
66
+
end-$(CONFIG_BAMBOO) := bamboo
67
+
entrypoint-$(CONFIG_BAMBOO) := 0x01000000
68
+
extra.o-$(CONFIG_BAMBOO) := pibs.o
69
+
70
zimage-$(CONFIG_EBONY) := zImage-TREE
71
zimageinitrd-$(CONFIG_EBONY) := zImage.initrd-TREE
72
end-$(CONFIG_EBONY) := ebony
+3
-1
arch/ppc/boot/simple/pibs.c
+3
-1
arch/ppc/boot/simple/pibs.c
···
91
92
mac64 = simple_strtoull((char *)PIBS_MAC_BASE, 0, 16);
93
memcpy(hold_residual->bi_enetaddr, (char *)&mac64+2, 6);
94
-
#ifdef CONFIG_440GX
95
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET), 0, 16);
96
memcpy(hold_residual->bi_enet1addr, (char *)&mac64+2, 6);
97
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*2), 0, 16);
98
memcpy(hold_residual->bi_enet2addr, (char *)&mac64+2, 6);
99
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*3), 0, 16);
···
91
92
mac64 = simple_strtoull((char *)PIBS_MAC_BASE, 0, 16);
93
memcpy(hold_residual->bi_enetaddr, (char *)&mac64+2, 6);
94
+
#if defined(CONFIG_440GX) || defined(CONFIG_440EP)
95
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET), 0, 16);
96
memcpy(hold_residual->bi_enet1addr, (char *)&mac64+2, 6);
97
+
#endif
98
+
#ifdef CONFIG_440GX
99
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*2), 0, 16);
100
memcpy(hold_residual->bi_enet2addr, (char *)&mac64+2, 6);
101
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*3), 0, 16);
+20
arch/ppc/kernel/cputable.c
+20
arch/ppc/kernel/cputable.c
···
852
853
#endif /* CONFIG_40x */
854
#ifdef CONFIG_44x
855
+
{
856
+
.pvr_mask = 0xf0000fff,
857
+
.pvr_value = 0x40000850,
858
+
.cpu_name = "440EP Rev. A",
859
+
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
860
+
CPU_FTR_USE_TB,
861
+
.cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
862
+
.icache_bsize = 32,
863
+
.dcache_bsize = 32,
864
+
},
865
+
{
866
+
.pvr_mask = 0xf0000fff,
867
+
.pvr_value = 0x400008d3,
868
+
.cpu_name = "440EP Rev. B",
869
+
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
870
+
CPU_FTR_USE_TB,
871
+
.cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
872
+
.icache_bsize = 32,
873
+
.dcache_bsize = 32,
874
+
},
875
{ /* 440GP Rev. B */
876
.pvr_mask = 0xf0000fff,
877
.pvr_value = 0x40000440,
+1
arch/ppc/kernel/entry.S
+1
arch/ppc/kernel/entry.S
+12
arch/ppc/kernel/head_44x.S
+12
arch/ppc/kernel/head_44x.S
···
190
191
/* xlat fields */
192
lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */
193
ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */
194
195
/* attrib fields */
196
li r5,0
···
229
/* Establish the interrupt vector base */
230
lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
231
mtspr SPRN_IVPR,r4
232
233
/*
234
* This is where the main kernel code starts.
···
190
191
/* xlat fields */
192
lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */
193
+
#ifndef CONFIG_440EP
194
ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */
195
+
#endif
196
197
/* attrib fields */
198
li r5,0
···
227
/* Establish the interrupt vector base */
228
lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
229
mtspr SPRN_IVPR,r4
230
+
231
+
#ifdef CONFIG_440EP
232
+
/* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */
233
+
mfspr r2,SPRN_CCR0
234
+
lis r3,0xffef
235
+
ori r3,r3,0xffff
236
+
and r2,r2,r3
237
+
mtspr SPRN_CCR0,r2
238
+
isync
239
+
#endif
240
241
/*
242
* This is where the main kernel code starts.
+1
arch/ppc/kernel/misc.S
+1
arch/ppc/kernel/misc.S
+18
-2
arch/ppc/platforms/4xx/Kconfig
+18
-2
arch/ppc/platforms/4xx/Kconfig
···
68
depends on 44x
69
default EBONY
70
71
config EBONY
72
bool "Ebony"
73
help
···
103
depends on ASH
104
default y
105
106
config 440GP
107
bool
108
depends on EBONY
···
126
127
config 440
128
bool
129
-
depends on 440GP || 440SP
130
default y
131
132
config 440A
133
bool
134
depends on 440GX
135
default y
136
137
# All 405-based cores up until the 405GPR and 405EP have this errata.
···
158
159
config IBM_OCP
160
bool
161
-
depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
162
default y
163
164
config XILINX_OCP
···
68
depends on 44x
69
default EBONY
70
71
+
config BAMBOO
72
+
bool "Bamboo"
73
+
help
74
+
This option enables support for the IBM PPC440EP evaluation board.
75
+
76
config EBONY
77
bool "Ebony"
78
help
···
98
depends on ASH
99
default y
100
101
+
config 440EP
102
+
bool
103
+
depends on BAMBOO
104
+
select PPC_FPU
105
+
default y
106
+
107
config 440GP
108
bool
109
depends on EBONY
···
115
116
config 440
117
bool
118
+
depends on 440GP || 440SP || 440EP
119
default y
120
121
config 440A
122
bool
123
depends on 440GX
124
+
default y
125
+
126
+
config IBM440EP_ERR42
127
+
bool
128
+
depends on 440EP
129
default y
130
131
# All 405-based cores up until the 405GPR and 405EP have this errata.
···
142
143
config IBM_OCP
144
bool
145
+
depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
146
default y
147
148
config XILINX_OCP
+2
arch/ppc/platforms/4xx/Makefile
+2
arch/ppc/platforms/4xx/Makefile
···
2
# Makefile for the PowerPC 4xx linux kernel.
3
4
obj-$(CONFIG_ASH) += ash.o
5
obj-$(CONFIG_CPCI405) += cpci405.o
6
obj-$(CONFIG_EBONY) += ebony.o
7
obj-$(CONFIG_EP405) += ep405.o
···
20
obj-$(CONFIG_REDWOOD_5) += ibmstb4.o
21
obj-$(CONFIG_NP405H) += ibmnp405h.o
22
obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o
23
obj-$(CONFIG_440GP) += ibm440gp.o
24
obj-$(CONFIG_440GX) += ibm440gx.o
25
obj-$(CONFIG_440SP) += ibm440sp.o
···
2
# Makefile for the PowerPC 4xx linux kernel.
3
4
obj-$(CONFIG_ASH) += ash.o
5
+
obj-$(CONFIG_BAMBOO) += bamboo.o
6
obj-$(CONFIG_CPCI405) += cpci405.o
7
obj-$(CONFIG_EBONY) += ebony.o
8
obj-$(CONFIG_EP405) += ep405.o
···
19
obj-$(CONFIG_REDWOOD_5) += ibmstb4.o
20
obj-$(CONFIG_NP405H) += ibmnp405h.o
21
obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o
22
+
obj-$(CONFIG_440EP) += ibm440ep.o
23
obj-$(CONFIG_440GP) += ibm440gp.o
24
obj-$(CONFIG_440GX) += ibm440gx.o
25
obj-$(CONFIG_440SP) += ibm440sp.o
+220
arch/ppc/platforms/4xx/ibm440ep.c
+220
arch/ppc/platforms/4xx/ibm440ep.c
···
···
1
+
/*
2
+
* arch/ppc/platforms/4xx/ibm440ep.c
3
+
*
4
+
* PPC440EP I/O descriptions
5
+
*
6
+
* Wade Farnsworth <wfarnsworth@mvista.com>
7
+
* Copyright 2004 MontaVista Software Inc.
8
+
*
9
+
* This program is free software; you can redistribute it and/or modify it
10
+
* under the terms of the GNU General Public License as published by the
11
+
* Free Software Foundation; either version 2 of the License, or (at your
12
+
* option) any later version.
13
+
*
14
+
*/
15
+
#include <linux/init.h>
16
+
#include <linux/module.h>
17
+
#include <platforms/4xx/ibm440ep.h>
18
+
#include <asm/ocp.h>
19
+
#include <asm/ppc4xx_pic.h>
20
+
21
+
static struct ocp_func_emac_data ibm440ep_emac0_def = {
22
+
.rgmii_idx = -1, /* No RGMII */
23
+
.rgmii_mux = -1, /* No RGMII */
24
+
.zmii_idx = 0, /* ZMII device index */
25
+
.zmii_mux = 0, /* ZMII input of this EMAC */
26
+
.mal_idx = 0, /* MAL device index */
27
+
.mal_rx_chan = 0, /* MAL rx channel number */
28
+
.mal_tx_chan = 0, /* MAL tx channel number */
29
+
.wol_irq = 61, /* WOL interrupt number */
30
+
.mdio_idx = -1, /* No shared MDIO */
31
+
.tah_idx = -1, /* No TAH */
32
+
};
33
+
34
+
static struct ocp_func_emac_data ibm440ep_emac1_def = {
35
+
.rgmii_idx = -1, /* No RGMII */
36
+
.rgmii_mux = -1, /* No RGMII */
37
+
.zmii_idx = 0, /* ZMII device index */
38
+
.zmii_mux = 1, /* ZMII input of this EMAC */
39
+
.mal_idx = 0, /* MAL device index */
40
+
.mal_rx_chan = 1, /* MAL rx channel number */
41
+
.mal_tx_chan = 2, /* MAL tx channel number */
42
+
.wol_irq = 63, /* WOL interrupt number */
43
+
.mdio_idx = -1, /* No shared MDIO */
44
+
.tah_idx = -1, /* No TAH */
45
+
};
46
+
OCP_SYSFS_EMAC_DATA()
47
+
48
+
static struct ocp_func_mal_data ibm440ep_mal0_def = {
49
+
.num_tx_chans = 4, /* Number of TX channels */
50
+
.num_rx_chans = 2, /* Number of RX channels */
51
+
.txeob_irq = 10, /* TX End Of Buffer IRQ */
52
+
.rxeob_irq = 11, /* RX End Of Buffer IRQ */
53
+
.txde_irq = 33, /* TX Descriptor Error IRQ */
54
+
.rxde_irq = 34, /* RX Descriptor Error IRQ */
55
+
.serr_irq = 32, /* MAL System Error IRQ */
56
+
};
57
+
OCP_SYSFS_MAL_DATA()
58
+
59
+
static struct ocp_func_iic_data ibm440ep_iic0_def = {
60
+
.fast_mode = 0, /* Use standad mode (100Khz) */
61
+
};
62
+
63
+
static struct ocp_func_iic_data ibm440ep_iic1_def = {
64
+
.fast_mode = 0, /* Use standad mode (100Khz) */
65
+
};
66
+
OCP_SYSFS_IIC_DATA()
67
+
68
+
struct ocp_def core_ocp[] = {
69
+
{ .vendor = OCP_VENDOR_IBM,
70
+
.function = OCP_FUNC_OPB,
71
+
.index = 0,
72
+
.paddr = 0x0EF600000ULL,
73
+
.irq = OCP_IRQ_NA,
74
+
.pm = OCP_CPM_NA,
75
+
},
76
+
{ .vendor = OCP_VENDOR_IBM,
77
+
.function = OCP_FUNC_16550,
78
+
.index = 0,
79
+
.paddr = PPC440EP_UART0_ADDR,
80
+
.irq = UART0_INT,
81
+
.pm = IBM_CPM_UART0,
82
+
},
83
+
{ .vendor = OCP_VENDOR_IBM,
84
+
.function = OCP_FUNC_16550,
85
+
.index = 1,
86
+
.paddr = PPC440EP_UART1_ADDR,
87
+
.irq = UART1_INT,
88
+
.pm = IBM_CPM_UART1,
89
+
},
90
+
{ .vendor = OCP_VENDOR_IBM,
91
+
.function = OCP_FUNC_16550,
92
+
.index = 2,
93
+
.paddr = PPC440EP_UART2_ADDR,
94
+
.irq = UART2_INT,
95
+
.pm = IBM_CPM_UART2,
96
+
},
97
+
{ .vendor = OCP_VENDOR_IBM,
98
+
.function = OCP_FUNC_16550,
99
+
.index = 3,
100
+
.paddr = PPC440EP_UART3_ADDR,
101
+
.irq = UART3_INT,
102
+
.pm = IBM_CPM_UART3,
103
+
},
104
+
{ .vendor = OCP_VENDOR_IBM,
105
+
.function = OCP_FUNC_IIC,
106
+
.index = 0,
107
+
.paddr = 0x0EF600700ULL,
108
+
.irq = 2,
109
+
.pm = IBM_CPM_IIC0,
110
+
.additions = &ibm440ep_iic0_def,
111
+
.show = &ocp_show_iic_data
112
+
},
113
+
{ .vendor = OCP_VENDOR_IBM,
114
+
.function = OCP_FUNC_IIC,
115
+
.index = 1,
116
+
.paddr = 0x0EF600800ULL,
117
+
.irq = 7,
118
+
.pm = IBM_CPM_IIC1,
119
+
.additions = &ibm440ep_iic1_def,
120
+
.show = &ocp_show_iic_data
121
+
},
122
+
{ .vendor = OCP_VENDOR_IBM,
123
+
.function = OCP_FUNC_GPIO,
124
+
.index = 0,
125
+
.paddr = 0x0EF600B00ULL,
126
+
.irq = OCP_IRQ_NA,
127
+
.pm = IBM_CPM_GPIO0,
128
+
},
129
+
{ .vendor = OCP_VENDOR_IBM,
130
+
.function = OCP_FUNC_GPIO,
131
+
.index = 1,
132
+
.paddr = 0x0EF600C00ULL,
133
+
.irq = OCP_IRQ_NA,
134
+
.pm = OCP_CPM_NA,
135
+
},
136
+
{ .vendor = OCP_VENDOR_IBM,
137
+
.function = OCP_FUNC_MAL,
138
+
.paddr = OCP_PADDR_NA,
139
+
.irq = OCP_IRQ_NA,
140
+
.pm = OCP_CPM_NA,
141
+
.additions = &ibm440ep_mal0_def,
142
+
.show = &ocp_show_mal_data,
143
+
},
144
+
{ .vendor = OCP_VENDOR_IBM,
145
+
.function = OCP_FUNC_EMAC,
146
+
.index = 0,
147
+
.paddr = 0x0EF600E00ULL,
148
+
.irq = 60,
149
+
.pm = OCP_CPM_NA,
150
+
.additions = &ibm440ep_emac0_def,
151
+
.show = &ocp_show_emac_data,
152
+
},
153
+
{ .vendor = OCP_VENDOR_IBM,
154
+
.function = OCP_FUNC_EMAC,
155
+
.index = 1,
156
+
.paddr = 0x0EF600F00ULL,
157
+
.irq = 62,
158
+
.pm = OCP_CPM_NA,
159
+
.additions = &ibm440ep_emac1_def,
160
+
.show = &ocp_show_emac_data,
161
+
},
162
+
{ .vendor = OCP_VENDOR_IBM,
163
+
.function = OCP_FUNC_ZMII,
164
+
.paddr = 0x0EF600D00ULL,
165
+
.irq = OCP_IRQ_NA,
166
+
.pm = OCP_CPM_NA,
167
+
},
168
+
{ .vendor = OCP_VENDOR_INVALID
169
+
}
170
+
};
171
+
172
+
/* Polarity and triggering settings for internal interrupt sources */
173
+
struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
174
+
{ .polarity = 0xffbffe03,
175
+
.triggering = 0xfffffe00,
176
+
.ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
177
+
},
178
+
{ .polarity = 0xffffc6ef,
179
+
.triggering = 0xffffc7ff,
180
+
.ext_irq_mask = 0x00003800, /* IRQ7 - IRQ9 */
181
+
},
182
+
};
183
+
184
+
static struct resource usb_gadget_resources[] = {
185
+
[0] = {
186
+
.start = 0x050000100ULL,
187
+
.end = 0x05000017FULL,
188
+
.flags = IORESOURCE_MEM,
189
+
},
190
+
[1] = {
191
+
.start = 55,
192
+
.end = 55,
193
+
.flags = IORESOURCE_IRQ,
194
+
},
195
+
};
196
+
197
+
static u64 dma_mask = 0xffffffffULL;
198
+
199
+
static struct platform_device usb_gadget_device = {
200
+
.name = "musbhsfc",
201
+
.id = 0,
202
+
.num_resources = ARRAY_SIZE(usb_gadget_resources),
203
+
.resource = usb_gadget_resources,
204
+
.dev = {
205
+
.dma_mask = &dma_mask,
206
+
.coherent_dma_mask = 0xffffffffULL,
207
+
}
208
+
};
209
+
210
+
static struct platform_device *ibm440ep_devs[] __initdata = {
211
+
&usb_gadget_device,
212
+
};
213
+
214
+
static int __init
215
+
ibm440ep_platform_add_devices(void)
216
+
{
217
+
return platform_add_devices(ibm440ep_devs, ARRAY_SIZE(ibm440ep_devs));
218
+
}
219
+
arch_initcall(ibm440ep_platform_add_devices);
220
+
+76
arch/ppc/platforms/4xx/ibm440ep.h
+76
arch/ppc/platforms/4xx/ibm440ep.h
···
···
1
+
/*
2
+
* arch/ppc/platforms/4xx/ibm440ep.h
3
+
*
4
+
* PPC440EP definitions
5
+
*
6
+
* Wade Farnsworth <wfarnsworth@mvista.com>
7
+
*
8
+
* Copyright 2002 Roland Dreier
9
+
* Copyright 2004 MontaVista Software, Inc.
10
+
*
11
+
* This program is free software; you can redistribute it and/or modify it
12
+
* under the terms of the GNU General Public License as published by the
13
+
* Free Software Foundation; either version 2 of the License, or (at your
14
+
* option) any later version.
15
+
*
16
+
*/
17
+
18
+
#ifdef __KERNEL__
19
+
#ifndef __PPC_PLATFORMS_IBM440EP_H
20
+
#define __PPC_PLATFORMS_IBM440EP_H
21
+
22
+
#include <linux/config.h>
23
+
#include <asm/ibm44x.h>
24
+
25
+
/* UART */
26
+
#define PPC440EP_UART0_ADDR 0x0EF600300
27
+
#define PPC440EP_UART1_ADDR 0x0EF600400
28
+
#define PPC440EP_UART2_ADDR 0x0EF600500
29
+
#define PPC440EP_UART3_ADDR 0x0EF600600
30
+
#define UART0_INT 0
31
+
#define UART1_INT 1
32
+
#define UART2_INT 3
33
+
#define UART3_INT 4
34
+
35
+
/* Clock and Power Management */
36
+
#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
37
+
#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
38
+
#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
39
+
#define IBM_CPM_USB1H 0x08000000 /* USB 1.1 Host */
40
+
#define IBM_CPM_FPU 0x04000000 /* floating point unit */
41
+
#define IBM_CPM_CPU 0x02000000 /* processor core */
42
+
#define IBM_CPM_DMA 0x01000000 /* DMA controller */
43
+
#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
44
+
#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
45
+
#define IBM_CPM_EBC 0x00200000 /* External Bus Controller */
46
+
#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
47
+
#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
48
+
#define IBM_CPM_PLB4 0x00040000 /* PLB4 bus arbiter */
49
+
#define IBM_CPM_PLB4x3 0x00020000 /* PLB4 to PLB3 bridge controller */
50
+
#define IBM_CPM_PLB3x4 0x00010000 /* PLB3 to PLB4 bridge controller */
51
+
#define IBM_CPM_PLB3 0x00008000 /* PLB3 bus arbiter */
52
+
#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
53
+
#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
54
+
#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
55
+
#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
56
+
#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
57
+
#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
58
+
#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
59
+
#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
60
+
#define IBM_CPM_EMAC0 0x00000020 /* ethernet port 0 */
61
+
#define IBM_CPM_EMAC1 0x00000010 /* ethernet port 1 */
62
+
#define IBM_CPM_UART2 0x00000008 /* serial port 2 */
63
+
#define IBM_CPM_UART3 0x00000004 /* serial port 3 */
64
+
#define IBM_CPM_USB2D 0x00000002 /* USB 2.0 Device */
65
+
#define IBM_CPM_USB2H 0x00000001 /* USB 2.0 Host */
66
+
67
+
#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
68
+
| IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \
69
+
| IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \
70
+
| IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \
71
+
| IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \
72
+
| IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1)
73
+
74
+
75
+
#endif /* __PPC_PLATFORMS_IBM440EP_H */
76
+
#endif /* __KERNEL__ */
+2
arch/ppc/syslib/Makefile
+2
arch/ppc/syslib/Makefile
···
11
obj-$(CONFIG_PPC_OCP) += ocp.o
12
obj-$(CONFIG_IBM_OCP) += ibm_ocp.o
13
obj-$(CONFIG_44x) += ibm44x_common.o
14
obj-$(CONFIG_440GP) += ibm440gp_common.o
15
obj-$(CONFIG_440GX) += ibm440gx_common.o
16
obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
···
45
obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o
46
obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
47
todc_time.o
48
obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
49
obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
50
obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
···
11
obj-$(CONFIG_PPC_OCP) += ocp.o
12
obj-$(CONFIG_IBM_OCP) += ibm_ocp.o
13
obj-$(CONFIG_44x) += ibm44x_common.o
14
+
obj-$(CONFIG_440EP) += ibm440gx_common.o
15
obj-$(CONFIG_440GP) += ibm440gp_common.o
16
obj-$(CONFIG_440GX) += ibm440gx_common.o
17
obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
···
44
obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o
45
obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
46
todc_time.o
47
+
obj-$(CONFIG_BAMBOO) += indirect_pci.o pci_auto.o todc_time.o
48
obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
49
obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
50
obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
+15
arch/ppc/syslib/ibm440gx_common.c
+15
arch/ppc/syslib/ibm440gx_common.c
···
34
u32 plld = CPR_READ(DCRN_CPR_PLLD);
35
u32 uart0 = SDR_READ(DCRN_SDR_UART0);
36
u32 uart1 = SDR_READ(DCRN_SDR_UART1);
37
38
/* Dividers */
39
u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
···
100
p->uart1 = ser_clk;
101
else
102
p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
103
}
104
105
/* Issue L2C diagnostic command */
···
34
u32 plld = CPR_READ(DCRN_CPR_PLLD);
35
u32 uart0 = SDR_READ(DCRN_SDR_UART0);
36
u32 uart1 = SDR_READ(DCRN_SDR_UART1);
37
+
#ifdef CONFIG_440EP
38
+
u32 uart2 = SDR_READ(DCRN_SDR_UART2);
39
+
u32 uart3 = SDR_READ(DCRN_SDR_UART3);
40
+
#endif
41
42
/* Dividers */
43
u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
···
96
p->uart1 = ser_clk;
97
else
98
p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
99
+
#ifdef CONFIG_440EP
100
+
if (uart2 & 0x00800000)
101
+
p->uart2 = ser_clk;
102
+
else
103
+
p->uart2 = p->plb / __fix_zero(uart2 & 0xff, 256);
104
+
105
+
if (uart3 & 0x00800000)
106
+
p->uart3 = ser_clk;
107
+
else
108
+
p->uart3 = p->plb / __fix_zero(uart3 & 0xff, 256);
109
+
#endif
110
}
111
112
/* Issue L2C diagnostic command */
+4
arch/ppc/syslib/ibm44x_common.h
+4
arch/ppc/syslib/ibm44x_common.h
+31
-3
include/asm-ppc/ibm44x.h
+31
-3
include/asm-ppc/ibm44x.h
···
35
#define PPC44x_LOW_SLOT 63
36
37
/* LS 32-bits of UART0 physical address location for early serial text debug */
38
-
#ifdef CONFIG_440SP
39
#define UART0_PHYS_IO_BASE 0xf0000200
40
#else
41
#define UART0_PHYS_IO_BASE 0x40000200
42
#endif
···
51
/*
52
* Standard 4GB "page" definitions
53
*/
54
-
#ifdef CONFIG_440SP
55
#define PPC44x_IO_PAGE 0x0000000100000000ULL
56
#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
57
#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
58
#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
59
#else
60
#define PPC44x_IO_PAGE 0x0000000100000000ULL
61
#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
···
71
/*
72
* 36-bit trap ranges
73
*/
74
-
#ifdef CONFIG_440SP
75
#define PPC44x_IO_LO 0xf0000000UL
76
#define PPC44x_IO_HI 0xf0000fffUL
77
#define PPC44x_PCI0CFG_LO 0x0ec00000UL
···
81
#define PPC44x_PCI2CFG_LO 0x2ec00000UL
82
#define PPC44x_PCI2CFG_HI 0x2ec00007UL
83
#define PPC44x_PCIMEM_LO 0x80000000UL
84
#define PPC44x_PCIMEM_HI 0xdfffffffUL
85
#else
86
#define PPC44x_IO_LO 0x40000000UL
···
166
#define DCRN_SDR_UART0 0x0120
167
#define DCRN_SDR_UART1 0x0121
168
169
/* SDR read/write helper macros */
170
#define SDR_READ(offset) ({\
171
mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
···
188
#define DCRN_DMASR_BASE 0x120
189
#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
190
#define DCRN_MAL_BASE 0x180
191
192
/* UIC */
193
#define DCRN_UIC0_BASE 0xc0
···
35
#define PPC44x_LOW_SLOT 63
36
37
/* LS 32-bits of UART0 physical address location for early serial text debug */
38
+
#if defined(CONFIG_440SP)
39
#define UART0_PHYS_IO_BASE 0xf0000200
40
+
#elif defined(CONFIG_440EP)
41
+
#define UART0_PHYS_IO_BASE 0xe0000000
42
#else
43
#define UART0_PHYS_IO_BASE 0x40000200
44
#endif
···
49
/*
50
* Standard 4GB "page" definitions
51
*/
52
+
#if defined(CONFIG_440SP)
53
#define PPC44x_IO_PAGE 0x0000000100000000ULL
54
#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
55
#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
56
#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
57
+
#elif defined(CONFIG_440EP)
58
+
#define PPC44x_IO_PAGE 0x0000000000000000ULL
59
+
#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
60
+
#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
61
+
#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL
62
#else
63
#define PPC44x_IO_PAGE 0x0000000100000000ULL
64
#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
···
64
/*
65
* 36-bit trap ranges
66
*/
67
+
#if defined(CONFIG_440SP)
68
#define PPC44x_IO_LO 0xf0000000UL
69
#define PPC44x_IO_HI 0xf0000fffUL
70
#define PPC44x_PCI0CFG_LO 0x0ec00000UL
···
74
#define PPC44x_PCI2CFG_LO 0x2ec00000UL
75
#define PPC44x_PCI2CFG_HI 0x2ec00007UL
76
#define PPC44x_PCIMEM_LO 0x80000000UL
77
+
#define PPC44x_PCIMEM_HI 0xdfffffffUL
78
+
#elif defined(CONFIG_440EP)
79
+
#define PPC44x_IO_LO 0xef500000UL
80
+
#define PPC44x_IO_HI 0xefffffffUL
81
+
#define PPC44x_PCI0CFG_LO 0xeec00000UL
82
+
#define PPC44x_PCI0CFG_HI 0xeecfffffUL
83
+
#define PPC44x_PCIMEM_LO 0xa0000000UL
84
#define PPC44x_PCIMEM_HI 0xdfffffffUL
85
#else
86
#define PPC44x_IO_LO 0x40000000UL
···
152
#define DCRN_SDR_UART0 0x0120
153
#define DCRN_SDR_UART1 0x0121
154
155
+
#ifdef CONFIG_440EP
156
+
#define DCRN_SDR_UART2 0x0122
157
+
#define DCRN_SDR_UART3 0x0123
158
+
#define DCRN_SDR_CUST0 0x4000
159
+
#endif
160
+
161
/* SDR read/write helper macros */
162
#define SDR_READ(offset) ({\
163
mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
···
168
#define DCRN_DMASR_BASE 0x120
169
#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
170
#define DCRN_MAL_BASE 0x180
171
+
172
+
#ifdef CONFIG_440EP
173
+
#define DCRN_DMA2P40_BASE 0x300
174
+
#define DCRN_DMA2P41_BASE 0x308
175
+
#define DCRN_DMA2P42_BASE 0x310
176
+
#define DCRN_DMA2P43_BASE 0x318
177
+
#define DCRN_DMA2P4SR_BASE 0x320
178
+
#endif
179
180
/* UIC */
181
#define DCRN_UIC0_BASE 0xc0
+4
include/asm-ppc/ibm4xx.h
+4
include/asm-ppc/ibm4xx.h
+6
include/asm-ppc/ppc_asm.h
+6
include/asm-ppc/ppc_asm.h