tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/i915/display: convert the M/N functions to struct intel_display

Going forward, struct intel_display is the main display device data
pointer. Convert the functions to set/get M/N values and check for M2/N2
support to struct intel_display.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/8ac3472fe8e6647c0da57013c8bef575d8324a88.1740502116.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Jani Nikula c9c672db 8266c817

+59 -62
+44 -44
drivers/gpu/drm/i915/display/intel_display.c
··· 2662 2662 m_n->tu = 1; 2663 2663 } 2664 2664 2665 - void intel_set_m_n(struct drm_i915_private *i915, 2665 + void intel_set_m_n(struct intel_display *display, 2666 2666 const struct intel_link_m_n *m_n, 2667 2667 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2668 2668 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2669 2669 { 2670 - intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2671 - intel_de_write(i915, data_n_reg, m_n->data_n); 2672 - intel_de_write(i915, link_m_reg, m_n->link_m); 2670 + intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2671 + intel_de_write(display, data_n_reg, m_n->data_n); 2672 + intel_de_write(display, link_m_reg, m_n->link_m); 2673 2673 /* 2674 2674 * On BDW+ writing LINK_N arms the double buffered update 2675 2675 * of all the M/N registers, so it must be written last. 2676 2676 */ 2677 - intel_de_write(i915, link_n_reg, m_n->link_n); 2677 + intel_de_write(display, link_n_reg, m_n->link_n); 2678 2678 } 2679 2679 2680 - bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2680 + bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, 2681 2681 enum transcoder transcoder) 2682 2682 { 2683 - if (IS_HASWELL(dev_priv)) 2683 + if (display->platform.haswell) 2684 2684 return transcoder == TRANSCODER_EDP; 2685 2685 2686 - return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2686 + return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview; 2687 2687 } 2688 2688 2689 2689 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2690 2690 enum transcoder transcoder, 2691 2691 const struct intel_link_m_n *m_n) 2692 2692 { 2693 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2693 + struct intel_display *display = to_intel_display(crtc); 2694 2694 enum pipe pipe = crtc->pipe; 2695 2695 2696 - if (DISPLAY_VER(dev_priv) >= 5) 2697 - intel_set_m_n(dev_priv, m_n, 2698 - PIPE_DATA_M1(dev_priv, transcoder), 2699 - PIPE_DATA_N1(dev_priv, transcoder), 2700 - PIPE_LINK_M1(dev_priv, transcoder), 2701 - PIPE_LINK_N1(dev_priv, transcoder)); 2696 + if (DISPLAY_VER(display) >= 5) 2697 + intel_set_m_n(display, m_n, 2698 + PIPE_DATA_M1(display, transcoder), 2699 + PIPE_DATA_N1(display, transcoder), 2700 + PIPE_LINK_M1(display, transcoder), 2701 + PIPE_LINK_N1(display, transcoder)); 2702 2702 else 2703 - intel_set_m_n(dev_priv, m_n, 2703 + intel_set_m_n(display, m_n, 2704 2704 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2705 2705 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2706 2706 } ··· 2709 2709 enum transcoder transcoder, 2710 2710 const struct intel_link_m_n *m_n) 2711 2711 { 2712 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2712 + struct intel_display *display = to_intel_display(crtc); 2713 2713 2714 - if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2714 + if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) 2715 2715 return; 2716 2716 2717 - intel_set_m_n(dev_priv, m_n, 2718 - PIPE_DATA_M2(dev_priv, transcoder), 2719 - PIPE_DATA_N2(dev_priv, transcoder), 2720 - PIPE_LINK_M2(dev_priv, transcoder), 2721 - PIPE_LINK_N2(dev_priv, transcoder)); 2717 + intel_set_m_n(display, m_n, 2718 + PIPE_DATA_M2(display, transcoder), 2719 + PIPE_DATA_N2(display, transcoder), 2720 + PIPE_LINK_M2(display, transcoder), 2721 + PIPE_LINK_N2(display, transcoder)); 2722 2722 } 2723 2723 2724 2724 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) ··· 3404 3404 return DIV_ROUND_UP(bps, link_bw * 8); 3405 3405 } 3406 3406 3407 - void intel_get_m_n(struct drm_i915_private *i915, 3407 + void intel_get_m_n(struct intel_display *display, 3408 3408 struct intel_link_m_n *m_n, 3409 3409 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3410 3410 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3411 3411 { 3412 - m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3413 - m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3414 - m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3415 - m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3416 - m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3412 + m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK; 3413 + m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK; 3414 + m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK; 3415 + m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK; 3416 + m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1; 3417 3417 } 3418 3418 3419 3419 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3420 3420 enum transcoder transcoder, 3421 3421 struct intel_link_m_n *m_n) 3422 3422 { 3423 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3423 + struct intel_display *display = to_intel_display(crtc); 3424 3424 enum pipe pipe = crtc->pipe; 3425 3425 3426 - if (DISPLAY_VER(dev_priv) >= 5) 3427 - intel_get_m_n(dev_priv, m_n, 3428 - PIPE_DATA_M1(dev_priv, transcoder), 3429 - PIPE_DATA_N1(dev_priv, transcoder), 3430 - PIPE_LINK_M1(dev_priv, transcoder), 3431 - PIPE_LINK_N1(dev_priv, transcoder)); 3426 + if (DISPLAY_VER(display) >= 5) 3427 + intel_get_m_n(display, m_n, 3428 + PIPE_DATA_M1(display, transcoder), 3429 + PIPE_DATA_N1(display, transcoder), 3430 + PIPE_LINK_M1(display, transcoder), 3431 + PIPE_LINK_N1(display, transcoder)); 3432 3432 else 3433 - intel_get_m_n(dev_priv, m_n, 3433 + intel_get_m_n(display, m_n, 3434 3434 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3435 3435 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3436 3436 } ··· 3439 3439 enum transcoder transcoder, 3440 3440 struct intel_link_m_n *m_n) 3441 3441 { 3442 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3442 + struct intel_display *display = to_intel_display(crtc); 3443 3443 3444 - if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3444 + if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) 3445 3445 return; 3446 3446 3447 - intel_get_m_n(dev_priv, m_n, 3448 - PIPE_DATA_M2(dev_priv, transcoder), 3449 - PIPE_DATA_N2(dev_priv, transcoder), 3450 - PIPE_LINK_M2(dev_priv, transcoder), 3451 - PIPE_LINK_N2(dev_priv, transcoder)); 3447 + intel_get_m_n(display, m_n, 3448 + PIPE_DATA_M2(display, transcoder), 3449 + PIPE_DATA_N2(display, transcoder), 3450 + PIPE_LINK_M2(display, transcoder), 3451 + PIPE_LINK_N2(display, transcoder)); 3452 3452 } 3453 3453 3454 3454 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
+3 -3
drivers/gpu/drm/i915/display/intel_display.h
··· 481 481 bool intel_fuzzy_clock_check(int clock1, int clock2); 482 482 483 483 void intel_zero_m_n(struct intel_link_m_n *m_n); 484 - void intel_set_m_n(struct drm_i915_private *i915, 484 + void intel_set_m_n(struct intel_display *display, 485 485 const struct intel_link_m_n *m_n, 486 486 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 487 487 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 488 - void intel_get_m_n(struct drm_i915_private *i915, 488 + void intel_get_m_n(struct intel_display *display, 489 489 struct intel_link_m_n *m_n, 490 490 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 491 491 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 492 - bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 492 + bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, 493 493 enum transcoder transcoder); 494 494 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 495 495 enum transcoder cpu_transcoder,
+1 -2
drivers/gpu/drm/i915/display/intel_dp.c
··· 2943 2943 int link_bpp_x16) 2944 2944 { 2945 2945 struct intel_display *display = to_intel_display(connector); 2946 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 2947 2946 const struct drm_display_mode *downclock_mode = 2948 2947 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); 2949 2948 int pixel_clock; ··· 2955 2956 pipe_config->update_m_n = true; 2956 2957 2957 2958 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { 2958 - if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) 2959 + if (intel_cpu_transcoder_has_m2_n2(display, pipe_config->cpu_transcoder)) 2959 2960 intel_zero_m_n(&pipe_config->dp_m2_n2); 2960 2961 return; 2961 2962 }
+3 -5
drivers/gpu/drm/i915/display/intel_drrs.c
··· 68 68 bool intel_cpu_transcoder_has_drrs(struct intel_display *display, 69 69 enum transcoder cpu_transcoder) 70 70 { 71 - struct drm_i915_private *i915 = to_i915(display->drm); 72 - 73 71 if (HAS_DOUBLE_BUFFERED_M_N(display)) 74 72 return true; 75 73 76 - return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder); 74 + return intel_cpu_transcoder_has_m2_n2(display, cpu_transcoder); 77 75 } 78 76 79 77 static void ··· 108 110 static void intel_drrs_set_state(struct intel_crtc *crtc, 109 111 enum drrs_refresh_rate refresh_rate) 110 112 { 111 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 113 + struct intel_display *display = to_intel_display(crtc); 112 114 113 115 if (refresh_rate == crtc->drrs.refresh_rate) 114 116 return; 115 117 116 - if (intel_cpu_transcoder_has_m2_n2(dev_priv, crtc->drrs.cpu_transcoder)) 118 + if (intel_cpu_transcoder_has_m2_n2(display, crtc->drrs.cpu_transcoder)) 117 119 intel_drrs_set_refresh_rate_pipeconf(crtc, refresh_rate); 118 120 else 119 121 intel_drrs_set_refresh_rate_m_n(crtc, refresh_rate);
+8 -8
drivers/gpu/drm/i915/display/intel_pch_display.c
··· 181 181 static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc, 182 182 const struct intel_link_m_n *m_n) 183 183 { 184 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 184 + struct intel_display *display = to_intel_display(crtc); 185 185 enum pipe pipe = crtc->pipe; 186 186 187 - intel_set_m_n(dev_priv, m_n, 187 + intel_set_m_n(display, m_n, 188 188 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), 189 189 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); 190 190 } ··· 192 192 static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc, 193 193 const struct intel_link_m_n *m_n) 194 194 { 195 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 195 + struct intel_display *display = to_intel_display(crtc); 196 196 enum pipe pipe = crtc->pipe; 197 197 198 - intel_set_m_n(dev_priv, m_n, 198 + intel_set_m_n(display, m_n, 199 199 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), 200 200 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); 201 201 } ··· 203 203 void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc, 204 204 struct intel_link_m_n *m_n) 205 205 { 206 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 206 + struct intel_display *display = to_intel_display(crtc); 207 207 enum pipe pipe = crtc->pipe; 208 208 209 - intel_get_m_n(dev_priv, m_n, 209 + intel_get_m_n(display, m_n, 210 210 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), 211 211 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); 212 212 } ··· 214 214 void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc, 215 215 struct intel_link_m_n *m_n) 216 216 { 217 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 217 + struct intel_display *display = to_intel_display(crtc); 218 218 enum pipe pipe = crtc->pipe; 219 219 220 - intel_get_m_n(dev_priv, m_n, 220 + intel_get_m_n(display, m_n, 221 221 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), 222 222 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); 223 223 }