tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

ARM: dts: uniphier: Use GIC interrupt definitions

Use human-readable definitions for GIC interrupt type and flag, instead of
hard-coding the numbers. No functional change.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042249.4708-6-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

authored by

Kunihiko Hayashi and committed by
Arnd Bergmann c9c50dfd 888c7017

+163 -121
+2 -2
arch/arm/boot/dts/uniphier-ld4-ref.dts
··· 36 36 }; 37 37 38 38 &ethsc { 39 - interrupts = <1 8>; 39 + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 40 40 }; 41 41 42 42 &serialsc { 43 - interrupts = <1 8>; 43 + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 44 44 }; 45 45 46 46 &serial0 {
+29 -20
arch/arm/boot/dts/uniphier-ld4.dtsi
··· 6 6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 7 8 8 #include <dt-bindings/gpio/uniphier-gpio.h> 9 + #include <dt-bindings/interrupt-controller/arm-gic.h> 9 10 10 11 / { 11 12 compatible = "socionext,uniphier-ld4"; ··· 56 55 compatible = "socionext,uniphier-system-cache"; 57 56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 58 57 <0x506c0000 0x400>; 59 - interrupts = <0 174 4>, <0 175 4>; 58 + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 59 + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 60 60 cache-unified; 61 61 cache-size = <(512 * 1024)>; 62 62 cache-sets = <256>; ··· 71 69 reg = <0x54006000 0x100>; 72 70 #address-cells = <1>; 73 71 #size-cells = <0>; 74 - interrupts = <0 39 4>; 72 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 75 73 pinctrl-names = "default"; 76 74 pinctrl-0 = <&pinctrl_spi0>; 77 75 clocks = <&peri_clk 11>; ··· 82 80 compatible = "socionext,uniphier-uart"; 83 81 status = "disabled"; 84 82 reg = <0x54006800 0x40>; 85 - interrupts = <0 33 4>; 83 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 86 84 pinctrl-names = "default"; 87 85 pinctrl-0 = <&pinctrl_uart0>; 88 86 clocks = <&peri_clk 0>; ··· 93 91 compatible = "socionext,uniphier-uart"; 94 92 status = "disabled"; 95 93 reg = <0x54006900 0x40>; 96 - interrupts = <0 35 4>; 94 + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 97 95 pinctrl-names = "default"; 98 96 pinctrl-0 = <&pinctrl_uart1>; 99 97 clocks = <&peri_clk 1>; ··· 104 102 compatible = "socionext,uniphier-uart"; 105 103 status = "disabled"; 106 104 reg = <0x54006a00 0x40>; 107 - interrupts = <0 37 4>; 105 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 108 106 pinctrl-names = "default"; 109 107 pinctrl-0 = <&pinctrl_uart2>; 110 108 clocks = <&peri_clk 2>; ··· 115 113 compatible = "socionext,uniphier-uart"; 116 114 status = "disabled"; 117 115 reg = <0x54006b00 0x40>; 118 - interrupts = <0 29 4>; 116 + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 119 117 pinctrl-names = "default"; 120 118 pinctrl-0 = <&pinctrl_uart3>; 121 119 clocks = <&peri_clk 3>; ··· 142 140 reg = <0x58400000 0x40>; 143 141 #address-cells = <1>; 144 142 #size-cells = <0>; 145 - interrupts = <0 41 1>; 143 + interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>; 146 144 pinctrl-names = "default"; 147 145 pinctrl-0 = <&pinctrl_i2c0>; 148 146 clocks = <&peri_clk 4>; ··· 156 154 reg = <0x58480000 0x40>; 157 155 #address-cells = <1>; 158 156 #size-cells = <0>; 159 - interrupts = <0 42 1>; 157 + interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>; 160 158 pinctrl-names = "default"; 161 159 pinctrl-0 = <&pinctrl_i2c1>; 162 160 clocks = <&peri_clk 5>; ··· 170 168 reg = <0x58500000 0x40>; 171 169 #address-cells = <1>; 172 170 #size-cells = <0>; 173 - interrupts = <0 43 1>; 171 + interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>; 174 172 pinctrl-names = "default"; 175 173 pinctrl-0 = <&pinctrl_i2c2>; 176 174 clocks = <&peri_clk 6>; ··· 184 182 reg = <0x58580000 0x40>; 185 183 #address-cells = <1>; 186 184 #size-cells = <0>; 187 - interrupts = <0 44 1>; 185 + interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>; 188 186 pinctrl-names = "default"; 189 187 pinctrl-0 = <&pinctrl_i2c3>; 190 188 clocks = <&peri_clk 7>; ··· 242 240 dmac: dma-controller@5a000000 { 243 241 compatible = "socionext,uniphier-mio-dmac"; 244 242 reg = <0x5a000000 0x1000>; 245 - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, 246 - <0 71 4>, <0 72 4>, <0 73 4>; 243 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 244 + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 245 + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 246 + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 247 + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 248 + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 249 + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 247 250 clocks = <&mio_clk 7>; 248 251 resets = <&mio_rst 7>; 249 252 #dma-cells = <1>; ··· 258 251 compatible = "socionext,uniphier-sd-v2.91"; 259 252 status = "disabled"; 260 253 reg = <0x5a400000 0x200>; 261 - interrupts = <0 76 4>; 254 + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 262 255 pinctrl-names = "default", "uhs"; 263 256 pinctrl-0 = <&pinctrl_sd>; 264 257 pinctrl-1 = <&pinctrl_sd_uhs>; ··· 278 271 compatible = "socionext,uniphier-sd-v2.91"; 279 272 status = "disabled"; 280 273 reg = <0x5a500000 0x200>; 281 - interrupts = <0 78 4>; 274 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 282 275 pinctrl-names = "default"; 283 276 pinctrl-0 = <&pinctrl_emmc>; 284 277 clocks = <&mio_clk 1>; ··· 296 289 compatible = "socionext,uniphier-ehci", "generic-ehci"; 297 290 status = "disabled"; 298 291 reg = <0x5a800100 0x100>; 299 - interrupts = <0 80 4>; 292 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 300 293 pinctrl-names = "default"; 301 294 pinctrl-0 = <&pinctrl_usb0>; 302 295 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, ··· 310 303 compatible = "socionext,uniphier-ehci", "generic-ehci"; 311 304 status = "disabled"; 312 305 reg = <0x5a810100 0x100>; 313 - interrupts = <0 81 4>; 306 + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 314 307 pinctrl-names = "default"; 315 308 pinctrl-0 = <&pinctrl_usb1>; 316 309 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, ··· 324 317 compatible = "socionext,uniphier-ehci", "generic-ehci"; 325 318 status = "disabled"; 326 319 reg = <0x5a820100 0x100>; 327 - interrupts = <0 82 4>; 320 + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 328 321 pinctrl-names = "default"; 329 322 pinctrl-0 = <&pinctrl_usb2>; 330 323 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, ··· 365 358 timer@60000200 { 366 359 compatible = "arm,cortex-a9-global-timer"; 367 360 reg = <0x60000200 0x20>; 368 - interrupts = <1 11 0x104>; 361 + interrupts = <GIC_PPI 11 362 + (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; 369 363 clocks = <&arm_timer_clk>; 370 364 }; 371 365 372 366 timer@60000600 { 373 367 compatible = "arm,cortex-a9-twd-timer"; 374 368 reg = <0x60000600 0x20>; 375 - interrupts = <1 13 0x104>; 369 + interrupts = <GIC_PPI 13 370 + (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; 376 371 clocks = <&arm_timer_clk>; 377 372 }; 378 373 ··· 416 407 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 417 408 #address-cells = <1>; 418 409 #size-cells = <0>; 419 - interrupts = <0 65 4>; 410 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 420 411 pinctrl-names = "default"; 421 412 pinctrl-0 = <&pinctrl_nand>; 422 413 clock-names = "nand", "nand_x", "ecc";
+2 -2
arch/arm/boot/dts/uniphier-ld6b-ref.dts
··· 40 40 }; 41 41 42 42 &ethsc { 43 - interrupts = <4 8>; 43 + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 44 44 }; 45 45 46 46 &serialsc { 47 - interrupts = <4 8>; 47 + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 48 48 }; 49 49 50 50 &serial0 {
+2 -2
arch/arm/boot/dts/uniphier-pro4-ref.dts
··· 39 39 }; 40 40 41 41 &ethsc { 42 - interrupts = <2 8>; 42 + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 43 43 }; 44 44 45 45 &serialsc { 46 - interrupts = <2 8>; 46 + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 47 47 }; 48 48 49 49 &serial0 {
+38 -26
arch/arm/boot/dts/uniphier-pro4.dtsi
··· 6 6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 7 8 8 #include <dt-bindings/gpio/uniphier-gpio.h> 9 + #include <dt-bindings/interrupt-controller/arm-gic.h> 9 10 10 11 / { 11 12 compatible = "socionext,uniphier-pro4"; ··· 64 63 compatible = "socionext,uniphier-system-cache"; 65 64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 66 65 <0x506c0000 0x400>; 67 - interrupts = <0 174 4>, <0 175 4>; 66 + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 67 + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 68 68 cache-unified; 69 69 cache-size = <(768 * 1024)>; 70 70 cache-sets = <256>; ··· 79 77 reg = <0x54006000 0x100>; 80 78 #address-cells = <1>; 81 79 #size-cells = <0>; 82 - interrupts = <0 39 4>; 80 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 83 81 pinctrl-names = "default"; 84 82 pinctrl-0 = <&pinctrl_spi0>; 85 83 clocks = <&peri_clk 11>; ··· 90 88 compatible = "socionext,uniphier-uart"; 91 89 status = "disabled"; 92 90 reg = <0x54006800 0x40>; 93 - interrupts = <0 33 4>; 91 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 94 92 pinctrl-names = "default"; 95 93 pinctrl-0 = <&pinctrl_uart0>; 96 94 clocks = <&peri_clk 0>; ··· 101 99 compatible = "socionext,uniphier-uart"; 102 100 status = "disabled"; 103 101 reg = <0x54006900 0x40>; 104 - interrupts = <0 35 4>; 102 + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 105 103 pinctrl-names = "default"; 106 104 pinctrl-0 = <&pinctrl_uart1>; 107 105 clocks = <&peri_clk 1>; ··· 112 110 compatible = "socionext,uniphier-uart"; 113 111 status = "disabled"; 114 112 reg = <0x54006a00 0x40>; 115 - interrupts = <0 37 4>; 113 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 116 114 pinctrl-names = "default"; 117 115 pinctrl-0 = <&pinctrl_uart2>; 118 116 clocks = <&peri_clk 2>; ··· 123 121 compatible = "socionext,uniphier-uart"; 124 122 status = "disabled"; 125 123 reg = <0x54006b00 0x40>; 126 - interrupts = <0 177 4>; 124 + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 127 125 pinctrl-names = "default"; 128 126 pinctrl-0 = <&pinctrl_uart3>; 129 127 clocks = <&peri_clk 3>; ··· 150 148 reg = <0x58780000 0x80>; 151 149 #address-cells = <1>; 152 150 #size-cells = <0>; 153 - interrupts = <0 41 4>; 151 + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 154 152 pinctrl-names = "default"; 155 153 pinctrl-0 = <&pinctrl_i2c0>; 156 154 clocks = <&peri_clk 4>; ··· 164 162 reg = <0x58781000 0x80>; 165 163 #address-cells = <1>; 166 164 #size-cells = <0>; 167 - interrupts = <0 42 4>; 165 + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 168 166 pinctrl-names = "default"; 169 167 pinctrl-0 = <&pinctrl_i2c1>; 170 168 clocks = <&peri_clk 5>; ··· 178 176 reg = <0x58782000 0x80>; 179 177 #address-cells = <1>; 180 178 #size-cells = <0>; 181 - interrupts = <0 43 4>; 179 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 182 180 pinctrl-names = "default"; 183 181 pinctrl-0 = <&pinctrl_i2c2>; 184 182 clocks = <&peri_clk 6>; ··· 192 190 reg = <0x58783000 0x80>; 193 191 #address-cells = <1>; 194 192 #size-cells = <0>; 195 - interrupts = <0 44 4>; 193 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 196 194 pinctrl-names = "default"; 197 195 pinctrl-0 = <&pinctrl_i2c3>; 198 196 clocks = <&peri_clk 7>; ··· 208 206 reg = <0x58785000 0x80>; 209 207 #address-cells = <1>; 210 208 #size-cells = <0>; 211 - interrupts = <0 25 4>; 209 + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 212 210 clocks = <&peri_clk 9>; 213 211 resets = <&peri_rst 9>; 214 212 clock-frequency = <400000>; ··· 220 218 reg = <0x58786000 0x80>; 221 219 #address-cells = <1>; 222 220 #size-cells = <0>; 223 - interrupts = <0 26 4>; 221 + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 224 222 clocks = <&peri_clk 10>; 225 223 resets = <&peri_rst 10>; 226 224 clock-frequency = <400000>; ··· 276 274 dmac: dma-controller@5a000000 { 277 275 compatible = "socionext,uniphier-mio-dmac"; 278 276 reg = <0x5a000000 0x1000>; 279 - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, 280 - <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; 277 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 278 + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 279 + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 280 + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 281 + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 282 + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 283 + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 284 + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 281 285 clocks = <&mio_clk 7>; 282 286 resets = <&mio_rst 7>; 283 287 #dma-cells = <1>; ··· 293 285 compatible = "socionext,uniphier-sd-v2.91"; 294 286 status = "disabled"; 295 287 reg = <0x5a400000 0x200>; 296 - interrupts = <0 76 4>; 288 + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 297 289 pinctrl-names = "default", "uhs"; 298 290 pinctrl-0 = <&pinctrl_sd>; 299 291 pinctrl-1 = <&pinctrl_sd_uhs>; ··· 313 305 compatible = "socionext,uniphier-sd-v2.91"; 314 306 status = "disabled"; 315 307 reg = <0x5a500000 0x200>; 316 - interrupts = <0 78 4>; 308 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 317 309 pinctrl-names = "default"; 318 310 pinctrl-0 = <&pinctrl_emmc>; 319 311 clocks = <&mio_clk 1>; ··· 331 323 compatible = "socionext,uniphier-sd-v2.91"; 332 324 status = "disabled"; 333 325 reg = <0x5a600000 0x200>; 334 - interrupts = <0 85 4>; 326 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 335 327 pinctrl-names = "default"; 336 328 pinctrl-0 = <&pinctrl_sd1>; 337 329 clocks = <&mio_clk 2>; ··· 347 339 compatible = "socionext,uniphier-ehci", "generic-ehci"; 348 340 status = "disabled"; 349 341 reg = <0x5a800100 0x100>; 350 - interrupts = <0 80 4>; 342 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 351 343 pinctrl-names = "default"; 352 344 pinctrl-0 = <&pinctrl_usb2>; 353 345 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, ··· 363 355 compatible = "socionext,uniphier-ehci", "generic-ehci"; 364 356 status = "disabled"; 365 357 reg = <0x5a810100 0x100>; 366 - interrupts = <0 81 4>; 358 + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 367 359 pinctrl-names = "default"; 368 360 pinctrl-0 = <&pinctrl_usb3>; 369 361 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, ··· 439 431 xdmac: dma-controller@5fc10000 { 440 432 compatible = "socionext,uniphier-xdmac"; 441 433 reg = <0x5fc10000 0x5300>; 442 - interrupts = <0 188 4>; 434 + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 443 435 dma-channels = <16>; 444 436 #dma-cells = <2>; 445 437 }; ··· 454 446 timer@60000200 { 455 447 compatible = "arm,cortex-a9-global-timer"; 456 448 reg = <0x60000200 0x20>; 457 - interrupts = <1 11 0x304>; 449 + interrupts = <GIC_PPI 11 450 + (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 458 451 clocks = <&arm_timer_clk>; 459 452 }; 460 453 461 454 timer@60000600 { 462 455 compatible = "arm,cortex-a9-twd-timer"; 463 456 reg = <0x60000600 0x20>; 464 - interrupts = <1 13 0x304>; 457 + interrupts = <GIC_PPI 13 458 + (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 465 459 clocks = <&arm_timer_clk>; 466 460 }; 467 461 ··· 495 485 compatible = "socionext,uniphier-pro4-ave4"; 496 486 status = "disabled"; 497 487 reg = <0x65000000 0x8500>; 498 - interrupts = <0 66 4>; 488 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 499 489 pinctrl-names = "default"; 500 490 pinctrl-0 = <&pinctrl_ether_rgmii>; 501 491 clock-names = "gio", "ether", "ether-gb", "ether-phy"; ··· 518 508 status = "disabled"; 519 509 reg = <0x65a00000 0xcd00>; 520 510 interrupt-names = "host", "peripheral"; 521 - interrupts = <0 134 4>, <0 135 4>; 511 + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 512 + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 522 513 pinctrl-names = "default"; 523 514 pinctrl-0 = <&pinctrl_usb0>; 524 515 clock-names = "ref", "bus_early", "suspend"; ··· 572 561 status = "disabled"; 573 562 reg = <0x65c00000 0xcd00>; 574 563 interrupt-names = "host", "peripheral"; 575 - interrupts = <0 137 4>, <0 138 4>; 564 + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 565 + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 576 566 pinctrl-names = "default"; 577 567 pinctrl-0 = <&pinctrl_usb1>; 578 568 clock-names = "ref", "bus_early", "suspend"; ··· 617 605 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 618 606 #address-cells = <1>; 619 607 #size-cells = <0>; 620 - interrupts = <0 65 4>; 608 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 621 609 pinctrl-names = "default"; 622 610 pinctrl-0 = <&pinctrl_nand>; 623 611 clock-names = "nand", "nand_x", "ecc";
+28 -22
arch/arm/boot/dts/uniphier-pro5.dtsi
··· 5 5 // Copyright (C) 2015-2016 Socionext Inc. 6 6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 7 8 + #include <dt-bindings/interrupt-controller/arm-gic.h> 9 + 8 10 / { 9 11 compatible = "socionext,uniphier-pro5"; 10 12 #address-cells = <1>; ··· 137 135 compatible = "socionext,uniphier-system-cache"; 138 136 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 139 137 <0x506c0000 0x400>; 140 - interrupts = <0 190 4>, <0 191 4>; 138 + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 139 + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 141 140 cache-unified; 142 141 cache-size = <(2 * 1024 * 1024)>; 143 142 cache-sets = <512>; ··· 151 148 compatible = "socionext,uniphier-system-cache"; 152 149 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, 153 150 <0x506c8000 0x400>; 154 - interrupts = <0 174 4>, <0 175 4>; 151 + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 152 + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 155 153 cache-unified; 156 154 cache-size = <(2 * 1024 * 1024)>; 157 155 cache-sets = <512>; ··· 166 162 reg = <0x54006000 0x100>; 167 163 #address-cells = <1>; 168 164 #size-cells = <0>; 169 - interrupts = <0 39 4>; 165 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 170 166 pinctrl-names = "default"; 171 167 pinctrl-0 = <&pinctrl_spi0>; 172 168 clocks = <&peri_clk 11>; ··· 179 175 reg = <0x54006100 0x100>; 180 176 #address-cells = <1>; 181 177 #size-cells = <0>; 182 - interrupts = <0 216 4>; 178 + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 183 179 pinctrl-names = "default"; 184 180 pinctrl-0 = <&pinctrl_spi1>; 185 181 clocks = <&peri_clk 11>; /* common with spi0 */ ··· 190 186 compatible = "socionext,uniphier-uart"; 191 187 status = "disabled"; 192 188 reg = <0x54006800 0x40>; 193 - interrupts = <0 33 4>; 189 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 194 190 pinctrl-names = "default"; 195 191 pinctrl-0 = <&pinctrl_uart0>; 196 192 clocks = <&peri_clk 0>; ··· 201 197 compatible = "socionext,uniphier-uart"; 202 198 status = "disabled"; 203 199 reg = <0x54006900 0x40>; 204 - interrupts = <0 35 4>; 200 + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 205 201 pinctrl-names = "default"; 206 202 pinctrl-0 = <&pinctrl_uart1>; 207 203 clocks = <&peri_clk 1>; ··· 212 208 compatible = "socionext,uniphier-uart"; 213 209 status = "disabled"; 214 210 reg = <0x54006a00 0x40>; 215 - interrupts = <0 37 4>; 211 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 216 212 pinctrl-names = "default"; 217 213 pinctrl-0 = <&pinctrl_uart2>; 218 214 clocks = <&peri_clk 2>; ··· 223 219 compatible = "socionext,uniphier-uart"; 224 220 status = "disabled"; 225 221 reg = <0x54006b00 0x40>; 226 - interrupts = <0 177 4>; 222 + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 227 223 pinctrl-names = "default"; 228 224 pinctrl-0 = <&pinctrl_uart3>; 229 225 clocks = <&peri_clk 3>; ··· 250 246 reg = <0x58780000 0x80>; 251 247 #address-cells = <1>; 252 248 #size-cells = <0>; 253 - interrupts = <0 41 4>; 249 + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 254 250 pinctrl-names = "default"; 255 251 pinctrl-0 = <&pinctrl_i2c0>; 256 252 clocks = <&peri_clk 4>; ··· 264 260 reg = <0x58781000 0x80>; 265 261 #address-cells = <1>; 266 262 #size-cells = <0>; 267 - interrupts = <0 42 4>; 263 + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 268 264 pinctrl-names = "default"; 269 265 pinctrl-0 = <&pinctrl_i2c1>; 270 266 clocks = <&peri_clk 5>; ··· 278 274 reg = <0x58782000 0x80>; 279 275 #address-cells = <1>; 280 276 #size-cells = <0>; 281 - interrupts = <0 43 4>; 277 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 282 278 pinctrl-names = "default"; 283 279 pinctrl-0 = <&pinctrl_i2c2>; 284 280 clocks = <&peri_clk 6>; ··· 292 288 reg = <0x58783000 0x80>; 293 289 #address-cells = <1>; 294 290 #size-cells = <0>; 295 - interrupts = <0 44 4>; 291 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 296 292 pinctrl-names = "default"; 297 293 pinctrl-0 = <&pinctrl_i2c3>; 298 294 clocks = <&peri_clk 7>; ··· 308 304 reg = <0x58785000 0x80>; 309 305 #address-cells = <1>; 310 306 #size-cells = <0>; 311 - interrupts = <0 25 4>; 307 + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 312 308 clocks = <&peri_clk 9>; 313 309 resets = <&peri_rst 9>; 314 310 clock-frequency = <400000>; ··· 320 316 reg = <0x58786000 0x80>; 321 317 #address-cells = <1>; 322 318 #size-cells = <0>; 323 - interrupts = <0 26 4>; 319 + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 324 320 clocks = <&peri_clk 10>; 325 321 resets = <&peri_rst 10>; 326 322 clock-frequency = <400000>; ··· 419 415 xdmac: dma-controller@5fc10000 { 420 416 compatible = "socionext,uniphier-xdmac"; 421 417 reg = <0x5fc10000 0x5300>; 422 - interrupts = <0 188 4>; 418 + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 423 419 dma-channels = <16>; 424 420 #dma-cells = <2>; 425 421 }; ··· 434 430 timer@60000200 { 435 431 compatible = "arm,cortex-a9-global-timer"; 436 432 reg = <0x60000200 0x20>; 437 - interrupts = <1 11 0x304>; 433 + interrupts = <GIC_PPI 11 434 + (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 438 435 clocks = <&arm_timer_clk>; 439 436 }; 440 437 441 438 timer@60000600 { 442 439 compatible = "arm,cortex-a9-twd-timer"; 443 440 reg = <0x60000600 0x20>; 444 - interrupts = <1 13 0x304>; 441 + interrupts = <GIC_PPI 13 442 + (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 445 443 clocks = <&arm_timer_clk>; 446 444 }; 447 445 ··· 476 470 status = "disabled"; 477 471 reg = <0x65a00000 0xcd00>; 478 472 interrupt-names = "host"; 479 - interrupts = <0 134 4>; 473 + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 480 474 pinctrl-names = "default"; 481 475 pinctrl-0 = <&pinctrl_usb0>; 482 476 clock-names = "ref", "bus_early", "suspend"; ··· 540 534 status = "disabled"; 541 535 reg = <0x65c00000 0xcd00>; 542 536 interrupt-names = "host"; 543 - interrupts = <0 137 4>; 537 + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 544 538 pinctrl-names = "default"; 545 539 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; 546 540 clock-names = "ref", "bus_early", "suspend"; ··· 656 650 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 657 651 #address-cells = <1>; 658 652 #size-cells = <0>; 659 - interrupts = <0 65 4>; 653 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 660 654 pinctrl-names = "default"; 661 655 pinctrl-0 = <&pinctrl_nand>; 662 656 clock-names = "nand", "nand_x", "ecc"; ··· 669 663 compatible = "socionext,uniphier-sd-v3.1"; 670 664 status = "disabled"; 671 665 reg = <0x68400000 0x800>; 672 - interrupts = <0 78 4>; 666 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 673 667 pinctrl-names = "default"; 674 668 pinctrl-0 = <&pinctrl_emmc>; 675 669 clocks = <&sd_clk 1>; ··· 685 679 compatible = "socionext,uniphier-sd-v3.1"; 686 680 status = "disabled"; 687 681 reg = <0x68800000 0x800>; 688 - interrupts = <0 76 4>; 682 + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 689 683 pinctrl-names = "default", "uhs"; 690 684 pinctrl-0 = <&pinctrl_sd>; 691 685 pinctrl-1 = <&pinctrl_sd_uhs>;
+31 -25
arch/arm/boot/dts/uniphier-pxs2.dtsi
··· 6 6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 7 8 8 #include <dt-bindings/gpio/uniphier-gpio.h> 9 + #include <dt-bindings/interrupt-controller/arm-gic.h> 9 10 #include <dt-bindings/thermal/thermal.h> 10 11 11 12 / { ··· 162 161 compatible = "socionext,uniphier-system-cache"; 163 162 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 164 163 <0x506c0000 0x400>; 165 - interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; 164 + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 165 + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 166 + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 167 + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 166 168 cache-unified; 167 169 cache-size = <(1280 * 1024)>; 168 170 cache-sets = <512>; ··· 179 175 reg = <0x54006000 0x100>; 180 176 #address-cells = <1>; 181 177 #size-cells = <0>; 182 - interrupts = <0 39 4>; 178 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 183 179 pinctrl-names = "default"; 184 180 pinctrl-0 = <&pinctrl_spi0>; 185 181 clocks = <&peri_clk 11>; ··· 192 188 reg = <0x54006100 0x100>; 193 189 #address-cells = <1>; 194 190 #size-cells = <0>; 195 - interrupts = <0 216 4>; 191 + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 196 192 pinctrl-names = "default"; 197 193 pinctrl-0 = <&pinctrl_spi1>; 198 194 clocks = <&peri_clk 12>; ··· 203 199 compatible = "socionext,uniphier-uart"; 204 200 status = "disabled"; 205 201 reg = <0x54006800 0x40>; 206 - interrupts = <0 33 4>; 202 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 207 203 pinctrl-names = "default"; 208 204 pinctrl-0 = <&pinctrl_uart0>; 209 205 clocks = <&peri_clk 0>; ··· 214 210 compatible = "socionext,uniphier-uart"; 215 211 status = "disabled"; 216 212 reg = <0x54006900 0x40>; 217 - interrupts = <0 35 4>; 213 + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 218 214 pinctrl-names = "default"; 219 215 pinctrl-0 = <&pinctrl_uart1>; 220 216 clocks = <&peri_clk 1>; ··· 225 221 compatible = "socionext,uniphier-uart"; 226 222 status = "disabled"; 227 223 reg = <0x54006a00 0x40>; 228 - interrupts = <0 37 4>; 224 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 229 225 pinctrl-names = "default"; 230 226 pinctrl-0 = <&pinctrl_uart2>; 231 227 clocks = <&peri_clk 2>; ··· 236 232 compatible = "socionext,uniphier-uart"; 237 233 status = "disabled"; 238 234 reg = <0x54006b00 0x40>; 239 - interrupts = <0 177 4>; 235 + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 240 236 pinctrl-names = "default"; 241 237 pinctrl-0 = <&pinctrl_uart3>; 242 238 clocks = <&peri_clk 3>; ··· 263 259 audio@56000000 { 264 260 compatible = "socionext,uniphier-pxs2-aio"; 265 261 reg = <0x56000000 0x80000>; 266 - interrupts = <0 144 4>; 262 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 267 263 pinctrl-names = "default"; 268 264 pinctrl-0 = <&pinctrl_ain1>, 269 265 <&pinctrl_ain2>, ··· 321 317 reg = <0x58780000 0x80>; 322 318 #address-cells = <1>; 323 319 #size-cells = <0>; 324 - interrupts = <0 41 4>; 320 + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 325 321 pinctrl-names = "default"; 326 322 pinctrl-0 = <&pinctrl_i2c0>; 327 323 clocks = <&peri_clk 4>; ··· 335 331 reg = <0x58781000 0x80>; 336 332 #address-cells = <1>; 337 333 #size-cells = <0>; 338 - interrupts = <0 42 4>; 334 + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 339 335 pinctrl-names = "default"; 340 336 pinctrl-0 = <&pinctrl_i2c1>; 341 337 clocks = <&peri_clk 5>; ··· 349 345 reg = <0x58782000 0x80>; 350 346 #address-cells = <1>; 351 347 #size-cells = <0>; 352 - interrupts = <0 43 4>; 348 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 353 349 pinctrl-names = "default"; 354 350 pinctrl-0 = <&pinctrl_i2c2>; 355 351 clocks = <&peri_clk 6>; ··· 363 359 reg = <0x58783000 0x80>; 364 360 #address-cells = <1>; 365 361 #size-cells = <0>; 366 - interrupts = <0 44 4>; 362 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 367 363 pinctrl-names = "default"; 368 364 pinctrl-0 = <&pinctrl_i2c3>; 369 365 clocks = <&peri_clk 7>; ··· 377 373 reg = <0x58784000 0x80>; 378 374 #address-cells = <1>; 379 375 #size-cells = <0>; 380 - interrupts = <0 45 4>; 376 + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 381 377 clocks = <&peri_clk 8>; 382 378 resets = <&peri_rst 8>; 383 379 clock-frequency = <400000>; ··· 389 385 reg = <0x58785000 0x80>; 390 386 #address-cells = <1>; 391 387 #size-cells = <0>; 392 - interrupts = <0 25 4>; 388 + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 393 389 clocks = <&peri_clk 9>; 394 390 resets = <&peri_rst 9>; 395 391 clock-frequency = <400000>; ··· 401 397 reg = <0x58786000 0x80>; 402 398 #address-cells = <1>; 403 399 #size-cells = <0>; 404 - interrupts = <0 26 4>; 400 + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 405 401 clocks = <&peri_clk 10>; 406 402 resets = <&peri_rst 10>; 407 403 clock-frequency = <400000>; ··· 458 454 compatible = "socionext,uniphier-sd-v3.1.1"; 459 455 status = "disabled"; 460 456 reg = <0x5a000000 0x800>; 461 - interrupts = <0 78 4>; 457 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 462 458 pinctrl-names = "default"; 463 459 pinctrl-0 = <&pinctrl_emmc>; 464 460 clocks = <&sd_clk 1>; ··· 474 470 compatible = "socionext,uniphier-sd-v3.1.1"; 475 471 status = "disabled"; 476 472 reg = <0x5a400000 0x800>; 477 - interrupts = <0 76 4>; 473 + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 478 474 pinctrl-names = "default", "uhs"; 479 475 pinctrl-0 = <&pinctrl_sd>; 480 476 pinctrl-1 = <&pinctrl_sd_uhs>; ··· 519 515 xdmac: dma-controller@5fc10000 { 520 516 compatible = "socionext,uniphier-xdmac"; 521 517 reg = <0x5fc10000 0x5300>; 522 - interrupts = <0 188 4>; 518 + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 523 519 dma-channels = <16>; 524 520 #dma-cells = <2>; 525 521 }; ··· 534 530 timer@60000200 { 535 531 compatible = "arm,cortex-a9-global-timer"; 536 532 reg = <0x60000200 0x20>; 537 - interrupts = <1 11 0xf04>; 533 + interrupts = <GIC_PPI 11 534 + (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>; 538 535 clocks = <&arm_timer_clk>; 539 536 }; 540 537 541 538 timer@60000600 { 542 539 compatible = "arm,cortex-a9-twd-timer"; 543 540 reg = <0x60000600 0x20>; 544 - interrupts = <1 13 0xf04>; 541 + interrupts = <GIC_PPI 13 542 + (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>; 545 543 clocks = <&arm_timer_clk>; 546 544 }; 547 545 ··· 572 566 573 567 pvtctl: thermal-sensor { 574 568 compatible = "socionext,uniphier-pxs2-thermal"; 575 - interrupts = <0 3 4>; 569 + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 576 570 #thermal-sensor-cells = <0>; 577 571 socionext,tmod-calibration = <0x0f86 0x6844>; 578 572 }; ··· 582 576 compatible = "socionext,uniphier-pxs2-ave4"; 583 577 status = "disabled"; 584 578 reg = <0x65000000 0x8500>; 585 - interrupts = <0 66 4>; 579 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 586 580 pinctrl-names = "default"; 587 581 pinctrl-0 = <&pinctrl_ether_rgmii>; 588 582 clock-names = "ether"; ··· 604 598 status = "disabled"; 605 599 reg = <0x65a00000 0xcd00>; 606 600 interrupt-names = "dwc_usb3"; 607 - interrupts = <0 134 4>; 601 + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 608 602 pinctrl-names = "default"; 609 603 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 610 604 clock-names = "ref", "bus_early", "suspend"; ··· 700 694 status = "disabled"; 701 695 reg = <0x65c00000 0xcd00>; 702 696 interrupt-names = "dwc_usb3"; 703 - interrupts = <0 137 4>; 697 + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 704 698 pinctrl-names = "default"; 705 699 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 706 700 clock-names = "ref", "bus_early", "suspend"; ··· 786 780 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 787 781 #address-cells = <1>; 788 782 #size-cells = <0>; 789 - interrupts = <0 65 4>; 783 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 790 784 pinctrl-names = "default"; 791 785 pinctrl-0 = <&pinctrl_nand>; 792 786 clock-names = "nand", "nand_x", "ecc";
+2 -2
arch/arm/boot/dts/uniphier-sld8-ref.dts
··· 36 36 }; 37 37 38 38 &ethsc { 39 - interrupts = <0 8>; 39 + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 40 40 }; 41 41 42 42 &serialsc { 43 - interrupts = <0 8>; 43 + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 44 44 }; 45 45 46 46 &serial0 {
+29 -20
arch/arm/boot/dts/uniphier-sld8.dtsi
··· 6 6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 7 8 8 #include <dt-bindings/gpio/uniphier-gpio.h> 9 + #include <dt-bindings/interrupt-controller/arm-gic.h> 9 10 10 11 / { 11 12 compatible = "socionext,uniphier-sld8"; ··· 56 55 compatible = "socionext,uniphier-system-cache"; 57 56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 58 57 <0x506c0000 0x400>; 59 - interrupts = <0 174 4>, <0 175 4>; 58 + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 59 + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 60 60 cache-unified; 61 61 cache-size = <(256 * 1024)>; 62 62 cache-sets = <256>; ··· 71 69 reg = <0x54006000 0x100>; 72 70 #address-cells = <1>; 73 71 #size-cells = <0>; 74 - interrupts = <0 39 4>; 72 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 75 73 pinctrl-names = "default"; 76 74 pinctrl-0 = <&pinctrl_spi0>; 77 75 clocks = <&peri_clk 11>; ··· 82 80 compatible = "socionext,uniphier-uart"; 83 81 status = "disabled"; 84 82 reg = <0x54006800 0x40>; 85 - interrupts = <0 33 4>; 83 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 86 84 pinctrl-names = "default"; 87 85 pinctrl-0 = <&pinctrl_uart0>; 88 86 clocks = <&peri_clk 0>; ··· 93 91 compatible = "socionext,uniphier-uart"; 94 92 status = "disabled"; 95 93 reg = <0x54006900 0x40>; 96 - interrupts = <0 35 4>; 94 + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 97 95 pinctrl-names = "default"; 98 96 pinctrl-0 = <&pinctrl_uart1>; 99 97 clocks = <&peri_clk 1>; ··· 104 102 compatible = "socionext,uniphier-uart"; 105 103 status = "disabled"; 106 104 reg = <0x54006a00 0x40>; 107 - interrupts = <0 37 4>; 105 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 108 106 pinctrl-names = "default"; 109 107 pinctrl-0 = <&pinctrl_uart2>; 110 108 clocks = <&peri_clk 2>; ··· 115 113 compatible = "socionext,uniphier-uart"; 116 114 status = "disabled"; 117 115 reg = <0x54006b00 0x40>; 118 - interrupts = <0 29 4>; 116 + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 119 117 pinctrl-names = "default"; 120 118 pinctrl-0 = <&pinctrl_uart3>; 121 119 clocks = <&peri_clk 3>; ··· 146 144 reg = <0x58400000 0x40>; 147 145 #address-cells = <1>; 148 146 #size-cells = <0>; 149 - interrupts = <0 41 1>; 147 + interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>; 150 148 pinctrl-names = "default"; 151 149 pinctrl-0 = <&pinctrl_i2c0>; 152 150 clocks = <&peri_clk 4>; ··· 160 158 reg = <0x58480000 0x40>; 161 159 #address-cells = <1>; 162 160 #size-cells = <0>; 163 - interrupts = <0 42 1>; 161 + interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>; 164 162 pinctrl-names = "default"; 165 163 pinctrl-0 = <&pinctrl_i2c1>; 166 164 clocks = <&peri_clk 5>; ··· 174 172 reg = <0x58500000 0x40>; 175 173 #address-cells = <1>; 176 174 #size-cells = <0>; 177 - interrupts = <0 43 1>; 175 + interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>; 178 176 pinctrl-names = "default"; 179 177 pinctrl-0 = <&pinctrl_i2c2>; 180 178 clocks = <&peri_clk 6>; ··· 188 186 reg = <0x58580000 0x40>; 189 187 #address-cells = <1>; 190 188 #size-cells = <0>; 191 - interrupts = <0 44 1>; 189 + interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>; 192 190 pinctrl-names = "default"; 193 191 pinctrl-0 = <&pinctrl_i2c3>; 194 192 clocks = <&peri_clk 7>; ··· 246 244 dmac: dma-controller@5a000000 { 247 245 compatible = "socionext,uniphier-mio-dmac"; 248 246 reg = <0x5a000000 0x1000>; 249 - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, 250 - <0 71 4>, <0 72 4>, <0 73 4>; 247 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 248 + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 249 + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 250 + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 251 + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 252 + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 253 + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 251 254 clocks = <&mio_clk 7>; 252 255 resets = <&mio_rst 7>; 253 256 #dma-cells = <1>; ··· 262 255 compatible = "socionext,uniphier-sd-v2.91"; 263 256 status = "disabled"; 264 257 reg = <0x5a400000 0x200>; 265 - interrupts = <0 76 4>; 258 + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 266 259 pinctrl-names = "default", "uhs"; 267 260 pinctrl-0 = <&pinctrl_sd>; 268 261 pinctrl-1 = <&pinctrl_sd_uhs>; ··· 282 275 compatible = "socionext,uniphier-sd-v2.91"; 283 276 status = "disabled"; 284 277 reg = <0x5a500000 0x200>; 285 - interrupts = <0 78 4>; 278 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 286 279 pinctrl-names = "default"; 287 280 pinctrl-0 = <&pinctrl_emmc>; 288 281 clocks = <&mio_clk 1>; ··· 300 293 compatible = "socionext,uniphier-ehci", "generic-ehci"; 301 294 status = "disabled"; 302 295 reg = <0x5a800100 0x100>; 303 - interrupts = <0 80 4>; 296 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 304 297 pinctrl-names = "default"; 305 298 pinctrl-0 = <&pinctrl_usb0>; 306 299 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, ··· 314 307 compatible = "socionext,uniphier-ehci", "generic-ehci"; 315 308 status = "disabled"; 316 309 reg = <0x5a810100 0x100>; 317 - interrupts = <0 81 4>; 310 + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 318 311 pinctrl-names = "default"; 319 312 pinctrl-0 = <&pinctrl_usb1>; 320 313 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, ··· 328 321 compatible = "socionext,uniphier-ehci", "generic-ehci"; 329 322 status = "disabled"; 330 323 reg = <0x5a820100 0x100>; 331 - interrupts = <0 82 4>; 324 + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 332 325 pinctrl-names = "default"; 333 326 pinctrl-0 = <&pinctrl_usb2>; 334 327 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, ··· 369 362 timer@60000200 { 370 363 compatible = "arm,cortex-a9-global-timer"; 371 364 reg = <0x60000200 0x20>; 372 - interrupts = <1 11 0x104>; 365 + interrupts = <GIC_PPI 11 366 + (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; 373 367 clocks = <&arm_timer_clk>; 374 368 }; 375 369 376 370 timer@60000600 { 377 371 compatible = "arm,cortex-a9-twd-timer"; 378 372 reg = <0x60000600 0x20>; 379 - interrupts = <1 13 0x104>; 373 + interrupts = <GIC_PPI 13 374 + (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; 380 375 clocks = <&arm_timer_clk>; 381 376 }; 382 377 ··· 420 411 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 421 412 #address-cells = <1>; 422 413 #size-cells = <0>; 423 - interrupts = <0 65 4>; 414 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 424 415 pinctrl-names = "default"; 425 416 pinctrl-0 = <&pinctrl_nand>; 426 417 clock-names = "nand", "nand_x", "ecc";