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linux
arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622
There are two independent PCIe controllers in MT2712 and MT7622
platform. Each of them should contain an independent MSI domain.
In old dts architecture, MSI domain will be inherited from the root
bridge, and all of the devices will share the same MSI domain.
Hence that, the PCIe devices will not work properly if the irq number
which required is more than 32.
Split the PCIe node for MT2712 and MT7622 platform to comply with
the hardware design and fix MSI issue.
Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
Link: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
authored by
Chuanjia Liu
and committed by
Matthias Brugger
c99c4733
d2bbd5d9
+118
-113
+50
-47
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+50
-47
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
···
915
915
};
916
916
};
917
917
918
-
pcie: pcie@11700000 {
918
+
pcie1: pcie@112ff000 {
919
919
compatible = "mediatek,mt2712-pcie";
920
920
device_type = "pci";
921
-
reg = <0 0x11700000 0 0x1000>,
922
-
<0 0x112ff000 0 0x1000>;
923
-
reg-names = "port0", "port1";
921
+
reg = <0 0x112ff000 0 0x1000>;
922
+
reg-names = "port1";
923
+
linux,pci-domain = <1>;
924
924
#address-cells = <3>;
925
925
#size-cells = <2>;
926
-
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
927
-
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
928
-
clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
929
-
<&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
930
-
<&pericfg CLK_PERI_PCIE0>,
926
+
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
927
+
interrupt-names = "pcie_irq";
928
+
clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
931
929
<&pericfg CLK_PERI_PCIE1>;
932
-
clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
933
-
phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
934
-
phy-names = "pcie-phy0", "pcie-phy1";
930
+
clock-names = "sys_ck1", "ahb_ck1";
931
+
phys = <&u3port1 PHY_TYPE_PCIE>;
932
+
phy-names = "pcie-phy1";
935
933
bus-range = <0x00 0xff>;
936
-
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
934
+
ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
935
+
status = "disabled";
937
936
938
-
pcie0: pcie@0,0 {
939
-
device_type = "pci";
940
-
status = "disabled";
941
-
reg = <0x0000 0 0 0 0>;
942
-
#address-cells = <3>;
943
-
#size-cells = <2>;
937
+
#interrupt-cells = <1>;
938
+
interrupt-map-mask = <0 0 0 7>;
939
+
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
940
+
<0 0 0 2 &pcie_intc1 1>,
941
+
<0 0 0 3 &pcie_intc1 2>,
942
+
<0 0 0 4 &pcie_intc1 3>;
943
+
pcie_intc1: interrupt-controller {
944
+
interrupt-controller;
945
+
#address-cells = <0>;
944
946
#interrupt-cells = <1>;
945
-
ranges;
946
-
interrupt-map-mask = <0 0 0 7>;
947
-
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
948
-
<0 0 0 2 &pcie_intc0 1>,
949
-
<0 0 0 3 &pcie_intc0 2>,
950
-
<0 0 0 4 &pcie_intc0 3>;
951
-
pcie_intc0: interrupt-controller {
952
-
interrupt-controller;
953
-
#address-cells = <0>;
954
-
#interrupt-cells = <1>;
955
-
};
956
947
};
948
+
};
957
949
958
-
pcie1: pcie@1,0 {
959
-
device_type = "pci";
960
-
status = "disabled";
961
-
reg = <0x0800 0 0 0 0>;
962
-
#address-cells = <3>;
963
-
#size-cells = <2>;
950
+
pcie0: pcie@11700000 {
951
+
compatible = "mediatek,mt2712-pcie";
952
+
device_type = "pci";
953
+
reg = <0 0x11700000 0 0x1000>;
954
+
reg-names = "port0";
955
+
linux,pci-domain = <0>;
956
+
#address-cells = <3>;
957
+
#size-cells = <2>;
958
+
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
959
+
interrupt-names = "pcie_irq";
960
+
clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
961
+
<&pericfg CLK_PERI_PCIE0>;
962
+
clock-names = "sys_ck0", "ahb_ck0";
963
+
phys = <&u3port0 PHY_TYPE_PCIE>;
964
+
phy-names = "pcie-phy0";
965
+
bus-range = <0x00 0xff>;
966
+
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
967
+
status = "disabled";
968
+
969
+
#interrupt-cells = <1>;
970
+
interrupt-map-mask = <0 0 0 7>;
971
+
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
972
+
<0 0 0 2 &pcie_intc0 1>,
973
+
<0 0 0 3 &pcie_intc0 2>,
974
+
<0 0 0 4 &pcie_intc0 3>;
975
+
pcie_intc0: interrupt-controller {
976
+
interrupt-controller;
977
+
#address-cells = <0>;
964
978
#interrupt-cells = <1>;
965
-
ranges;
966
-
interrupt-map-mask = <0 0 0 7>;
967
-
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
968
-
<0 0 0 2 &pcie_intc1 1>,
969
-
<0 0 0 3 &pcie_intc1 2>,
970
-
<0 0 0 4 &pcie_intc1 3>;
971
-
pcie_intc1: interrupt-controller {
972
-
interrupt-controller;
973
-
#address-cells = <0>;
974
-
#interrupt-cells = <1>;
975
-
};
976
979
};
977
980
};
978
981
+7
-9
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+7
-9
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
···
257
257
};
258
258
};
259
259
260
-
&pcie {
260
+
&pcie0 {
261
261
pinctrl-names = "default";
262
-
pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
262
+
pinctrl-0 = <&pcie0_pins>;
263
263
status = "okay";
264
+
};
264
265
265
-
pcie@0,0 {
266
-
status = "okay";
267
-
};
268
-
269
-
pcie@1,0 {
270
-
status = "okay";
271
-
};
266
+
&pcie1 {
267
+
pinctrl-names = "default";
268
+
pinctrl-0 = <&pcie1_pins>;
269
+
status = "okay";
272
270
};
273
271
274
272
&pio {
+1
-5
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+1
-5
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+60
-52
arch/arm64/boot/dts/mediatek/mt7622.dtsi
+60
-52
arch/arm64/boot/dts/mediatek/mt7622.dtsi
···
781
781
#reset-cells = <1>;
782
782
};
783
783
784
-
pcie: pcie@1a140000 {
784
+
pciecfg: pciecfg@1a140000 {
785
+
compatible = "mediatek,generic-pciecfg", "syscon";
786
+
reg = <0 0x1a140000 0 0x1000>;
787
+
};
788
+
789
+
pcie0: pcie@1a143000 {
785
790
compatible = "mediatek,mt7622-pcie";
786
791
device_type = "pci";
787
-
reg = <0 0x1a140000 0 0x1000>,
788
-
<0 0x1a143000 0 0x1000>,
789
-
<0 0x1a145000 0 0x1000>;
790
-
reg-names = "subsys", "port0", "port1";
792
+
reg = <0 0x1a143000 0 0x1000>;
793
+
reg-names = "port0";
794
+
linux,pci-domain = <0>;
791
795
#address-cells = <3>;
792
796
#size-cells = <2>;
793
-
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
794
-
<GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
797
+
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
798
+
interrupt-names = "pcie_irq";
795
799
clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
796
-
<&pciesys CLK_PCIE_P1_MAC_EN>,
797
-
<&pciesys CLK_PCIE_P0_AHB_EN>,
798
800
<&pciesys CLK_PCIE_P0_AHB_EN>,
799
801
<&pciesys CLK_PCIE_P0_AUX_EN>,
800
-
<&pciesys CLK_PCIE_P1_AUX_EN>,
801
802
<&pciesys CLK_PCIE_P0_AXI_EN>,
802
-
<&pciesys CLK_PCIE_P1_AXI_EN>,
803
803
<&pciesys CLK_PCIE_P0_OBFF_EN>,
804
-
<&pciesys CLK_PCIE_P1_OBFF_EN>,
805
-
<&pciesys CLK_PCIE_P0_PIPE_EN>,
806
-
<&pciesys CLK_PCIE_P1_PIPE_EN>;
807
-
clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
808
-
"aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
809
-
"obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
804
+
<&pciesys CLK_PCIE_P0_PIPE_EN>;
805
+
clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
806
+
"axi_ck0", "obff_ck0", "pipe_ck0";
807
+
810
808
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
811
809
bus-range = <0x00 0xff>;
812
-
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
810
+
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
813
811
status = "disabled";
814
812
815
-
pcie0: pcie@0,0 {
816
-
reg = <0x0000 0 0 0 0>;
817
-
#address-cells = <3>;
818
-
#size-cells = <2>;
813
+
#interrupt-cells = <1>;
814
+
interrupt-map-mask = <0 0 0 7>;
815
+
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
816
+
<0 0 0 2 &pcie_intc0 1>,
817
+
<0 0 0 3 &pcie_intc0 2>,
818
+
<0 0 0 4 &pcie_intc0 3>;
819
+
pcie_intc0: interrupt-controller {
820
+
interrupt-controller;
821
+
#address-cells = <0>;
819
822
#interrupt-cells = <1>;
820
-
ranges;
821
-
status = "disabled";
822
-
823
-
interrupt-map-mask = <0 0 0 7>;
824
-
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
825
-
<0 0 0 2 &pcie_intc0 1>,
826
-
<0 0 0 3 &pcie_intc0 2>,
827
-
<0 0 0 4 &pcie_intc0 3>;
828
-
pcie_intc0: interrupt-controller {
829
-
interrupt-controller;
830
-
#address-cells = <0>;
831
-
#interrupt-cells = <1>;
832
-
};
833
823
};
824
+
};
834
825
835
-
pcie1: pcie@1,0 {
836
-
reg = <0x0800 0 0 0 0>;
837
-
#address-cells = <3>;
838
-
#size-cells = <2>;
826
+
pcie1: pcie@1a145000 {
827
+
compatible = "mediatek,mt7622-pcie";
828
+
device_type = "pci";
829
+
reg = <0 0x1a145000 0 0x1000>;
830
+
reg-names = "port1";
831
+
linux,pci-domain = <1>;
832
+
#address-cells = <3>;
833
+
#size-cells = <2>;
834
+
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
835
+
interrupt-names = "pcie_irq";
836
+
clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
837
+
/* designer has connect RC1 with p0_ahb clock */
838
+
<&pciesys CLK_PCIE_P0_AHB_EN>,
839
+
<&pciesys CLK_PCIE_P1_AUX_EN>,
840
+
<&pciesys CLK_PCIE_P1_AXI_EN>,
841
+
<&pciesys CLK_PCIE_P1_OBFF_EN>,
842
+
<&pciesys CLK_PCIE_P1_PIPE_EN>;
843
+
clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
844
+
"axi_ck1", "obff_ck1", "pipe_ck1";
845
+
846
+
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
847
+
bus-range = <0x00 0xff>;
848
+
ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
849
+
status = "disabled";
850
+
851
+
#interrupt-cells = <1>;
852
+
interrupt-map-mask = <0 0 0 7>;
853
+
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
854
+
<0 0 0 2 &pcie_intc1 1>,
855
+
<0 0 0 3 &pcie_intc1 2>,
856
+
<0 0 0 4 &pcie_intc1 3>;
857
+
pcie_intc1: interrupt-controller {
858
+
interrupt-controller;
859
+
#address-cells = <0>;
839
860
#interrupt-cells = <1>;
840
-
ranges;
841
-
status = "disabled";
842
-
843
-
interrupt-map-mask = <0 0 0 7>;
844
-
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
845
-
<0 0 0 2 &pcie_intc1 1>,
846
-
<0 0 0 3 &pcie_intc1 2>,
847
-
<0 0 0 4 &pcie_intc1 3>;
848
-
pcie_intc1: interrupt-controller {
849
-
interrupt-controller;
850
-
#address-cells = <0>;
851
-
#interrupt-cells = <1>;
852
-
};
853
861
};
854
862
};
855
863