tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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dt-bindings: clk: Add compatibles for D1 CCUs

The D1 has a CCU and a R_CCU (PRCM CCU) like most other sunxi SoCs, with
3 and 4 clock inputs, respectively. Add the compatibles and bindings.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211119043545.4010-2-samuel@sholland.org

authored by

Samuel Holland and committed by
Maxime Ripard c962f10f 91389c39

+272
+4
Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
··· 34 34 - allwinner,sun8i-v3-ccu 35 35 - allwinner,sun8i-v3s-ccu 36 36 - allwinner,sun9i-a80-ccu 37 + - allwinner,sun20i-d1-ccu 38 + - allwinner,sun20i-d1-r-ccu 37 39 - allwinner,sun50i-a64-ccu 38 40 - allwinner,sun50i-a64-r-ccu 39 41 - allwinner,sun50i-a100-ccu ··· 81 79 enum: 82 80 - allwinner,sun8i-a83t-r-ccu 83 81 - allwinner,sun8i-h3-r-ccu 82 + - allwinner,sun20i-d1-r-ccu 84 83 - allwinner,sun50i-a64-r-ccu 85 84 - allwinner,sun50i-a100-r-ccu 86 85 - allwinner,sun50i-h6-r-ccu ··· 102 99 properties: 103 100 compatible: 104 101 enum: 102 + - allwinner,sun20i-d1-ccu 105 103 - allwinner,sun50i-a100-ccu 106 104 - allwinner,sun50i-h6-ccu 107 105 - allwinner,sun50i-h616-ccu
+156
include/dt-bindings/clock/sun20i-d1-ccu.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 2 + /* 3 + * Copyright (C) 2020 huangzhenwei@allwinnertech.com 4 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ 8 + #define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ 9 + 10 + #define CLK_PLL_CPUX 0 11 + #define CLK_PLL_DDR0 1 12 + #define CLK_PLL_PERIPH0_4X 2 13 + #define CLK_PLL_PERIPH0_2X 3 14 + #define CLK_PLL_PERIPH0_800M 4 15 + #define CLK_PLL_PERIPH0 5 16 + #define CLK_PLL_PERIPH0_DIV3 6 17 + #define CLK_PLL_VIDEO0_4X 7 18 + #define CLK_PLL_VIDEO0_2X 8 19 + #define CLK_PLL_VIDEO0 9 20 + #define CLK_PLL_VIDEO1_4X 10 21 + #define CLK_PLL_VIDEO1_2X 11 22 + #define CLK_PLL_VIDEO1 12 23 + #define CLK_PLL_VE 13 24 + #define CLK_PLL_AUDIO0_4X 14 25 + #define CLK_PLL_AUDIO0_2X 15 26 + #define CLK_PLL_AUDIO0 16 27 + #define CLK_PLL_AUDIO1 17 28 + #define CLK_PLL_AUDIO1_DIV2 18 29 + #define CLK_PLL_AUDIO1_DIV5 19 30 + #define CLK_CPUX 20 31 + #define CLK_CPUX_AXI 21 32 + #define CLK_CPUX_APB 22 33 + #define CLK_PSI_AHB 23 34 + #define CLK_APB0 24 35 + #define CLK_APB1 25 36 + #define CLK_MBUS 26 37 + #define CLK_DE 27 38 + #define CLK_BUS_DE 28 39 + #define CLK_DI 29 40 + #define CLK_BUS_DI 30 41 + #define CLK_G2D 31 42 + #define CLK_BUS_G2D 32 43 + #define CLK_CE 33 44 + #define CLK_BUS_CE 34 45 + #define CLK_VE 35 46 + #define CLK_BUS_VE 36 47 + #define CLK_BUS_DMA 37 48 + #define CLK_BUS_MSGBOX0 38 49 + #define CLK_BUS_MSGBOX1 39 50 + #define CLK_BUS_MSGBOX2 40 51 + #define CLK_BUS_SPINLOCK 41 52 + #define CLK_BUS_HSTIMER 42 53 + #define CLK_AVS 43 54 + #define CLK_BUS_DBG 44 55 + #define CLK_BUS_PWM 45 56 + #define CLK_BUS_IOMMU 46 57 + #define CLK_DRAM 47 58 + #define CLK_MBUS_DMA 48 59 + #define CLK_MBUS_VE 49 60 + #define CLK_MBUS_CE 50 61 + #define CLK_MBUS_TVIN 51 62 + #define CLK_MBUS_CSI 52 63 + #define CLK_MBUS_G2D 53 64 + #define CLK_MBUS_RISCV 54 65 + #define CLK_BUS_DRAM 55 66 + #define CLK_MMC0 56 67 + #define CLK_MMC1 57 68 + #define CLK_MMC2 58 69 + #define CLK_BUS_MMC0 59 70 + #define CLK_BUS_MMC1 60 71 + #define CLK_BUS_MMC2 61 72 + #define CLK_BUS_UART0 62 73 + #define CLK_BUS_UART1 63 74 + #define CLK_BUS_UART2 64 75 + #define CLK_BUS_UART3 65 76 + #define CLK_BUS_UART4 66 77 + #define CLK_BUS_UART5 67 78 + #define CLK_BUS_I2C0 68 79 + #define CLK_BUS_I2C1 69 80 + #define CLK_BUS_I2C2 70 81 + #define CLK_BUS_I2C3 71 82 + #define CLK_SPI0 72 83 + #define CLK_SPI1 73 84 + #define CLK_BUS_SPI0 74 85 + #define CLK_BUS_SPI1 75 86 + #define CLK_EMAC_25M 76 87 + #define CLK_BUS_EMAC 77 88 + #define CLK_IR_TX 78 89 + #define CLK_BUS_IR_TX 79 90 + #define CLK_BUS_GPADC 80 91 + #define CLK_BUS_THS 81 92 + #define CLK_I2S0 82 93 + #define CLK_I2S1 83 94 + #define CLK_I2S2 84 95 + #define CLK_I2S2_ASRC 85 96 + #define CLK_BUS_I2S0 86 97 + #define CLK_BUS_I2S1 87 98 + #define CLK_BUS_I2S2 88 99 + #define CLK_SPDIF_TX 89 100 + #define CLK_SPDIF_RX 90 101 + #define CLK_BUS_SPDIF 91 102 + #define CLK_DMIC 92 103 + #define CLK_BUS_DMIC 93 104 + #define CLK_AUDIO_DAC 94 105 + #define CLK_AUDIO_ADC 95 106 + #define CLK_BUS_AUDIO 96 107 + #define CLK_USB_OHCI0 97 108 + #define CLK_USB_OHCI1 98 109 + #define CLK_BUS_OHCI0 99 110 + #define CLK_BUS_OHCI1 100 111 + #define CLK_BUS_EHCI0 101 112 + #define CLK_BUS_EHCI1 102 113 + #define CLK_BUS_OTG 103 114 + #define CLK_BUS_LRADC 104 115 + #define CLK_BUS_DPSS_TOP 105 116 + #define CLK_HDMI_24M 106 117 + #define CLK_HDMI_CEC_32K 107 118 + #define CLK_HDMI_CEC 108 119 + #define CLK_BUS_HDMI 109 120 + #define CLK_MIPI_DSI 110 121 + #define CLK_BUS_MIPI_DSI 111 122 + #define CLK_TCON_LCD0 112 123 + #define CLK_BUS_TCON_LCD0 113 124 + #define CLK_TCON_TV 114 125 + #define CLK_BUS_TCON_TV 115 126 + #define CLK_TVE 116 127 + #define CLK_BUS_TVE_TOP 117 128 + #define CLK_BUS_TVE 118 129 + #define CLK_TVD 119 130 + #define CLK_BUS_TVD_TOP 120 131 + #define CLK_BUS_TVD 121 132 + #define CLK_LEDC 122 133 + #define CLK_BUS_LEDC 123 134 + #define CLK_CSI_TOP 124 135 + #define CLK_CSI_MCLK 125 136 + #define CLK_BUS_CSI 126 137 + #define CLK_TPADC 127 138 + #define CLK_BUS_TPADC 128 139 + #define CLK_BUS_TZMA 129 140 + #define CLK_DSP 130 141 + #define CLK_BUS_DSP_CFG 131 142 + #define CLK_RISCV 132 143 + #define CLK_RISCV_AXI 133 144 + #define CLK_BUS_RISCV_CFG 134 145 + #define CLK_FANOUT_24M 135 146 + #define CLK_FANOUT_12M 136 147 + #define CLK_FANOUT_16M 137 148 + #define CLK_FANOUT_25M 138 149 + #define CLK_FANOUT_32K 139 150 + #define CLK_FANOUT_27M 140 151 + #define CLK_FANOUT_PCLK 141 152 + #define CLK_FANOUT0 142 153 + #define CLK_FANOUT1 143 154 + #define CLK_FANOUT2 144 155 + 156 + #endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
+19
include/dt-bindings/clock/sun20i-d1-r-ccu.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 2 + /* 3 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ 7 + #define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ 8 + 9 + #define CLK_R_AHB 0 10 + 11 + #define CLK_BUS_R_TIMER 2 12 + #define CLK_BUS_R_TWD 3 13 + #define CLK_BUS_R_PPU 4 14 + #define CLK_R_IR_RX 5 15 + #define CLK_BUS_R_IR_RX 6 16 + #define CLK_BUS_R_RTC 7 17 + #define CLK_BUS_R_CPUCFG 8 18 + 19 + #endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */
+77
include/dt-bindings/reset/sun20i-d1-ccu.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 2 + /* 3 + * Copyright (c) 2020 huangzhenwei@allwinnertech.com 4 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ 8 + #define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ 9 + 10 + #define RST_MBUS 0 11 + #define RST_BUS_DE 1 12 + #define RST_BUS_DI 2 13 + #define RST_BUS_G2D 3 14 + #define RST_BUS_CE 4 15 + #define RST_BUS_VE 5 16 + #define RST_BUS_DMA 6 17 + #define RST_BUS_MSGBOX0 7 18 + #define RST_BUS_MSGBOX1 8 19 + #define RST_BUS_MSGBOX2 9 20 + #define RST_BUS_SPINLOCK 10 21 + #define RST_BUS_HSTIMER 11 22 + #define RST_BUS_DBG 12 23 + #define RST_BUS_PWM 13 24 + #define RST_BUS_DRAM 14 25 + #define RST_BUS_MMC0 15 26 + #define RST_BUS_MMC1 16 27 + #define RST_BUS_MMC2 17 28 + #define RST_BUS_UART0 18 29 + #define RST_BUS_UART1 19 30 + #define RST_BUS_UART2 20 31 + #define RST_BUS_UART3 21 32 + #define RST_BUS_UART4 22 33 + #define RST_BUS_UART5 23 34 + #define RST_BUS_I2C0 24 35 + #define RST_BUS_I2C1 25 36 + #define RST_BUS_I2C2 26 37 + #define RST_BUS_I2C3 27 38 + #define RST_BUS_SPI0 28 39 + #define RST_BUS_SPI1 29 40 + #define RST_BUS_EMAC 30 41 + #define RST_BUS_IR_TX 31 42 + #define RST_BUS_GPADC 32 43 + #define RST_BUS_THS 33 44 + #define RST_BUS_I2S0 34 45 + #define RST_BUS_I2S1 35 46 + #define RST_BUS_I2S2 36 47 + #define RST_BUS_SPDIF 37 48 + #define RST_BUS_DMIC 38 49 + #define RST_BUS_AUDIO 39 50 + #define RST_USB_PHY0 40 51 + #define RST_USB_PHY1 41 52 + #define RST_BUS_OHCI0 42 53 + #define RST_BUS_OHCI1 43 54 + #define RST_BUS_EHCI0 44 55 + #define RST_BUS_EHCI1 45 56 + #define RST_BUS_OTG 46 57 + #define RST_BUS_LRADC 47 58 + #define RST_BUS_DPSS_TOP 48 59 + #define RST_BUS_HDMI_SUB 49 60 + #define RST_BUS_HDMI_MAIN 50 61 + #define RST_BUS_MIPI_DSI 51 62 + #define RST_BUS_TCON_LCD0 52 63 + #define RST_BUS_TCON_TV 53 64 + #define RST_BUS_LVDS0 54 65 + #define RST_BUS_TVE 55 66 + #define RST_BUS_TVE_TOP 56 67 + #define RST_BUS_TVD 57 68 + #define RST_BUS_TVD_TOP 58 69 + #define RST_BUS_LEDC 59 70 + #define RST_BUS_CSI 60 71 + #define RST_BUS_TPADC 61 72 + #define RST_DSP 62 73 + #define RST_BUS_DSP_CFG 63 74 + #define RST_BUS_DSP_DBG 64 75 + #define RST_BUS_RISCV_CFG 65 76 + 77 + #endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */
+16
include/dt-bindings/reset/sun20i-d1-r-ccu.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 2 + /* 3 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ 7 + #define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ 8 + 9 + #define RST_BUS_R_TIMER 0 10 + #define RST_BUS_R_TWD 1 11 + #define RST_BUS_R_PPU 2 12 + #define RST_BUS_R_IR_RX 3 13 + #define RST_BUS_R_RTC 4 14 + #define RST_BUS_R_CPUCFG 5 15 + 16 + #endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */