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dt-bindings: soc: intel: lgm-syscon: Move to dedicated schema

intel,lgm-syscon is not a simple syscon device - it has children - thus
it should be fully documented in its own binding.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240626-dt-bindings-mfd-syscon-split-v3-3-3409903bb99b@linaro.org
Signed-off-by: Lee Jones <lee@kernel.org>

authored by

Krzysztof Kozlowski and committed by
Lee Jones
c94ee67a cf87496b

+57 -1
-1
Documentation/devicetree/bindings/mfd/syscon.yaml
··· 57 57 - hisilicon,pcie-sas-subctrl 58 58 - hisilicon,peri-subctrl 59 59 - hpe,gxp-sysreg 60 - - intel,lgm-syscon 61 60 - loongson,ls1b-syscon 62 61 - loongson,ls1c-syscon 63 62 - marvell,armada-3700-cpu-misc
+57
Documentation/devicetree/bindings/soc/intel/intel,lgm-syscon.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/soc/intel/intel,lgm-syscon.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Intel Lightning Mountain(LGM) Syscon 8 + 9 + maintainers: 10 + - Chuanhua Lei <lchuanhua@maxlinear.com> 11 + - Rahul Tanwar <rtanwar@maxlinear.com> 12 + 13 + properties: 14 + compatible: 15 + items: 16 + - const: intel,lgm-syscon 17 + - const: syscon 18 + 19 + reg: 20 + maxItems: 1 21 + 22 + ranges: true 23 + 24 + "#address-cells": 25 + const: 1 26 + 27 + "#size-cells": 28 + const: 1 29 + 30 + patternProperties: 31 + "^emmc-phy@[0-9a-f]+$": 32 + $ref: /schemas/phy/intel,lgm-emmc-phy.yaml# 33 + 34 + required: 35 + - compatible 36 + - reg 37 + - "#address-cells" 38 + - "#size-cells" 39 + 40 + additionalProperties: false 41 + 42 + examples: 43 + - | 44 + chiptop@e0200000 { 45 + compatible = "intel,lgm-syscon", "syscon"; 46 + reg = <0xe0200000 0x100>; 47 + ranges = <0x0 0xe0200000 0x100>; 48 + #address-cells = <1>; 49 + #size-cells = <1>; 50 + 51 + emmc-phy@a8 { 52 + compatible = "intel,lgm-emmc-phy"; 53 + reg = <0x00a8 0x10>; 54 + clocks = <&emmc>; 55 + #phy-cells = <0>; 56 + }; 57 + };