tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'dmaengine-5.8-rc1' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine updates from Vinod Koul:
"A fairly small dmaengine update which includes mostly driver updates
(dmatest, dw-edma, ioat, mmp-tdma and k3-udma) along with Renesas
binding update to json-schema"
* tag 'dmaengine-5.8-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (39 commits)
dmaengine: imx-sdma: initialize all script addresses
dmaengine: ti: k3-udma: Use proper return code in alloc_chan_resources
dmaengine: ti: k3-udma: Remove udma_chan.in_ring_cnt
dmaengine: ti: k3-udma: Add missing dma_sync call for rx flush descriptor
dmaengine: at_xdmac: Replace zero-length array with flexible-array
dmaengine: at_hdmac: Replace zero-length array with flexible-array
dmaengine: qcom: bam_dma: Replace zero-length array with flexible-array
dmaengine: ti: k3-udma: Use PTR_ERR_OR_ZERO() to simplify code
dmaengine: moxart-dma: Drop pointless static qualifier in moxart_probe()
dmaengine: sf-pdma: Simplify the error handling path in 'sf_pdma_probe()'
dmaengine: qcom_hidma: use true,false for bool variable
dmaengine: dw-edma: support local dma device transfer semantics
dmaengine: Fix doc strings to satisfy validation script
dmaengine: Include dmaengine.h into dmaengine.c
dmaengine: dmatest: Describe members of struct dmatest_info
dmaengine: dmatest: Describe members of struct dmatest_params
dmaengine: dmatest: Allow negative timeout value to specify infinite wait
Revert "dmaengine: dmatest: timeout value of -1 should specify infinite wait"
dmaengine: stm32-dma: direct mode support through device tree
dt-bindings: dma: add direct mode support through device tree in stm32-dma
...
+537
-358
+6
Documentation/ABI/stable/sysfs-driver-dma-idxd
+6
Documentation/ABI/stable/sysfs-driver-dma-idxd
-117
Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
-117
Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
···
1
-
* Renesas R-Car (RZ/G) DMA Controller Device Tree bindings
2
-
3
-
Renesas R-Car (Gen 2/3) and RZ/G SoCs have multiple multi-channel DMA
4
-
controller instances named DMAC capable of serving multiple clients. Channels
5
-
can be dedicated to specific clients or shared between a large number of
6
-
clients.
7
-
8
-
Each DMA client is connected to one dedicated port of the DMAC, identified by
9
-
an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
10
-
256 clients in total. When the number of hardware channels is lower than the
11
-
number of clients to be served, channels must be shared between multiple DMA
12
-
clients. The association of DMA clients to DMAC channels is fully dynamic and
13
-
not described in these device tree bindings.
14
-
15
-
Required Properties:
16
-
17
-
- compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
18
-
Examples with soctypes are:
19
-
- "renesas,dmac-r8a7743" (RZ/G1M)
20
-
- "renesas,dmac-r8a7744" (RZ/G1N)
21
-
- "renesas,dmac-r8a7745" (RZ/G1E)
22
-
- "renesas,dmac-r8a77470" (RZ/G1C)
23
-
- "renesas,dmac-r8a774a1" (RZ/G2M)
24
-
- "renesas,dmac-r8a774b1" (RZ/G2N)
25
-
- "renesas,dmac-r8a774c0" (RZ/G2E)
26
-
- "renesas,dmac-r8a7790" (R-Car H2)
27
-
- "renesas,dmac-r8a7791" (R-Car M2-W)
28
-
- "renesas,dmac-r8a7792" (R-Car V2H)
29
-
- "renesas,dmac-r8a7793" (R-Car M2-N)
30
-
- "renesas,dmac-r8a7794" (R-Car E2)
31
-
- "renesas,dmac-r8a7795" (R-Car H3)
32
-
- "renesas,dmac-r8a7796" (R-Car M3-W)
33
-
- "renesas,dmac-r8a77961" (R-Car M3-W+)
34
-
- "renesas,dmac-r8a77965" (R-Car M3-N)
35
-
- "renesas,dmac-r8a77970" (R-Car V3M)
36
-
- "renesas,dmac-r8a77980" (R-Car V3H)
37
-
- "renesas,dmac-r8a77990" (R-Car E3)
38
-
- "renesas,dmac-r8a77995" (R-Car D3)
39
-
40
-
- reg: base address and length of the registers block for the DMAC
41
-
42
-
- interrupts: interrupt specifiers for the DMAC, one for each entry in
43
-
interrupt-names.
44
-
- interrupt-names: one entry for the error interrupt, named "error", plus one
45
-
entry per channel, named "ch%u", where %u is the channel number ranging from
46
-
zero to the number of channels minus one.
47
-
48
-
- clock-names: "fck" for the functional clock
49
-
- clocks: a list of phandle + clock-specifier pairs, one for each entry
50
-
in clock-names.
51
-
- clock-names: must contain "fck" for the functional clock.
52
-
53
-
- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
54
-
connected to the DMA client
55
-
- dma-channels: number of DMA channels
56
-
57
-
Example: R8A7790 (R-Car H2) SYS-DMACs
58
-
59
-
dmac0: dma-controller@e6700000 {
60
-
compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
61
-
reg = <0 0xe6700000 0 0x20000>;
62
-
interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
63
-
0 200 IRQ_TYPE_LEVEL_HIGH
64
-
0 201 IRQ_TYPE_LEVEL_HIGH
65
-
0 202 IRQ_TYPE_LEVEL_HIGH
66
-
0 203 IRQ_TYPE_LEVEL_HIGH
67
-
0 204 IRQ_TYPE_LEVEL_HIGH
68
-
0 205 IRQ_TYPE_LEVEL_HIGH
69
-
0 206 IRQ_TYPE_LEVEL_HIGH
70
-
0 207 IRQ_TYPE_LEVEL_HIGH
71
-
0 208 IRQ_TYPE_LEVEL_HIGH
72
-
0 209 IRQ_TYPE_LEVEL_HIGH
73
-
0 210 IRQ_TYPE_LEVEL_HIGH
74
-
0 211 IRQ_TYPE_LEVEL_HIGH
75
-
0 212 IRQ_TYPE_LEVEL_HIGH
76
-
0 213 IRQ_TYPE_LEVEL_HIGH
77
-
0 214 IRQ_TYPE_LEVEL_HIGH>;
78
-
interrupt-names = "error",
79
-
"ch0", "ch1", "ch2", "ch3",
80
-
"ch4", "ch5", "ch6", "ch7",
81
-
"ch8", "ch9", "ch10", "ch11",
82
-
"ch12", "ch13", "ch14";
83
-
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
84
-
clock-names = "fck";
85
-
#dma-cells = <1>;
86
-
dma-channels = <15>;
87
-
};
88
-
89
-
dmac1: dma-controller@e6720000 {
90
-
compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
91
-
reg = <0 0xe6720000 0 0x20000>;
92
-
interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
93
-
0 216 IRQ_TYPE_LEVEL_HIGH
94
-
0 217 IRQ_TYPE_LEVEL_HIGH
95
-
0 218 IRQ_TYPE_LEVEL_HIGH
96
-
0 219 IRQ_TYPE_LEVEL_HIGH
97
-
0 308 IRQ_TYPE_LEVEL_HIGH
98
-
0 309 IRQ_TYPE_LEVEL_HIGH
99
-
0 310 IRQ_TYPE_LEVEL_HIGH
100
-
0 311 IRQ_TYPE_LEVEL_HIGH
101
-
0 312 IRQ_TYPE_LEVEL_HIGH
102
-
0 313 IRQ_TYPE_LEVEL_HIGH
103
-
0 314 IRQ_TYPE_LEVEL_HIGH
104
-
0 315 IRQ_TYPE_LEVEL_HIGH
105
-
0 316 IRQ_TYPE_LEVEL_HIGH
106
-
0 317 IRQ_TYPE_LEVEL_HIGH
107
-
0 318 IRQ_TYPE_LEVEL_HIGH>;
108
-
interrupt-names = "error",
109
-
"ch0", "ch1", "ch2", "ch3",
110
-
"ch4", "ch5", "ch6", "ch7",
111
-
"ch8", "ch9", "ch10", "ch11",
112
-
"ch12", "ch13", "ch14";
113
-
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
114
-
clock-names = "fck";
115
-
#dma-cells = <1>;
116
-
dma-channels = <15>;
117
-
};
+150
Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
+150
Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Renesas R-Car and RZ/G DMA Controller
8
+
9
+
maintainers:
10
+
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
11
+
12
+
allOf:
13
+
- $ref: "dma-controller.yaml#"
14
+
15
+
properties:
16
+
compatible:
17
+
items:
18
+
- enum:
19
+
- renesas,dmac-r8a7743 # RZ/G1M
20
+
- renesas,dmac-r8a7744 # RZ/G1N
21
+
- renesas,dmac-r8a7745 # RZ/G1E
22
+
- renesas,dmac-r8a77470 # RZ/G1C
23
+
- renesas,dmac-r8a774a1 # RZ/G2M
24
+
- renesas,dmac-r8a774b1 # RZ/G2N
25
+
- renesas,dmac-r8a774c0 # RZ/G2E
26
+
- renesas,dmac-r8a7790 # R-Car H2
27
+
- renesas,dmac-r8a7791 # R-Car M2-W
28
+
- renesas,dmac-r8a7792 # R-Car V2H
29
+
- renesas,dmac-r8a7793 # R-Car M2-N
30
+
- renesas,dmac-r8a7794 # R-Car E2
31
+
- renesas,dmac-r8a7795 # R-Car H3
32
+
- renesas,dmac-r8a7796 # R-Car M3-W
33
+
- renesas,dmac-r8a77961 # R-Car M3-W+
34
+
- renesas,dmac-r8a77965 # R-Car M3-N
35
+
- renesas,dmac-r8a77970 # R-Car V3M
36
+
- renesas,dmac-r8a77980 # R-Car V3H
37
+
- renesas,dmac-r8a77990 # R-Car E3
38
+
- renesas,dmac-r8a77995 # R-Car D3
39
+
- const: renesas,rcar-dmac
40
+
41
+
reg:
42
+
maxItems: 1
43
+
44
+
interrupts:
45
+
minItems: 9
46
+
maxItems: 17
47
+
48
+
interrupt-names:
49
+
minItems: 9
50
+
maxItems: 17
51
+
items:
52
+
- const: error
53
+
- pattern: "^ch([0-9]|1[0-5])$"
54
+
- pattern: "^ch([0-9]|1[0-5])$"
55
+
- pattern: "^ch([0-9]|1[0-5])$"
56
+
- pattern: "^ch([0-9]|1[0-5])$"
57
+
- pattern: "^ch([0-9]|1[0-5])$"
58
+
- pattern: "^ch([0-9]|1[0-5])$"
59
+
- pattern: "^ch([0-9]|1[0-5])$"
60
+
- pattern: "^ch([0-9]|1[0-5])$"
61
+
- pattern: "^ch([0-9]|1[0-5])$"
62
+
- pattern: "^ch([0-9]|1[0-5])$"
63
+
- pattern: "^ch([0-9]|1[0-5])$"
64
+
- pattern: "^ch([0-9]|1[0-5])$"
65
+
- pattern: "^ch([0-9]|1[0-5])$"
66
+
- pattern: "^ch([0-9]|1[0-5])$"
67
+
- pattern: "^ch([0-9]|1[0-5])$"
68
+
- pattern: "^ch([0-9]|1[0-5])$"
69
+
70
+
clocks:
71
+
maxItems: 1
72
+
73
+
clock-names:
74
+
maxItems: 1
75
+
items:
76
+
- const: fck
77
+
78
+
'#dma-cells':
79
+
const: 1
80
+
description:
81
+
The cell specifies the MID/RID of the DMAC port connected to
82
+
the DMA client.
83
+
84
+
dma-channels:
85
+
minimum: 8
86
+
maximum: 16
87
+
88
+
dma-channel-mask: true
89
+
90
+
iommus:
91
+
minItems: 8
92
+
maxItems: 16
93
+
94
+
power-domains:
95
+
maxItems: 1
96
+
97
+
resets:
98
+
maxItems: 1
99
+
100
+
required:
101
+
- compatible
102
+
- reg
103
+
- interrupts
104
+
- interrupt-names
105
+
- clocks
106
+
- clock-names
107
+
- '#dma-cells'
108
+
- dma-channels
109
+
- power-domains
110
+
- resets
111
+
112
+
additionalProperties: false
113
+
114
+
examples:
115
+
- |
116
+
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
117
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
118
+
#include <dt-bindings/power/r8a7790-sysc.h>
119
+
120
+
dmac0: dma-controller@e6700000 {
121
+
compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
122
+
reg = <0xe6700000 0x20000>;
123
+
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
124
+
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
125
+
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
126
+
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
127
+
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
128
+
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
129
+
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
130
+
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
131
+
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
132
+
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
133
+
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
134
+
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
135
+
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
136
+
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
137
+
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
138
+
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
139
+
interrupt-names = "error",
140
+
"ch0", "ch1", "ch2", "ch3",
141
+
"ch4", "ch5", "ch6", "ch7",
142
+
"ch8", "ch9", "ch10", "ch11",
143
+
"ch12", "ch13", "ch14";
144
+
clocks = <&cpg CPG_MOD 219>;
145
+
clock-names = "fck";
146
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
147
+
resets = <&cpg 219>;
148
+
#dma-cells = <1>;
149
+
dma-channels = <15>;
150
+
};
-55
Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
-55
Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
···
1
-
* Renesas USB DMA Controller Device Tree bindings
2
-
3
-
Required Properties:
4
-
-compatible: "renesas,<soctype>-usb-dmac", "renesas,usb-dmac" as fallback.
5
-
Examples with soctypes are:
6
-
- "renesas,r8a7743-usb-dmac" (RZ/G1M)
7
-
- "renesas,r8a7744-usb-dmac" (RZ/G1N)
8
-
- "renesas,r8a7745-usb-dmac" (RZ/G1E)
9
-
- "renesas,r8a77470-usb-dmac" (RZ/G1C)
10
-
- "renesas,r8a774a1-usb-dmac" (RZ/G2M)
11
-
- "renesas,r8a774b1-usb-dmac" (RZ/G2N)
12
-
- "renesas,r8a774c0-usb-dmac" (RZ/G2E)
13
-
- "renesas,r8a7790-usb-dmac" (R-Car H2)
14
-
- "renesas,r8a7791-usb-dmac" (R-Car M2-W)
15
-
- "renesas,r8a7793-usb-dmac" (R-Car M2-N)
16
-
- "renesas,r8a7794-usb-dmac" (R-Car E2)
17
-
- "renesas,r8a7795-usb-dmac" (R-Car H3)
18
-
- "renesas,r8a7796-usb-dmac" (R-Car M3-W)
19
-
- "renesas,r8a77961-usb-dmac" (R-Car M3-W+)
20
-
- "renesas,r8a77965-usb-dmac" (R-Car M3-N)
21
-
- "renesas,r8a77990-usb-dmac" (R-Car E3)
22
-
- "renesas,r8a77995-usb-dmac" (R-Car D3)
23
-
- reg: base address and length of the registers block for the DMAC
24
-
- interrupts: interrupt specifiers for the DMAC, one for each entry in
25
-
interrupt-names.
26
-
- interrupt-names: one entry per channel, named "ch%u", where %u is the
27
-
channel number ranging from zero to the number of channels minus one.
28
-
- clocks: a list of phandle + clock-specifier pairs.
29
-
- #dma-cells: must be <1>, the cell specifies the channel number of the DMAC
30
-
port connected to the DMA client.
31
-
- dma-channels: number of DMA channels
32
-
33
-
Example: R8A7790 (R-Car H2) USB-DMACs
34
-
35
-
usb_dmac0: dma-controller@e65a0000 {
36
-
compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
37
-
reg = <0 0xe65a0000 0 0x100>;
38
-
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
39
-
0 109 IRQ_TYPE_LEVEL_HIGH>;
40
-
interrupt-names = "ch0", "ch1";
41
-
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
42
-
#dma-cells = <1>;
43
-
dma-channels = <2>;
44
-
};
45
-
46
-
usb_dmac1: dma-controller@e65b0000 {
47
-
compatible = "renesas,usb-dmac";
48
-
reg = <0 0xe65b0000 0 0x100>;
49
-
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
50
-
0 110 IRQ_TYPE_LEVEL_HIGH>;
51
-
interrupt-names = "ch0", "ch1";
52
-
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
53
-
#dma-cells = <1>;
54
-
dma-channels = <2>;
55
-
};
+102
Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml
+102
Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/renesas,usb-dmac.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Renesas USB DMA Controller
8
+
9
+
maintainers:
10
+
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
11
+
12
+
allOf:
13
+
- $ref: "dma-controller.yaml#"
14
+
15
+
properties:
16
+
compatible:
17
+
items:
18
+
- enum:
19
+
- renesas,r8a7743-usb-dmac # RZ/G1M
20
+
- renesas,r8a7744-usb-dmac # RZ/G1N
21
+
- renesas,r8a7745-usb-dmac # RZ/G1E
22
+
- renesas,r8a77470-usb-dmac # RZ/G1C
23
+
- renesas,r8a774a1-usb-dmac # RZ/G2M
24
+
- renesas,r8a774b1-usb-dmac # RZ/G2N
25
+
- renesas,r8a774c0-usb-dmac # RZ/G2E
26
+
- renesas,r8a7790-usb-dmac # R-Car H2
27
+
- renesas,r8a7791-usb-dmac # R-Car M2-W
28
+
- renesas,r8a7793-usb-dmac # R-Car M2-N
29
+
- renesas,r8a7794-usb-dmac # R-Car E2
30
+
- renesas,r8a7795-usb-dmac # R-Car H3
31
+
- renesas,r8a7796-usb-dmac # R-Car M3-W
32
+
- renesas,r8a77961-usb-dmac # R-Car M3-W+
33
+
- renesas,r8a77965-usb-dmac # R-Car M3-N
34
+
- renesas,r8a77990-usb-dmac # R-Car E3
35
+
- renesas,r8a77995-usb-dmac # R-Car D3
36
+
- const: renesas,usb-dmac
37
+
38
+
reg:
39
+
maxItems: 1
40
+
41
+
interrupts:
42
+
minItems: 2
43
+
maxItems: 2
44
+
45
+
interrupt-names:
46
+
items:
47
+
- pattern: ch0
48
+
- pattern: ch1
49
+
50
+
clocks:
51
+
maxItems: 1
52
+
53
+
'#dma-cells':
54
+
const: 1
55
+
description:
56
+
The cell specifies the channel number of the DMAC port connected to
57
+
the DMA client.
58
+
59
+
dma-channels:
60
+
const: 2
61
+
62
+
iommus:
63
+
minItems: 2
64
+
maxItems: 2
65
+
66
+
power-domains:
67
+
maxItems: 1
68
+
69
+
resets:
70
+
maxItems: 1
71
+
72
+
required:
73
+
- compatible
74
+
- reg
75
+
- interrupts
76
+
- interrupt-names
77
+
- clocks
78
+
- '#dma-cells'
79
+
- dma-channels
80
+
- power-domains
81
+
- resets
82
+
83
+
additionalProperties: false
84
+
85
+
examples:
86
+
- |
87
+
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
88
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
89
+
#include <dt-bindings/power/r8a7790-sysc.h>
90
+
91
+
usb_dmac0: dma-controller@e65a0000 {
92
+
compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
93
+
reg = <0xe65a0000 0x100>;
94
+
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
95
+
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
96
+
interrupt-names = "ch0", "ch1";
97
+
clocks = <&cpg CPG_MOD 330>;
98
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
99
+
resets = <&cpg 330>;
100
+
#dma-cells = <1>;
101
+
dma-channels = <2>;
102
+
};
+5
Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
+5
Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
···
36
36
0x1: 1/2 full FIFO
37
37
0x2: 3/4 full FIFO
38
38
0x3: full FIFO
39
+
-bit 2: DMA direct mode
40
+
0x0: FIFO mode with threshold selectable with bit 0-1
41
+
0x1: Direct mode: each DMA request immediately initiates a transfer
42
+
from/to the memory, FIFO is bypassed.
43
+
39
44
40
45
maintainers:
41
46
- Amelie Delaunay <amelie.delaunay@st.com>
+1
-3
drivers/dma/Kconfig
+1
-3
drivers/dma/Kconfig
···
106
106
select REGMAP_MMIO
107
107
help
108
108
Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
109
-
controller is often used in Analog Device's reference designs for FPGA
109
+
controller is often used in Analog Devices' reference designs for FPGA
110
110
platforms.
111
111
112
112
config BCM_SBA_RAID
···
395
395
bool "MMP Two-Channel DMA support"
396
396
depends on ARCH_MMP || COMPILE_TEST
397
397
select DMA_ENGINE
398
-
select MMP_SRAM if ARCH_MMP
399
398
select GENERIC_ALLOCATOR
400
399
help
401
400
Support the MMP Two-Channel DMA engine.
402
401
This engine used for MMP Audio DMA and pxa910 SQU.
403
-
It needs sram driver under mach-mmp.
404
402
405
403
config MOXART_DMA
406
404
tristate "MOXART DMA support"
+1
-1
drivers/dma/at_hdmac_regs.h
+1
-1
drivers/dma/at_hdmac_regs.h
+1
-1
drivers/dma/at_xdmac.c
+1
-1
drivers/dma/at_xdmac.c
+52
-46
drivers/dma/dmaengine.c
+52
-46
drivers/dma/dmaengine.c
···
53
53
#include <linux/mempool.h>
54
54
#include <linux/numa.h>
55
55
56
+
#include "dmaengine.h"
57
+
56
58
static DEFINE_MUTEX(dma_list_mutex);
57
59
static DEFINE_IDA(dma_ida);
58
60
static LIST_HEAD(dma_device_list);
···
147
145
148
146
/**
149
147
* dev_to_dma_chan - convert a device pointer to its sysfs container object
150
-
* @dev - device node
148
+
* @dev: device node
151
149
*
152
-
* Must be called under dma_list_mutex
150
+
* Must be called under dma_list_mutex.
153
151
*/
154
152
static struct dma_chan *dev_to_dma_chan(struct device *dev)
155
153
{
···
245
243
246
244
/* --- client and device registration --- */
247
245
248
-
/**
249
-
* dma_cap_mask_all - enable iteration over all operation types
250
-
*/
246
+
/* enable iteration over all operation types */
251
247
static dma_cap_mask_t dma_cap_mask_all;
252
248
253
249
/**
254
-
* dma_chan_tbl_ent - tracks channel allocations per core/operation
255
-
* @chan - associated channel for this entry
250
+
* struct dma_chan_tbl_ent - tracks channel allocations per core/operation
251
+
* @chan: associated channel for this entry
256
252
*/
257
253
struct dma_chan_tbl_ent {
258
254
struct dma_chan *chan;
259
255
};
260
256
261
-
/**
262
-
* channel_table - percpu lookup table for memory-to-memory offload providers
263
-
*/
257
+
/* percpu lookup table for memory-to-memory offload providers */
264
258
static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
265
259
266
260
static int __init dma_channel_table_init(void)
···
293
295
arch_initcall(dma_channel_table_init);
294
296
295
297
/**
296
-
* dma_chan_is_local - returns true if the channel is in the same numa-node as
297
-
* the cpu
298
+
* dma_chan_is_local - checks if the channel is in the same NUMA-node as the CPU
299
+
* @chan: DMA channel to test
300
+
* @cpu: CPU index which the channel should be close to
301
+
*
302
+
* Returns true if the channel is in the same NUMA-node as the CPU.
298
303
*/
299
304
static bool dma_chan_is_local(struct dma_chan *chan, int cpu)
300
305
{
···
307
306
}
308
307
309
308
/**
310
-
* min_chan - returns the channel with min count and in the same numa-node as
311
-
* the cpu
312
-
* @cap: capability to match
313
-
* @cpu: cpu index which the channel should be close to
309
+
* min_chan - finds the channel with min count and in the same NUMA-node as the CPU
310
+
* @cap: capability to match
311
+
* @cpu: CPU index which the channel should be close to
314
312
*
315
-
* If some channels are close to the given cpu, the one with the lowest
316
-
* reference count is returned. Otherwise, cpu is ignored and only the
313
+
* If some channels are close to the given CPU, the one with the lowest
314
+
* reference count is returned. Otherwise, CPU is ignored and only the
317
315
* reference count is taken into account.
316
+
*
318
317
* Must be called under dma_list_mutex.
319
318
*/
320
319
static struct dma_chan *min_chan(enum dma_transaction_type cap, int cpu)
···
352
351
/**
353
352
* dma_channel_rebalance - redistribute the available channels
354
353
*
355
-
* Optimize for cpu isolation (each cpu gets a dedicated channel for an
356
-
* operation type) in the SMP case, and operation isolation (avoid
357
-
* multi-tasking channels) in the non-SMP case. Must be called under
358
-
* dma_list_mutex.
354
+
* Optimize for CPU isolation (each CPU gets a dedicated channel for an
355
+
* operation type) in the SMP case, and operation isolation (avoid
356
+
* multi-tasking channels) in the non-SMP case.
357
+
*
358
+
* Must be called under dma_list_mutex.
359
359
*/
360
360
static void dma_channel_rebalance(void)
361
361
{
···
406
404
407
405
/**
408
406
* balance_ref_count - catch up the channel reference count
409
-
* @chan - channel to balance ->client_count versus dmaengine_ref_count
407
+
* @chan: channel to balance ->client_count versus dmaengine_ref_count
410
408
*
411
-
* balance_ref_count must be called under dma_list_mutex
409
+
* Must be called under dma_list_mutex.
412
410
*/
413
411
static void balance_ref_count(struct dma_chan *chan)
414
412
{
···
438
436
}
439
437
440
438
/**
441
-
* dma_chan_get - try to grab a dma channel's parent driver module
442
-
* @chan - channel to grab
439
+
* dma_chan_get - try to grab a DMA channel's parent driver module
440
+
* @chan: channel to grab
443
441
*
444
-
* Must be called under dma_list_mutex
442
+
* Must be called under dma_list_mutex.
445
443
*/
446
444
static int dma_chan_get(struct dma_chan *chan)
447
445
{
···
485
483
}
486
484
487
485
/**
488
-
* dma_chan_put - drop a reference to a dma channel's parent driver module
489
-
* @chan - channel to release
486
+
* dma_chan_put - drop a reference to a DMA channel's parent driver module
487
+
* @chan: channel to release
490
488
*
491
-
* Must be called under dma_list_mutex
489
+
* Must be called under dma_list_mutex.
492
490
*/
493
491
static void dma_chan_put(struct dma_chan *chan)
494
492
{
···
539
537
540
538
/**
541
539
* dma_find_channel - find a channel to carry out the operation
542
-
* @tx_type: transaction type
540
+
* @tx_type: transaction type
543
541
*/
544
542
struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
545
543
{
···
679
677
680
678
/**
681
679
* dma_get_slave_channel - try to get specific channel exclusively
682
-
* @chan: target channel
680
+
* @chan: target channel
683
681
*/
684
682
struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
685
683
{
···
733
731
734
732
/**
735
733
* __dma_request_channel - try to allocate an exclusive channel
736
-
* @mask: capabilities that the channel must satisfy
737
-
* @fn: optional callback to disposition available channels
738
-
* @fn_param: opaque parameter to pass to dma_filter_fn
739
-
* @np: device node to look for DMA channels
734
+
* @mask: capabilities that the channel must satisfy
735
+
* @fn: optional callback to disposition available channels
736
+
* @fn_param: opaque parameter to pass to dma_filter_fn()
737
+
* @np: device node to look for DMA channels
740
738
*
741
739
* Returns pointer to appropriate DMA channel on success or NULL.
742
740
*/
···
879
877
880
878
/**
881
879
* dma_request_chan_by_mask - allocate a channel satisfying certain capabilities
882
-
* @mask: capabilities that the channel must satisfy
880
+
* @mask: capabilities that the channel must satisfy
883
881
*
884
882
* Returns pointer to appropriate DMA channel on success or an error pointer.
885
883
*/
···
970
968
EXPORT_SYMBOL(dmaengine_get);
971
969
972
970
/**
973
-
* dmaengine_put - let dma drivers be removed when ref_count == 0
971
+
* dmaengine_put - let DMA drivers be removed when ref_count == 0
974
972
*/
975
973
void dmaengine_put(void)
976
974
{
···
1134
1132
1135
1133
/**
1136
1134
* dma_async_device_register - registers DMA devices found
1137
-
* @device: &dma_device
1135
+
* @device: pointer to &struct dma_device
1138
1136
*
1139
1137
* After calling this routine the structure should not be freed except in the
1140
1138
* device_release() callback which will be called after
···
1306
1304
1307
1305
/**
1308
1306
* dma_async_device_unregister - unregister a DMA device
1309
-
* @device: &dma_device
1307
+
* @device: pointer to &struct dma_device
1310
1308
*
1311
1309
* This routine is called by dma driver exit routines, dmaengine holds module
1312
1310
* references to prevent it being called while channels are in use.
···
1343
1341
1344
1342
/**
1345
1343
* dmaenginem_async_device_register - registers DMA devices found
1346
-
* @device: &dma_device
1344
+
* @device: pointer to &struct dma_device
1347
1345
*
1348
1346
* The operation is managed and will be undone on driver detach.
1349
1347
*/
···
1580
1578
}
1581
1579
EXPORT_SYMBOL_GPL(dmaengine_desc_set_metadata_len);
1582
1580
1583
-
/* dma_wait_for_async_tx - spin wait for a transaction to complete
1584
-
* @tx: in-flight transaction to wait on
1581
+
/**
1582
+
* dma_wait_for_async_tx - spin wait for a transaction to complete
1583
+
* @tx: in-flight transaction to wait on
1585
1584
*/
1586
1585
enum dma_status
1587
1586
dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
···
1605
1602
}
1606
1603
EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
1607
1604
1608
-
/* dma_run_dependencies - helper routine for dma drivers to process
1609
-
* (start) dependent operations on their target channel
1610
-
* @tx: transaction with dependencies
1605
+
/**
1606
+
* dma_run_dependencies - process dependent operations on the target channel
1607
+
* @tx: transaction with dependencies
1608
+
*
1609
+
* Helper routine for DMA drivers to process (start) dependent operations
1610
+
* on their target channel.
1611
1611
*/
1612
1612
void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
1613
1613
{
+16
-8
drivers/dma/dmatest.c
+16
-8
drivers/dma/dmatest.c
···
60
60
"Number of p+q source buffers (default: 3)");
61
61
62
62
static int timeout = 3000;
63
-
module_param(timeout, uint, S_IRUGO | S_IWUSR);
63
+
module_param(timeout, int, S_IRUGO | S_IWUSR);
64
64
MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
65
-
"Pass 0xFFFFFFFF (4294967295) for maximum timeout");
65
+
"Pass -1 for infinite timeout");
66
66
67
67
static bool noverify;
68
68
module_param(noverify, bool, S_IRUGO | S_IWUSR);
···
71
71
static bool norandom;
72
72
module_param(norandom, bool, 0644);
73
73
MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)");
74
-
75
-
static bool polled;
76
-
module_param(polled, bool, S_IRUGO | S_IWUSR);
77
-
MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");
78
74
79
75
static bool verbose;
80
76
module_param(verbose, bool, S_IRUGO | S_IWUSR);
···
84
88
module_param(transfer_size, uint, 0644);
85
89
MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))");
86
90
91
+
static bool polled;
92
+
module_param(polled, bool, S_IRUGO | S_IWUSR);
93
+
MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");
94
+
87
95
/**
88
96
* struct dmatest_params - test parameters.
89
97
* @buf_size: size of the memcpy test buffer
···
98
98
* @iterations: iterations before stopping test
99
99
* @xor_sources: number of xor source buffers
100
100
* @pq_sources: number of p+q source buffers
101
-
* @timeout: transfer timeout in msec, 0 - 0xFFFFFFFF (4294967295)
101
+
* @timeout: transfer timeout in msec, -1 for infinite timeout
102
+
* @noverify: disable data verification
103
+
* @norandom: disable random offset setup
104
+
* @alignment: custom data address alignment taken as 2^alignment
105
+
* @transfer_size: custom transfer size in bytes
106
+
* @polled: use polling for completion instead of interrupts
102
107
*/
103
108
struct dmatest_params {
104
109
unsigned int buf_size;
···
114
109
unsigned int iterations;
115
110
unsigned int xor_sources;
116
111
unsigned int pq_sources;
117
-
unsigned int timeout;
112
+
int timeout;
118
113
bool noverify;
119
114
bool norandom;
120
115
int alignment;
···
125
120
/**
126
121
* struct dmatest_info - test information.
127
122
* @params: test parameters
123
+
* @channels: channels under test
124
+
* @nr_channels: number of channels under test
128
125
* @lock: access protection to the fields of this structure
126
+
* @did_init: module has been initialized completely
129
127
*/
130
128
static struct dmatest_info {
131
129
/* Test parameters */
+46
-19
drivers/dma/dw-edma/dw-edma-core.c
+46
-19
drivers/dma/dw-edma/dw-edma-core.c
···
13
13
#include <linux/dmaengine.h>
14
14
#include <linux/err.h>
15
15
#include <linux/interrupt.h>
16
+
#include <linux/irq.h>
16
17
#include <linux/dma/edma.h>
17
-
#include <linux/pci.h>
18
+
#include <linux/dma-mapping.h>
18
19
19
20
#include "dw-edma-core.h"
20
21
#include "dw-edma-v0-core.h"
···
323
322
dw_edma_device_transfer(struct dw_edma_transfer *xfer)
324
323
{
325
324
struct dw_edma_chan *chan = dchan2dw_edma_chan(xfer->dchan);
326
-
enum dma_transfer_direction direction = xfer->direction;
325
+
enum dma_transfer_direction dir = xfer->direction;
327
326
phys_addr_t src_addr, dst_addr;
328
327
struct scatterlist *sg = NULL;
329
328
struct dw_edma_chunk *chunk;
···
332
331
u32 cnt;
333
332
int i;
334
333
335
-
if ((direction == DMA_MEM_TO_DEV && chan->dir == EDMA_DIR_WRITE) ||
336
-
(direction == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_READ))
334
+
if (!chan->configured)
337
335
return NULL;
336
+
337
+
switch (chan->config.direction) {
338
+
case DMA_DEV_TO_MEM: /* local dma */
339
+
if (dir == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_READ)
340
+
break;
341
+
return NULL;
342
+
case DMA_MEM_TO_DEV: /* local dma */
343
+
if (dir == DMA_MEM_TO_DEV && chan->dir == EDMA_DIR_WRITE)
344
+
break;
345
+
return NULL;
346
+
default: /* remote dma */
347
+
if (dir == DMA_MEM_TO_DEV && chan->dir == EDMA_DIR_READ)
348
+
break;
349
+
if (dir == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_WRITE)
350
+
break;
351
+
return NULL;
352
+
}
338
353
339
354
if (xfer->cyclic) {
340
355
if (!xfer->xfer.cyclic.len || !xfer->xfer.cyclic.cnt)
···
359
342
if (xfer->xfer.sg.len < 1)
360
343
return NULL;
361
344
}
362
-
363
-
if (!chan->configured)
364
-
return NULL;
365
345
366
346
desc = dw_edma_alloc_desc(chan);
367
347
if (unlikely(!desc))
···
400
386
chunk->ll_region.sz += burst->sz;
401
387
desc->alloc_sz += burst->sz;
402
388
403
-
if (direction == DMA_DEV_TO_MEM) {
389
+
if (chan->dir == EDMA_DIR_WRITE) {
404
390
burst->sar = src_addr;
405
391
if (xfer->cyclic) {
406
392
burst->dar = xfer->xfer.cyclic.paddr;
···
787
773
u32 rd_mask = 1;
788
774
int i, err = 0;
789
775
u32 ch_cnt;
776
+
int irq;
790
777
791
778
ch_cnt = dw->wr_ch_cnt + dw->rd_ch_cnt;
792
779
···
796
781
797
782
if (dw->nr_irqs == 1) {
798
783
/* Common IRQ shared among all channels */
799
-
err = request_irq(pci_irq_vector(to_pci_dev(dev), 0),
800
-
dw_edma_interrupt_common,
784
+
irq = dw->ops->irq_vector(dev, 0);
785
+
err = request_irq(irq, dw_edma_interrupt_common,
801
786
IRQF_SHARED, dw->name, &dw->irq[0]);
802
787
if (err) {
803
788
dw->nr_irqs = 0;
804
789
return err;
805
790
}
806
791
807
-
get_cached_msi_msg(pci_irq_vector(to_pci_dev(dev), 0),
808
-
&dw->irq[0].msi);
792
+
if (irq_get_msi_desc(irq))
793
+
get_cached_msi_msg(irq, &dw->irq[0].msi);
809
794
} else {
810
795
/* Distribute IRQs equally among all channels */
811
796
int tmp = dw->nr_irqs;
···
819
804
dw_edma_add_irq_mask(&rd_mask, *rd_alloc, dw->rd_ch_cnt);
820
805
821
806
for (i = 0; i < (*wr_alloc + *rd_alloc); i++) {
822
-
err = request_irq(pci_irq_vector(to_pci_dev(dev), i),
807
+
irq = dw->ops->irq_vector(dev, i);
808
+
err = request_irq(irq,
823
809
i < *wr_alloc ?
824
810
dw_edma_interrupt_write :
825
811
dw_edma_interrupt_read,
···
831
815
return err;
832
816
}
833
817
834
-
get_cached_msi_msg(pci_irq_vector(to_pci_dev(dev), i),
835
-
&dw->irq[i].msi);
818
+
if (irq_get_msi_desc(irq))
819
+
get_cached_msi_msg(irq, &dw->irq[i].msi);
836
820
}
837
821
838
822
dw->nr_irqs = i;
···
843
827
844
828
int dw_edma_probe(struct dw_edma_chip *chip)
845
829
{
846
-
struct device *dev = chip->dev;
847
-
struct dw_edma *dw = chip->dw;
830
+
struct device *dev;
831
+
struct dw_edma *dw;
848
832
u32 wr_alloc = 0;
849
833
u32 rd_alloc = 0;
850
834
int i, err;
835
+
836
+
if (!chip)
837
+
return -EINVAL;
838
+
839
+
dev = chip->dev;
840
+
if (!dev)
841
+
return -EINVAL;
842
+
843
+
dw = chip->dw;
844
+
if (!dw || !dw->irq || !dw->ops || !dw->ops->irq_vector)
845
+
return -EINVAL;
851
846
852
847
raw_spin_lock_init(&dw->lock);
853
848
···
911
884
912
885
err_irq_free:
913
886
for (i = (dw->nr_irqs - 1); i >= 0; i--)
914
-
free_irq(pci_irq_vector(to_pci_dev(dev), i), &dw->irq[i]);
887
+
free_irq(dw->ops->irq_vector(dev, i), &dw->irq[i]);
915
888
916
889
dw->nr_irqs = 0;
917
890
···
931
904
932
905
/* Free irqs */
933
906
for (i = (dw->nr_irqs - 1); i >= 0; i--)
934
-
free_irq(pci_irq_vector(to_pci_dev(dev), i), &dw->irq[i]);
907
+
free_irq(dw->ops->irq_vector(dev, i), &dw->irq[i]);
935
908
936
909
/* Power management */
937
910
pm_runtime_disable(dev);
+4
drivers/dma/dw-edma/dw-edma-core.h
+4
drivers/dma/dw-edma/dw-edma-core.h
+10
drivers/dma/dw-edma/dw-edma-pcie.c
+10
drivers/dma/dw-edma/dw-edma-pcie.c
···
54
54
.irqs = 1,
55
55
};
56
56
57
+
static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr)
58
+
{
59
+
return pci_irq_vector(to_pci_dev(dev), nr);
60
+
}
61
+
62
+
static const struct dw_edma_core_ops dw_edma_pcie_core_ops = {
63
+
.irq_vector = dw_edma_pcie_irq_vector,
64
+
};
65
+
57
66
static int dw_edma_pcie_probe(struct pci_dev *pdev,
58
67
const struct pci_device_id *pid)
59
68
{
···
160
151
dw->version = pdata->version;
161
152
dw->mode = pdata->mode;
162
153
dw->nr_irqs = nr_irqs;
154
+
dw->ops = &dw_edma_pcie_core_ops;
163
155
164
156
/* Debug info */
165
157
pci_dbg(pdev, "Version:\t%u\n", dw->version);
+11
drivers/dma/idxd/sysfs.c
+11
drivers/dma/idxd/sysfs.c
···
1092
1092
};
1093
1093
1094
1094
/* IDXD device attribs */
1095
+
static ssize_t version_show(struct device *dev, struct device_attribute *attr,
1096
+
char *buf)
1097
+
{
1098
+
struct idxd_device *idxd =
1099
+
container_of(dev, struct idxd_device, conf_dev);
1100
+
1101
+
return sprintf(buf, "%#x\n", idxd->hw.version);
1102
+
}
1103
+
static DEVICE_ATTR_RO(version);
1104
+
1095
1105
static ssize_t max_work_queues_size_show(struct device *dev,
1096
1106
struct device_attribute *attr,
1097
1107
char *buf)
···
1323
1313
static DEVICE_ATTR_RO(cdev_major);
1324
1314
1325
1315
static struct attribute *idxd_device_attributes[] = {
1316
+
&dev_attr_version.attr,
1326
1317
&dev_attr_max_groups.attr,
1327
1318
&dev_attr_max_work_queues.attr,
1328
1319
&dev_attr_max_work_queues_size.attr,
+1
-1
drivers/dma/imx-sdma.c
+1
-1
drivers/dma/imx-sdma.c
···
2063
2063
2064
2064
/* initially no scripts available */
2065
2065
saddr_arr = (s32 *)sdma->script_addrs;
2066
-
for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
2066
+
for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++)
2067
2067
saddr_arr[i] = -EINVAL;
2068
2068
2069
2069
dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
+50
-39
drivers/dma/ioat/dma.c
+50
-39
drivers/dma/ioat/dma.c
···
332
332
u8 *pos;
333
333
off_t offs;
334
334
335
-
chunk = idx / IOAT_DESCS_PER_2M;
336
-
idx &= (IOAT_DESCS_PER_2M - 1);
335
+
chunk = idx / IOAT_DESCS_PER_CHUNK;
336
+
idx &= (IOAT_DESCS_PER_CHUNK - 1);
337
337
offs = idx * IOAT_DESC_SZ;
338
338
pos = (u8 *)ioat_chan->descs[chunk].virt + offs;
339
339
phys = ioat_chan->descs[chunk].hw + offs;
···
370
370
if (!ring)
371
371
return NULL;
372
372
373
-
ioat_chan->desc_chunks = chunks = (total_descs * IOAT_DESC_SZ) / SZ_2M;
373
+
chunks = (total_descs * IOAT_DESC_SZ) / IOAT_CHUNK_SIZE;
374
+
ioat_chan->desc_chunks = chunks;
374
375
375
376
for (i = 0; i < chunks; i++) {
376
377
struct ioat_descs *descs = &ioat_chan->descs[i];
···
383
382
384
383
for (idx = 0; idx < i; idx++) {
385
384
descs = &ioat_chan->descs[idx];
386
-
dma_free_coherent(to_dev(ioat_chan), SZ_2M,
387
-
descs->virt, descs->hw);
385
+
dma_free_coherent(to_dev(ioat_chan),
386
+
IOAT_CHUNK_SIZE,
387
+
descs->virt, descs->hw);
388
388
descs->virt = NULL;
389
389
descs->hw = 0;
390
390
}
···
406
404
407
405
for (idx = 0; idx < ioat_chan->desc_chunks; idx++) {
408
406
dma_free_coherent(to_dev(ioat_chan),
409
-
SZ_2M,
407
+
IOAT_CHUNK_SIZE,
410
408
ioat_chan->descs[idx].virt,
411
409
ioat_chan->descs[idx].hw);
412
410
ioat_chan->descs[idx].virt = NULL;
···
869
867
mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
870
868
}
871
869
870
+
static void ioat_reboot_chan(struct ioatdma_chan *ioat_chan)
871
+
{
872
+
spin_lock_bh(&ioat_chan->prep_lock);
873
+
set_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
874
+
spin_unlock_bh(&ioat_chan->prep_lock);
875
+
876
+
ioat_abort_descs(ioat_chan);
877
+
dev_warn(to_dev(ioat_chan), "Reset channel...\n");
878
+
ioat_reset_hw(ioat_chan);
879
+
dev_warn(to_dev(ioat_chan), "Restart channel...\n");
880
+
ioat_restart_channel(ioat_chan);
881
+
882
+
spin_lock_bh(&ioat_chan->prep_lock);
883
+
clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
884
+
spin_unlock_bh(&ioat_chan->prep_lock);
885
+
}
886
+
872
887
void ioat_timer_event(struct timer_list *t)
873
888
{
874
889
struct ioatdma_chan *ioat_chan = from_timer(ioat_chan, t, timer);
···
908
889
909
890
if (test_bit(IOAT_RUN, &ioat_chan->state)) {
910
891
spin_lock_bh(&ioat_chan->cleanup_lock);
911
-
spin_lock_bh(&ioat_chan->prep_lock);
912
-
set_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
913
-
spin_unlock_bh(&ioat_chan->prep_lock);
914
-
915
-
ioat_abort_descs(ioat_chan);
916
-
dev_warn(to_dev(ioat_chan), "Reset channel...\n");
917
-
ioat_reset_hw(ioat_chan);
918
-
dev_warn(to_dev(ioat_chan), "Restart channel...\n");
919
-
ioat_restart_channel(ioat_chan);
920
-
921
-
spin_lock_bh(&ioat_chan->prep_lock);
922
-
clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
923
-
spin_unlock_bh(&ioat_chan->prep_lock);
892
+
ioat_reboot_chan(ioat_chan);
924
893
spin_unlock_bh(&ioat_chan->cleanup_lock);
925
894
}
926
895
···
922
915
spin_lock_bh(&ioat_chan->prep_lock);
923
916
check_active(ioat_chan);
924
917
spin_unlock_bh(&ioat_chan->prep_lock);
925
-
spin_unlock_bh(&ioat_chan->cleanup_lock);
926
-
return;
918
+
goto unlock_out;
919
+
}
920
+
921
+
/* handle the missed cleanup case */
922
+
if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) {
923
+
/* timer restarted in ioat_cleanup_preamble
924
+
* and IOAT_COMPLETION_ACK cleared
925
+
*/
926
+
__cleanup(ioat_chan, phys_complete);
927
+
goto unlock_out;
927
928
}
928
929
929
930
/* if we haven't made progress and we have already
930
931
* acknowledged a pending completion once, then be more
931
932
* forceful with a restart
932
933
*/
933
-
if (ioat_cleanup_preamble(ioat_chan, &phys_complete))
934
-
__cleanup(ioat_chan, phys_complete);
935
-
else if (test_bit(IOAT_COMPLETION_ACK, &ioat_chan->state)) {
934
+
if (test_bit(IOAT_COMPLETION_ACK, &ioat_chan->state)) {
936
935
u32 chanerr;
937
936
938
937
chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
···
950
937
dev_dbg(to_dev(ioat_chan), "Active descriptors: %d\n",
951
938
ioat_ring_active(ioat_chan));
952
939
940
+
ioat_reboot_chan(ioat_chan);
941
+
942
+
goto unlock_out;
943
+
}
944
+
945
+
/* handle missed issue pending case */
946
+
if (ioat_ring_pending(ioat_chan)) {
947
+
dev_warn(to_dev(ioat_chan),
948
+
"Completion timeout with pending descriptors\n");
953
949
spin_lock_bh(&ioat_chan->prep_lock);
954
-
set_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
950
+
__ioat_issue_pending(ioat_chan);
955
951
spin_unlock_bh(&ioat_chan->prep_lock);
952
+
}
956
953
957
-
ioat_abort_descs(ioat_chan);
958
-
dev_warn(to_dev(ioat_chan), "Resetting channel...\n");
959
-
ioat_reset_hw(ioat_chan);
960
-
dev_warn(to_dev(ioat_chan), "Restarting channel...\n");
961
-
ioat_restart_channel(ioat_chan);
962
-
963
-
spin_lock_bh(&ioat_chan->prep_lock);
964
-
clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
965
-
spin_unlock_bh(&ioat_chan->prep_lock);
966
-
spin_unlock_bh(&ioat_chan->cleanup_lock);
967
-
return;
968
-
} else
969
-
set_bit(IOAT_COMPLETION_ACK, &ioat_chan->state);
970
-
954
+
set_bit(IOAT_COMPLETION_ACK, &ioat_chan->state);
971
955
mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
956
+
unlock_out:
972
957
spin_unlock_bh(&ioat_chan->cleanup_lock);
973
958
}
974
959
+6
-4
drivers/dma/ioat/dma.h
+6
-4
drivers/dma/ioat/dma.h
···
81
81
u32 msixpba;
82
82
};
83
83
84
+
#define IOAT_MAX_ORDER 16
85
+
#define IOAT_MAX_DESCS (1 << IOAT_MAX_ORDER)
86
+
#define IOAT_CHUNK_SIZE (SZ_512K)
87
+
#define IOAT_DESCS_PER_CHUNK (IOAT_CHUNK_SIZE / IOAT_DESC_SZ)
88
+
84
89
struct ioat_descs {
85
90
void *virt;
86
91
dma_addr_t hw;
···
133
128
u16 produce;
134
129
struct ioat_ring_ent **ring;
135
130
spinlock_t prep_lock;
136
-
struct ioat_descs descs[2];
131
+
struct ioat_descs descs[IOAT_MAX_DESCS / IOAT_DESCS_PER_CHUNK];
137
132
int desc_chunks;
138
133
int intr_coalesce;
139
134
int prev_intr_coalesce;
···
306
301
return !!err;
307
302
}
308
303
309
-
#define IOAT_MAX_ORDER 16
310
-
#define IOAT_MAX_DESCS 65536
311
-
#define IOAT_DESCS_PER_2M 32768
312
304
313
305
static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan)
314
306
{
+1
-1
drivers/dma/ioat/init.c
+1
-1
drivers/dma/ioat/init.c
+22
-4
drivers/dma/mmp_tdma.c
+22
-4
drivers/dma/mmp_tdma.c
···
235
235
tdcr |= TDCR_BURSTSZ_128B;
236
236
break;
237
237
default:
238
-
dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
238
+
dev_err(tdmac->dev, "unknown burst size.\n");
239
239
return -EINVAL;
240
240
}
241
241
···
250
250
tdcr |= TDCR_SSZ_32_BITS;
251
251
break;
252
252
default:
253
-
dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n");
253
+
dev_err(tdmac->dev, "unknown bus size.\n");
254
254
return -EINVAL;
255
255
}
256
256
} else if (tdmac->type == PXA910_SQU) {
···
276
276
tdcr |= TDCR_BURSTSZ_SQU_32B;
277
277
break;
278
278
default:
279
-
dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
279
+
dev_err(tdmac->dev, "unknown burst size.\n");
280
280
return -EINVAL;
281
281
}
282
282
}
···
429
429
int num_periods = buf_len / period_len;
430
430
int i = 0, buf = 0;
431
431
432
-
if (tdmac->status != DMA_COMPLETE)
432
+
if (!is_slave_direction(direction)) {
433
+
dev_err(tdmac->dev, "unsupported transfer direction\n");
433
434
return NULL;
435
+
}
436
+
437
+
if (tdmac->status != DMA_COMPLETE) {
438
+
dev_err(tdmac->dev, "controller busy");
439
+
return NULL;
440
+
}
434
441
435
442
if (period_len > TDMA_MAX_XFER_BYTES) {
436
443
dev_err(tdmac->dev,
···
710
703
tdev->device.device_resume = mmp_tdma_resume_chan;
711
704
tdev->device.device_terminate_all = mmp_tdma_terminate_all;
712
705
tdev->device.copy_align = DMAENGINE_ALIGN_8_BYTES;
706
+
707
+
tdev->device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
708
+
if (type == MMP_AUD_TDMA) {
709
+
tdev->device.max_burst = SZ_128;
710
+
tdev->device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
711
+
tdev->device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
712
+
} else if (type == PXA910_SQU) {
713
+
tdev->device.max_burst = SZ_32;
714
+
}
715
+
tdev->device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
716
+
tdev->device.descriptor_reuse = true;
713
717
714
718
dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
715
719
platform_set_drvdata(pdev, tdev);
+1
-1
drivers/dma/moxart-dma.c
+1
-1
drivers/dma/moxart-dma.c
+1
-1
drivers/dma/qcom/bam_dma.c
+1
-1
drivers/dma/qcom/bam_dma.c
+1
-2
drivers/dma/qcom/hidma.c
+1
-2
drivers/dma/qcom/hidma.c
···
550
550
kfree(mdesc);
551
551
}
552
552
553
-
mchan->allocated = 0;
553
+
mchan->allocated = false;
554
554
spin_unlock_irqrestore(&mchan->lock, irqflags);
555
555
}
556
556
···
897
897
if (msi)
898
898
hidma_free_msis(dmadev);
899
899
900
-
hidma_debug_uninit(dmadev);
901
900
hidma_ll_uninit(dmadev->lldev);
902
901
dmafree:
903
902
if (dmadev)
+7
-18
drivers/dma/sf-pdma/sf-pdma.c
+7
-18
drivers/dma/sf-pdma/sf-pdma.c
···
506
506
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
507
507
pdma->membase = devm_ioremap_resource(&pdev->dev, res);
508
508
if (IS_ERR(pdma->membase))
509
-
goto ERR_MEMBASE;
509
+
return PTR_ERR(pdma->membase);
510
510
511
511
ret = sf_pdma_irq_init(pdev, pdma);
512
512
if (ret)
513
-
goto ERR_INITIRQ;
513
+
return ret;
514
514
515
515
sf_pdma_setup_chans(pdma);
516
516
···
544
544
"Failed to set DMA mask. Fall back to default.\n");
545
545
546
546
ret = dma_async_device_register(&pdma->dma_dev);
547
-
if (ret)
548
-
goto ERR_REG_DMADEVICE;
547
+
if (ret) {
548
+
dev_err(&pdev->dev,
549
+
"Can't register SiFive Platform DMA. (%d)\n", ret);
550
+
return ret;
551
+
}
549
552
550
553
return 0;
551
-
552
-
ERR_MEMBASE:
553
-
devm_kfree(&pdev->dev, pdma);
554
-
return PTR_ERR(pdma->membase);
555
-
556
-
ERR_INITIRQ:
557
-
devm_kfree(&pdev->dev, pdma);
558
-
return ret;
559
-
560
-
ERR_REG_DMADEVICE:
561
-
devm_kfree(&pdev->dev, pdma);
562
-
dev_err(&pdev->dev,
563
-
"Can't register SiFive Platform DMA. (%d)\n", ret);
564
-
return ret;
565
554
}
566
555
567
556
static int sf_pdma_remove(struct platform_device *pdev)
+31
-10
drivers/dma/stm32-dma.c
+31
-10
drivers/dma/stm32-dma.c
···
117
117
#define STM32_DMA_FIFO_THRESHOLD_HALFFULL 0x01
118
118
#define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL 0x02
119
119
#define STM32_DMA_FIFO_THRESHOLD_FULL 0x03
120
+
#define STM32_DMA_FIFO_THRESHOLD_NONE 0x04
120
121
121
122
#define STM32_DMA_MAX_DATA_ITEMS 0xffff
122
123
/*
···
137
136
/* DMA Features */
138
137
#define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0)
139
138
#define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK)
139
+
#define STM32_DMA_DIRECT_MODE_MASK BIT(2)
140
+
#define STM32_DMA_DIRECT_MODE_GET(n) (((n) & STM32_DMA_DIRECT_MODE_MASK) \
141
+
>> 2)
140
142
141
143
enum stm32_dma_width {
142
144
STM32_DMA_BYTE,
···
285
281
{
286
282
u32 remaining;
287
283
284
+
if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE)
285
+
return false;
286
+
288
287
if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) {
289
288
if (burst != 0) {
290
289
/*
···
309
302
310
303
static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold)
311
304
{
305
+
/* If FIFO direct mode, burst is not possible */
306
+
if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE)
307
+
return false;
308
+
312
309
/*
313
310
* Buffer or period length has to be aligned on FIFO depth.
314
311
* Otherwise bytes may be stuck within FIFO at buffer or period
···
668
657
dev_dbg(chan2dev(chan), "FIFO over/underrun\n");
669
658
}
670
659
}
660
+
if (status & STM32_DMA_DMEI) {
661
+
stm32_dma_irq_clear(chan, STM32_DMA_DMEI);
662
+
status &= ~STM32_DMA_DMEI;
663
+
if (sfcr & STM32_DMA_SCR_DMEIE)
664
+
dev_dbg(chan2dev(chan), "Direct mode overrun\n");
665
+
}
671
666
if (status) {
672
667
stm32_dma_irq_clear(chan, status);
673
668
dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
···
709
692
int src_bus_width, dst_bus_width;
710
693
int src_burst_size, dst_burst_size;
711
694
u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst;
712
-
u32 dma_scr, threshold;
695
+
u32 dma_scr, fifoth;
713
696
714
697
src_addr_width = chan->dma_sconfig.src_addr_width;
715
698
dst_addr_width = chan->dma_sconfig.dst_addr_width;
716
699
src_maxburst = chan->dma_sconfig.src_maxburst;
717
700
dst_maxburst = chan->dma_sconfig.dst_maxburst;
718
-
threshold = chan->threshold;
701
+
fifoth = chan->threshold;
719
702
720
703
switch (direction) {
721
704
case DMA_MEM_TO_DEV:
···
727
710
/* Set device burst size */
728
711
dst_best_burst = stm32_dma_get_best_burst(buf_len,
729
712
dst_maxburst,
730
-
threshold,
713
+
fifoth,
731
714
dst_addr_width);
732
715
733
716
dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
···
735
718
return dst_burst_size;
736
719
737
720
/* Set memory data size */
738
-
src_addr_width = stm32_dma_get_max_width(buf_len, threshold);
721
+
src_addr_width = stm32_dma_get_max_width(buf_len, fifoth);
739
722
chan->mem_width = src_addr_width;
740
723
src_bus_width = stm32_dma_get_width(chan, src_addr_width);
741
724
if (src_bus_width < 0)
···
745
728
src_maxburst = STM32_DMA_MAX_BURST;
746
729
src_best_burst = stm32_dma_get_best_burst(buf_len,
747
730
src_maxburst,
748
-
threshold,
731
+
fifoth,
749
732
src_addr_width);
750
733
src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
751
734
if (src_burst_size < 0)
···
759
742
760
743
/* Set FIFO threshold */
761
744
chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
762
-
chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);
745
+
if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE)
746
+
chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth);
763
747
764
748
/* Set peripheral address */
765
749
chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
···
776
758
/* Set device burst size */
777
759
src_best_burst = stm32_dma_get_best_burst(buf_len,
778
760
src_maxburst,
779
-
threshold,
761
+
fifoth,
780
762
src_addr_width);
781
763
chan->mem_burst = src_best_burst;
782
764
src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
···
784
766
return src_burst_size;
785
767
786
768
/* Set memory data size */
787
-
dst_addr_width = stm32_dma_get_max_width(buf_len, threshold);
769
+
dst_addr_width = stm32_dma_get_max_width(buf_len, fifoth);
788
770
chan->mem_width = dst_addr_width;
789
771
dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
790
772
if (dst_bus_width < 0)
···
794
776
dst_maxburst = STM32_DMA_MAX_BURST;
795
777
dst_best_burst = stm32_dma_get_best_burst(buf_len,
796
778
dst_maxburst,
797
-
threshold,
779
+
fifoth,
798
780
dst_addr_width);
799
781
chan->mem_burst = dst_best_burst;
800
782
dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
···
809
791
810
792
/* Set FIFO threshold */
811
793
chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
812
-
chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);
794
+
if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE)
795
+
chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth);
813
796
814
797
/* Set peripheral address */
815
798
chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;
···
1235
1216
chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
1236
1217
1237
1218
chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features);
1219
+
if (STM32_DMA_DIRECT_MODE_GET(cfg->features))
1220
+
chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE;
1238
1221
}
1239
1222
1240
1223
static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
+2
-2
drivers/dma/ti/Kconfig
+2
-2
drivers/dma/ti/Kconfig
···
36
36
37
37
config TI_K3_UDMA
38
38
bool "Texas Instruments UDMA support"
39
-
depends on ARCH_K3 || COMPILE_TEST
39
+
depends on ARCH_K3
40
40
depends on TI_SCI_PROTOCOL
41
41
depends on TI_SCI_INTA_IRQCHIP
42
42
select DMA_ENGINE
···
49
49
50
50
config TI_K3_UDMA_GLUE_LAYER
51
51
bool "Texas Instruments UDMA Glue layer for non DMAengine users"
52
-
depends on ARCH_K3 || COMPILE_TEST
52
+
depends on ARCH_K3
53
53
depends on TI_K3_UDMA
54
54
help
55
55
Say y here to support the K3 NAVSS DMA glue interface
+9
-25
drivers/dma/ti/k3-udma.c
+9
-25
drivers/dma/ti/k3-udma.c
···
231
231
struct udma_tx_drain tx_drain;
232
232
233
233
u32 bcnt; /* number of bytes completed since the start of the channel */
234
-
u32 in_ring_cnt; /* number of descriptors in flight */
235
234
236
235
/* Channel configuration parameters */
237
236
struct udma_chan_config config;
···
573
574
struct udma_desc *d = uc->desc;
574
575
struct k3_ring *ring = NULL;
575
576
dma_addr_t paddr;
576
-
int ret;
577
577
578
578
switch (uc->config.dir) {
579
579
case DMA_DEV_TO_MEM:
···
596
598
udma_sync_for_device(uc, idx);
597
599
}
598
600
599
-
ret = k3_ringacc_ring_push(ring, &paddr);
600
-
if (!ret)
601
-
uc->in_ring_cnt++;
602
-
603
-
return ret;
601
+
return k3_ringacc_ring_push(ring, &paddr);
604
602
}
605
603
606
604
static bool udma_desc_is_rx_flush(struct udma_chan *uc, dma_addr_t addr)
···
649
655
d->hwdesc[0].cppi5_desc_size,
650
656
DMA_FROM_DEVICE);
651
657
rmb(); /* Ensure that reads are not moved before this point */
652
-
653
-
if (!ret)
654
-
uc->in_ring_cnt--;
655
658
}
656
659
657
660
return ret;
···
688
697
udma_desc_free(&uc->terminated_desc->vd);
689
698
uc->terminated_desc = NULL;
690
699
}
691
-
692
-
uc->in_ring_cnt = 0;
693
700
}
694
701
695
702
static void udma_reset_counters(struct udma_chan *uc)
···
1062
1073
1063
1074
/* Teardown completion message */
1064
1075
if (cppi5_desc_is_tdcm(paddr)) {
1065
-
/* Compensate our internal pop/push counter */
1066
-
uc->in_ring_cnt++;
1067
-
1068
1076
complete_all(&uc->teardown_completed);
1069
1077
1070
1078
if (uc->terminated_desc) {
···
1277
1291
}
1278
1292
1279
1293
uc->tchan = __udma_reserve_tchan(ud, uc->config.channel_tpl, -1);
1280
-
if (IS_ERR(uc->tchan))
1281
-
return PTR_ERR(uc->tchan);
1282
1294
1283
-
return 0;
1295
+
return PTR_ERR_OR_ZERO(uc->tchan);
1284
1296
}
1285
1297
1286
1298
static int udma_get_rchan(struct udma_chan *uc)
···
1292
1308
}
1293
1309
1294
1310
uc->rchan = __udma_reserve_rchan(ud, uc->config.channel_tpl, -1);
1295
-
if (IS_ERR(uc->rchan))
1296
-
return PTR_ERR(uc->rchan);
1297
1311
1298
-
return 0;
1312
+
return PTR_ERR_OR_ZERO(uc->rchan);
1299
1313
}
1300
1314
1301
1315
static int udma_get_chan_pair(struct udma_chan *uc)
···
1355
1373
}
1356
1374
1357
1375
uc->rflow = __udma_get_rflow(ud, flow_id);
1358
-
if (IS_ERR(uc->rflow))
1359
-
return PTR_ERR(uc->rflow);
1360
1376
1361
-
return 0;
1377
+
return PTR_ERR_OR_ZERO(uc->rflow);
1362
1378
}
1363
1379
1364
1380
static void udma_put_rchan(struct udma_chan *uc)
···
1850
1870
udma_stop(uc);
1851
1871
if (udma_is_chan_running(uc)) {
1852
1872
dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
1873
+
ret = -EBUSY;
1853
1874
goto err_res_free;
1854
1875
}
1855
1876
}
···
3170
3189
3171
3190
static struct udma_match_data am654_mcu_data = {
3172
3191
.psil_base = 0x6000,
3173
-
.enable_memcpy_support = true, /* TEST: DMA domains */
3192
+
.enable_memcpy_support = false,
3174
3193
.statictr_z_mask = GENMASK(11, 0),
3175
3194
.rchan_oes_offset = 0x2000,
3176
3195
.tpl_levels = 2,
···
3451
3470
tr_req->addr = rx_flush->buffer_paddr;
3452
3471
tr_req->icnt0 = rx_flush->buffer_size;
3453
3472
tr_req->icnt1 = 1;
3473
+
3474
+
dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr,
3475
+
hwdesc->cppi5_desc_size, DMA_TO_DEVICE);
3454
3476
3455
3477
/* Set up descriptor to be used for packet mode */
3456
3478
hwdesc = &rx_flush->hwdescs[1];