tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

phy: sparx5-serdes: add indirection layer to register macros

The register macros are used to read and write to the SERDES registers.
The registers are largely the same on Sparx5 and lan969x, however some
register target sizes differ. Therefore we introduce a new indirection
to the register macros. The target sizes are looked up, using a mapping
table (sparx5_serdes_tsize) that maps the register target to the
register target size.

With this addition, we can reuse all the existing macros for lan969x.

Also the autogenerated macros are now formatted slightly different, to
adhere to a 80 character limit.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-6-d695bcb57b84@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Daniel Machon and committed by
Vinod Koul c8e4c8b7 f16df057

+507 -254
+14
drivers/phy/microchip/sparx5_serdes.c
··· 28 28 /* Optimal power settings from GUC */ 29 29 #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c 30 30 31 + /* Register target sizes */ 32 + const unsigned int sparx5_serdes_tsize[TSIZE_LAST] = { 33 + [TC_SD10G_LANE] = 12, 34 + [TC_SD_CMU] = 14, 35 + [TC_SD_CMU_CFG] = 14, 36 + [TC_SD_LANE] = 25, 37 + }; 38 + 39 + /* Pointer to the register target size table */ 40 + const unsigned int *tsize; 41 + 31 42 enum sparx5_sd25g28_mode_preset_type { 32 43 SPX5_SD25G28_MODE_PRESET_25000, 33 44 SPX5_SD25G28_MODE_PRESET_10000, ··· 2517 2506 static const struct sparx5_serdes_match_data sparx5_desc = { 2518 2507 .iomap = sparx5_serdes_iomap, 2519 2508 .iomap_size = ARRAY_SIZE(sparx5_serdes_iomap), 2509 + .tsize = sparx5_serdes_tsize, 2520 2510 .consts = { 2521 2511 .sd_max = 33, 2522 2512 .cmu_max = 14, ··· 2579 2567 priv->data = device_get_match_data(priv->dev); 2580 2568 if (!priv->data) 2581 2569 return -EINVAL; 2570 + 2571 + tsize = priv->data->tsize; 2582 2572 2583 2573 /* Get coreclock */ 2584 2574 clk = devm_clk_get(priv->dev, NULL);
+1
drivers/phy/microchip/sparx5_serdes.h
··· 60 60 const struct sparx5_serdes_ops ops; 61 61 const struct sparx5_serdes_io_resource *iomap; 62 62 int iomap_size; 63 + const unsigned int *tsize; 63 64 }; 64 65 65 66 struct sparx5_serdes_private {
+492 -254
drivers/phy/microchip/sparx5_serdes_regs.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0+ 2 2 * Microchip Sparx5 SerDes driver 3 3 * 4 - * Copyright (c) 2020 Microchip Technology Inc. 4 + * Copyright (c) 2024 Microchip Technology Inc. 5 5 */ 6 6 7 - /* This file is autogenerated by cml-utils 2020-11-16 13:11:27 +0100. 8 - * Commit ID: 13bdf073131d8bf40c54901df6988ae4e9c8f29f 7 + /* This file is autogenerated by cml-utils 2023-04-13 15:02:00 +0200. 8 + * Commit ID: 5ac560288d46048f872ecdb8add53717f1efc0e1 9 9 */ 10 10 11 11 #ifndef _SPARX5_SERDES_REGS_H_ ··· 26 26 NUM_TARGETS = 332 27 27 }; 28 28 29 + enum sparx5_serdes_tsize_enum { 30 + TC_SD10G_LANE, 31 + TC_SD_CMU, 32 + TC_SD_CMU_CFG, 33 + TC_SD_LANE, 34 + TSIZE_LAST, 35 + }; 36 + 37 + /* sparx5_serdes.c */ 38 + extern const unsigned int *tsize; 39 + 40 + #define TSIZE(o) tsize[o] 41 + 29 42 #define __REG(...) __VA_ARGS__ 30 43 31 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */ 32 - #define SD10G_LANE_LANE_01(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 4, 0, 1, 4) 44 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */ 45 + #define SD10G_LANE_LANE_01(t) \ 46 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 4, 0, \ 47 + 1, 4) 33 48 34 49 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0) 35 50 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ ··· 64 49 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\ 65 50 FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x) 66 51 67 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */ 68 - #define SD10G_LANE_LANE_02(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 8, 0, 1, 4) 52 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */ 53 + #define SD10G_LANE_LANE_02(t) \ 54 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 8, 0, \ 55 + 1, 4) 69 56 70 57 #define SD10G_LANE_LANE_02_CFG_EN_ADV BIT(0) 71 58 #define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\ ··· 99 82 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\ 100 83 FIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x) 101 84 102 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */ 103 - #define SD10G_LANE_LANE_03(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 12, 0, 1, 4) 85 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */ 86 + #define SD10G_LANE_LANE_03(t) \ 87 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 12, 0, \ 88 + 1, 4) 104 89 105 90 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN BIT(0) 106 91 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\ ··· 110 91 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\ 111 92 FIELD_GET(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x) 112 93 113 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */ 114 - #define SD10G_LANE_LANE_04(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 16, 0, 1, 4) 94 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */ 95 + #define SD10G_LANE_LANE_04(t) \ 96 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 16, 0, \ 97 + 1, 4) 115 98 116 99 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0 GENMASK(4, 0) 117 100 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\ ··· 121 100 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\ 122 101 FIELD_GET(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x) 123 102 124 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */ 125 - #define SD10G_LANE_LANE_06(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 24, 0, 1, 4) 103 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */ 104 + #define SD10G_LANE_LANE_06(t) \ 105 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 24, 0, \ 106 + 1, 4) 126 107 127 108 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER BIT(0) 128 109 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\ ··· 162 139 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\ 163 140 FIELD_GET(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x) 164 141 165 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */ 166 - #define SD10G_LANE_LANE_0B(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 44, 0, 1, 4) 142 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */ 143 + #define SD10G_LANE_LANE_0B(t) \ 144 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 44, 0, \ 145 + 1, 4) 167 146 168 147 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0 GENMASK(3, 0) 169 148 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\ ··· 197 172 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\ 198 173 FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x) 199 174 200 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */ 201 - #define SD10G_LANE_LANE_0C(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 48, 0, 1, 4) 175 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */ 176 + #define SD10G_LANE_LANE_0C(t) \ 177 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 48, 0, \ 178 + 1, 4) 202 179 203 180 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE BIT(0) 204 181 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\ ··· 250 223 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\ 251 224 FIELD_GET(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x) 252 225 253 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */ 254 - #define SD10G_LANE_LANE_0D(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 52, 0, 1, 4) 226 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */ 227 + #define SD10G_LANE_LANE_0D(t) \ 228 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 52, 0, \ 229 + 1, 4) 255 230 256 231 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0 GENMASK(1, 0) 257 232 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\ ··· 267 238 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\ 268 239 FIELD_GET(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x) 269 240 270 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */ 271 - #define SD10G_LANE_LANE_0E(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 56, 0, 1, 4) 241 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */ 242 + #define SD10G_LANE_LANE_0E(t) \ 243 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 56, 0, \ 244 + 1, 4) 272 245 273 246 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 GENMASK(3, 0) 274 247 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\ ··· 296 265 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\ 297 266 FIELD_GET(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x) 298 267 299 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */ 300 - #define SD10G_LANE_LANE_0F(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 60, 0, 1, 4) 268 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */ 269 + #define SD10G_LANE_LANE_0F(t) \ 270 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 60, 0, \ 271 + 1, 4) 301 272 302 273 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0 GENMASK(7, 0) 303 274 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\ ··· 307 274 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\ 308 275 FIELD_GET(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x) 309 276 310 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */ 311 - #define SD10G_LANE_LANE_13(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 76, 0, 1, 4) 277 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */ 278 + #define SD10G_LANE_LANE_13(t) \ 279 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 76, 0, \ 280 + 1, 4) 312 281 313 282 #define SD10G_LANE_LANE_13_CFG_DCDR_PD BIT(0) 314 283 #define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\ ··· 330 295 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\ 331 296 FIELD_GET(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x) 332 297 333 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */ 334 - #define SD10G_LANE_LANE_14(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 80, 0, 1, 4) 298 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */ 299 + #define SD10G_LANE_LANE_14(t) \ 300 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 80, 0, \ 301 + 1, 4) 335 302 336 303 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0 GENMASK(7, 0) 337 304 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\ ··· 341 304 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\ 342 305 FIELD_GET(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x) 343 306 344 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */ 345 - #define SD10G_LANE_LANE_15(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 84, 0, 1, 4) 307 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */ 308 + #define SD10G_LANE_LANE_15(t) \ 309 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 84, 0, \ 310 + 1, 4) 346 311 347 312 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8 GENMASK(7, 0) 348 313 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\ ··· 352 313 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\ 353 314 FIELD_GET(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x) 354 315 355 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */ 356 - #define SD10G_LANE_LANE_16(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 88, 0, 1, 4) 316 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */ 317 + #define SD10G_LANE_LANE_16(t) \ 318 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 88, 0, \ 319 + 1, 4) 357 320 358 321 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16 GENMASK(7, 0) 359 322 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\ ··· 363 322 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\ 364 323 FIELD_GET(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x) 365 324 366 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */ 367 - #define SD10G_LANE_LANE_1A(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 104, 0, 1, 4) 325 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */ 326 + #define SD10G_LANE_LANE_1A(t) \ 327 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 104, 0,\ 328 + 1, 4) 368 329 369 330 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN BIT(0) 370 331 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\ ··· 398 355 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\ 399 356 FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x) 400 357 401 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */ 402 - #define SD10G_LANE_LANE_22(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 136, 0, 1, 4) 358 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */ 359 + #define SD10G_LANE_LANE_22(t) \ 360 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 136, 0,\ 361 + 1, 4) 403 362 404 363 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1 GENMASK(4, 0) 405 364 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\ ··· 409 364 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\ 410 365 FIELD_GET(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x) 411 366 412 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */ 413 - #define SD10G_LANE_LANE_23(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 140, 0, 1, 4) 367 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */ 368 + #define SD10G_LANE_LANE_23(t) \ 369 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 140, 0,\ 370 + 1, 4) 414 371 415 372 #define SD10G_LANE_LANE_23_CFG_DFE_PD BIT(0) 416 373 #define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\ ··· 444 397 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\ 445 398 FIELD_GET(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x) 446 399 447 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */ 448 - #define SD10G_LANE_LANE_24(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 144, 0, 1, 4) 400 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */ 401 + #define SD10G_LANE_LANE_24(t) \ 402 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 144, 0,\ 403 + 1, 4) 449 404 450 405 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0 GENMASK(3, 0) 451 406 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\ ··· 461 412 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\ 462 413 FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x) 463 414 464 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */ 465 - #define SD10G_LANE_LANE_26(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 152, 0, 1, 4) 415 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */ 416 + #define SD10G_LANE_LANE_26(t) \ 417 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 152, 0,\ 418 + 1, 4) 466 419 467 420 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0 GENMASK(7, 0) 468 421 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\ ··· 472 421 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\ 473 422 FIELD_GET(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x) 474 423 475 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */ 476 - #define SD10G_LANE_LANE_2F(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 188, 0, 1, 4) 424 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */ 425 + #define SD10G_LANE_LANE_2F(t) \ 426 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 188, 0,\ 427 + 1, 4) 477 428 478 429 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0 GENMASK(2, 0) 479 430 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\ ··· 489 436 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\ 490 437 FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x) 491 438 492 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */ 493 - #define SD10G_LANE_LANE_30(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 192, 0, 1, 4) 439 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */ 440 + #define SD10G_LANE_LANE_30(t) \ 441 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 192, 0,\ 442 + 1, 4) 494 443 495 444 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN BIT(0) 496 445 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\ ··· 506 451 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\ 507 452 FIELD_GET(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x) 508 453 509 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */ 510 - #define SD10G_LANE_LANE_31(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 196, 0, 1, 4) 454 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */ 455 + #define SD10G_LANE_LANE_31(t) \ 456 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 196, 0,\ 457 + 1, 4) 511 458 512 459 #define SD10G_LANE_LANE_31_CFG_PI_RSTN BIT(0) 513 460 #define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\ ··· 547 490 #define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\ 548 491 FIELD_GET(SD10G_LANE_LANE_31_CFG_R50_EN, x) 549 492 550 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */ 551 - #define SD10G_LANE_LANE_32(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 200, 0, 1, 4) 493 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */ 494 + #define SD10G_LANE_LANE_32(t) \ 495 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 200, 0,\ 496 + 1, 4) 552 497 553 498 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0) 554 499 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\ ··· 564 505 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\ 565 506 FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x) 566 507 567 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */ 568 - #define SD10G_LANE_LANE_33(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 204, 0, 1, 4) 508 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */ 509 + #define SD10G_LANE_LANE_33(t) \ 510 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 204, 0,\ 511 + 1, 4) 569 512 570 513 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0) 571 514 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ ··· 581 520 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\ 582 521 FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x) 583 522 584 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */ 585 - #define SD10G_LANE_LANE_35(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 212, 0, 1, 4) 523 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */ 524 + #define SD10G_LANE_LANE_35(t) \ 525 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 212, 0,\ 526 + 1, 4) 586 527 587 528 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0 GENMASK(1, 0) 588 529 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\ ··· 598 535 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\ 599 536 FIELD_GET(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x) 600 537 601 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */ 602 - #define SD10G_LANE_LANE_36(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 216, 0, 1, 4) 538 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */ 539 + #define SD10G_LANE_LANE_36(t) \ 540 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 216, 0,\ 541 + 1, 4) 603 542 604 543 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0) 605 544 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\ ··· 633 568 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\ 634 569 FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x) 635 570 636 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */ 637 - #define SD10G_LANE_LANE_37(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 220, 0, 1, 4) 571 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */ 572 + #define SD10G_LANE_LANE_37(t) \ 573 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 220, 0,\ 574 + 1, 4) 638 575 639 576 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD BIT(0) 640 577 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\ ··· 662 595 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\ 663 596 FIELD_GET(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x) 664 597 665 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */ 666 - #define SD10G_LANE_LANE_39(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 228, 0, 1, 4) 598 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */ 599 + #define SD10G_LANE_LANE_39(t) \ 600 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 228, 0,\ 601 + 1, 4) 667 602 668 603 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0 GENMASK(2, 0) 669 604 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\ ··· 679 610 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\ 680 611 FIELD_GET(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x) 681 612 682 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */ 683 - #define SD10G_LANE_LANE_3A(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 232, 0, 1, 4) 613 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */ 614 + #define SD10G_LANE_LANE_3A(t) \ 615 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 232, 0,\ 616 + 1, 4) 684 617 685 618 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0 GENMASK(3, 0) 686 619 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\ ··· 696 625 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\ 697 626 FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x) 698 627 699 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */ 700 - #define SD10G_LANE_LANE_3C(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 240, 0, 1, 4) 628 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */ 629 + #define SD10G_LANE_LANE_3C(t) \ 630 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 240, 0,\ 631 + 1, 4) 701 632 702 633 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC BIT(0) 703 634 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\ ··· 713 640 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\ 714 641 FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x) 715 642 716 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */ 717 - #define SD10G_LANE_LANE_40(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 256, 0, 1, 4) 643 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */ 644 + #define SD10G_LANE_LANE_40(t) \ 645 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 256, 0,\ 646 + 1, 4) 718 647 719 648 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0 GENMASK(7, 0) 720 649 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\ ··· 724 649 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\ 725 650 FIELD_GET(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x) 726 651 727 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */ 728 - #define SD10G_LANE_LANE_41(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 260, 0, 1, 4) 652 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */ 653 + #define SD10G_LANE_LANE_41(t) \ 654 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 260, 0,\ 655 + 1, 4) 729 656 730 657 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8 GENMASK(7, 0) 731 658 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\ ··· 735 658 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\ 736 659 FIELD_GET(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x) 737 660 738 - /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */ 739 - #define SD10G_LANE_LANE_42(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 264, 0, 1, 4) 661 + /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */ 662 + #define SD10G_LANE_LANE_42(t) \ 663 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 264, 0,\ 664 + 1, 4) 740 665 741 666 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0 GENMASK(2, 0) 742 667 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\ ··· 752 673 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\ 753 674 FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x) 754 675 755 - /* SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */ 756 - #define SD10G_LANE_LANE_48(t) __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 0, 0, 1, 4) 676 + /* SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */ 677 + #define SD10G_LANE_LANE_48(t) \ 678 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 0, 0, \ 679 + 1, 4) 757 680 758 681 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0 GENMASK(3, 0) 759 682 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\ ··· 775 694 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\ 776 695 FIELD_GET(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x) 777 696 778 - /* SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */ 779 - #define SD10G_LANE_LANE_50(t) __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 32, 0, 1, 4) 697 + /* SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */ 698 + #define SD10G_LANE_LANE_50(t) \ 699 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 32, 0,\ 700 + 1, 4) 780 701 781 702 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0 GENMASK(1, 0) 782 703 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\ ··· 810 727 #define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\ 811 728 FIELD_GET(SD10G_LANE_LANE_50_CFG_JT_EN, x) 812 729 813 - /* SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */ 814 - #define SD10G_LANE_LANE_52(t) __REG(TARGET_SD10G_LANE, t, 12, 328, 0, 1, 24, 0, 0, 1, 4) 730 + /* SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */ 731 + #define SD10G_LANE_LANE_52(t) \ 732 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 328, 0, 1, 24, 0, 0, \ 733 + 1, 4) 815 734 816 735 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0 GENMASK(5, 0) 817 736 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\ ··· 821 736 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\ 822 737 FIELD_GET(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x) 823 738 824 - /* SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */ 825 - #define SD10G_LANE_LANE_83(t) __REG(TARGET_SD10G_LANE, t, 12, 464, 0, 1, 112, 60, 0, 1, 4) 739 + /* SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */ 740 + #define SD10G_LANE_LANE_83(t) \ 741 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 464, 0, 1, 112, 60, \ 742 + 0, 1, 4) 826 743 827 744 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE BIT(0) 828 745 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\ ··· 868 781 #define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\ 869 782 FIELD_GET(SD10G_LANE_LANE_83_R_CTLE_RSTN, x) 870 783 871 - /* SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */ 872 - #define SD10G_LANE_LANE_93(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 12, 0, 1, 4) 784 + /* SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */ 785 + #define SD10G_LANE_LANE_93(t) \ 786 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 12, 0,\ 787 + 1, 4) 873 788 874 789 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN BIT(0) 875 790 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\ ··· 921 832 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\ 922 833 FIELD_GET(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x) 923 834 924 - /* SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */ 925 - #define SD10G_LANE_LANE_94(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 16, 0, 1, 4) 835 + /* SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */ 836 + #define SD10G_LANE_LANE_94(t) \ 837 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 16, 0,\ 838 + 1, 4) 926 839 927 840 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0 GENMASK(2, 0) 928 841 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\ ··· 956 865 #define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\ 957 866 FIELD_GET(SD10G_LANE_LANE_94_R_SWING_REG, x) 958 867 959 - /* SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */ 960 - #define SD10G_LANE_LANE_9E(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 56, 0, 1, 4) 868 + /* SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */ 869 + #define SD10G_LANE_LANE_9E(t) \ 870 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 56, 0,\ 871 + 1, 4) 961 872 962 873 #define SD10G_LANE_LANE_9E_R_RXEQ_REG BIT(0) 963 874 #define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\ ··· 979 886 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\ 980 887 FIELD_GET(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x) 981 888 982 - /* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */ 983 - #define SD10G_LANE_LANE_A1(t) __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 4, 0, 1, 4) 889 + /* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */ 890 + #define SD10G_LANE_LANE_A1(t) \ 891 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 4, 0,\ 892 + 1, 4) 984 893 985 894 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0) 986 895 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\ ··· 1014 919 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\ 1015 920 FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING, x) 1016 921 1017 - /* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */ 1018 - #define SD10G_LANE_LANE_A2(t) __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 8, 0, 1, 4) 922 + /* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */ 923 + #define SD10G_LANE_LANE_A2(t) \ 924 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 8, 0,\ 925 + 1, 4) 1019 926 1020 927 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0) 1021 928 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\ ··· 1025 928 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\ 1026 929 FIELD_GET(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x) 1027 930 1028 - /* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ 1029 - #define SD10G_LANE_LANE_DF(t) __REG(TARGET_SD10G_LANE, t, 12, 832, 0, 1, 84, 60, 0, 1, 4) 931 + /* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ 932 + #define SD10G_LANE_LANE_DF(t) \ 933 + __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 832, 0, 1, 84, 60, 0,\ 934 + 1, 4) 1030 935 1031 936 #define SD10G_LANE_LANE_DF_LOL_UDL BIT(0) 1032 937 #define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\ ··· 1054 955 #define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\ 1055 956 FIELD_GET(SD10G_LANE_LANE_DF_SQUELCH, x) 1056 957 1057 - /* SD25G_TARGET:CMU_GRP_0:CMU_09 */ 1058 - #define SD25G_LANE_CMU_09(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4) 958 + /* SPARX5 ONLY */ 959 + /* SD25G_TARGET:CMU_GRP_0:CMU_09 */ 960 + #define SD25G_LANE_CMU_09(t) \ 961 + __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4) 1059 962 1060 963 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN BIT(0) 1061 964 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\ ··· 1089 988 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\ 1090 989 FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x) 1091 990 1092 - /* SD25G_TARGET:CMU_GRP_0:CMU_0B */ 1093 - #define SD25G_LANE_CMU_0B(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4) 991 + /* SPARX5 ONLY */ 992 + /* SD25G_TARGET:CMU_GRP_0:CMU_0B */ 993 + #define SD25G_LANE_CMU_0B(t) \ 994 + __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4) 1094 995 1095 996 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT BIT(0) 1096 997 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\ ··· 1142 1039 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\ 1143 1040 FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x) 1144 1041 1145 - /* SD25G_TARGET:CMU_GRP_0:CMU_0C */ 1146 - #define SD25G_LANE_CMU_0C(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4) 1042 + /* SPARX5 ONLY */ 1043 + /* SD25G_TARGET:CMU_GRP_0:CMU_0C */ 1044 + #define SD25G_LANE_CMU_0C(t) \ 1045 + __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4) 1147 1046 1148 1047 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET BIT(0) 1149 1048 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\ ··· 1177 1072 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\ 1178 1073 FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x) 1179 1074 1180 - /* SD25G_TARGET:CMU_GRP_0:CMU_0D */ 1181 - #define SD25G_LANE_CMU_0D(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4) 1075 + /* SPARX5 ONLY */ 1076 + /* SD25G_TARGET:CMU_GRP_0:CMU_0D */ 1077 + #define SD25G_LANE_CMU_0D(t) \ 1078 + __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4) 1182 1079 1183 1080 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD BIT(0) 1184 1081 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\ ··· 1212 1105 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\ 1213 1106 FIELD_GET(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x) 1214 1107 1215 - /* SD25G_TARGET:CMU_GRP_0:CMU_0E */ 1216 - #define SD25G_LANE_CMU_0E(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4) 1108 + /* SPARX5 ONLY */ 1109 + /* SD25G_TARGET:CMU_GRP_0:CMU_0E */ 1110 + #define SD25G_LANE_CMU_0E(t) \ 1111 + __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4) 1217 1112 1218 1113 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0 GENMASK(3, 0) 1219 1114 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\ ··· 1229 1120 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\ 1230 1121 FIELD_GET(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x) 1231 1122 1232 - /* SD25G_TARGET:CMU_GRP_0:CMU_13 */ 1233 - #define SD25G_LANE_CMU_13(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4) 1123 + /* SPARX5 ONLY */ 1124 + /* SD25G_TARGET:CMU_GRP_0:CMU_13 */ 1125 + #define SD25G_LANE_CMU_13(t) \ 1126 + __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4) 1234 1127 1235 1128 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0 GENMASK(3, 0) 1236 1129 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\ ··· 1246 1135 #define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\ 1247 1136 FIELD_GET(SD25G_LANE_CMU_13_CFG_JT_EN, x) 1248 1137 1249 - /* SD25G_TARGET:CMU_GRP_0:CMU_18 */ 1250 - #define SD25G_LANE_CMU_18(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4) 1138 + /* SPARX5 ONLY */ 1139 + /* SD25G_TARGET:CMU_GRP_0:CMU_18 */ 1140 + #define SD25G_LANE_CMU_18(t) \ 1141 + __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4) 1251 1142 1252 1143 #define SD25G_LANE_CMU_18_R_PLL_RSTN BIT(0) 1253 1144 #define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\ ··· 1275 1162 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\ 1276 1163 FIELD_GET(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x) 1277 1164 1278 - /* SD25G_TARGET:CMU_GRP_0:CMU_19 */ 1279 - #define SD25G_LANE_CMU_19(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4) 1165 + /* SPARX5 ONLY */ 1166 + /* SD25G_TARGET:CMU_GRP_0:CMU_19 */ 1167 + #define SD25G_LANE_CMU_19(t) \ 1168 + __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4) 1280 1169 1281 1170 #define SD25G_LANE_CMU_19_R_CK_RESETB BIT(0) 1282 1171 #define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\ ··· 1292 1177 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\ 1293 1178 FIELD_GET(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x) 1294 1179 1295 - /* SD25G_TARGET:CMU_GRP_0:CMU_1A */ 1296 - #define SD25G_LANE_CMU_1A(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4) 1180 + /* SPARX5 ONLY */ 1181 + /* SD25G_TARGET:CMU_GRP_0:CMU_1A */ 1182 + #define SD25G_LANE_CMU_1A(t) \ 1183 + __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4) 1297 1184 1298 1185 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0 GENMASK(2, 0) 1299 1186 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\ ··· 1321 1204 #define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\ 1322 1205 FIELD_GET(SD25G_LANE_CMU_1A_R_REG_MANUAL, x) 1323 1206 1324 - /* SD25G_TARGET:CMU_GRP_1:CMU_2A */ 1325 - #define SD25G_LANE_CMU_2A(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4) 1207 + /* SPARX5 ONLY */ 1208 + /* SD25G_TARGET:CMU_GRP_1:CMU_2A */ 1209 + #define SD25G_LANE_CMU_2A(t) \ 1210 + __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4) 1326 1211 1327 1212 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0 GENMASK(1, 0) 1328 1213 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\ ··· 1344 1225 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\ 1345 1226 FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x) 1346 1227 1347 - /* SD25G_TARGET:CMU_GRP_1:CMU_30 */ 1348 - #define SD25G_LANE_CMU_30(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4) 1228 + /* SPARX5 ONLY */ 1229 + /* SD25G_TARGET:CMU_GRP_1:CMU_30 */ 1230 + #define SD25G_LANE_CMU_30(t) \ 1231 + __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4) 1349 1232 1350 1233 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 GENMASK(2, 0) 1351 1234 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\ ··· 1361 1240 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\ 1362 1241 FIELD_GET(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x) 1363 1242 1364 - /* SD25G_TARGET:CMU_GRP_1:CMU_31 */ 1365 - #define SD25G_LANE_CMU_31(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4) 1243 + /* SPARX5 ONLY */ 1244 + /* SD25G_TARGET:CMU_GRP_1:CMU_31 */ 1245 + #define SD25G_LANE_CMU_31(t) \ 1246 + __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4) 1366 1247 1367 1248 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0 GENMASK(7, 0) 1368 1249 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\ ··· 1372 1249 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\ 1373 1250 FIELD_GET(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x) 1374 1251 1375 - /* SD25G_TARGET:CMU_GRP_2:CMU_40 */ 1376 - #define SD25G_LANE_CMU_40(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4) 1252 + /* SPARX5 ONLY */ 1253 + /* SD25G_TARGET:CMU_GRP_2:CMU_40 */ 1254 + #define SD25G_LANE_CMU_40(t) \ 1255 + __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4) 1377 1256 1378 1257 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL BIT(0) 1379 1258 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\ ··· 1413 1288 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\ 1414 1289 FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x) 1415 1290 1416 - /* SD25G_TARGET:CMU_GRP_2:CMU_45 */ 1417 - #define SD25G_LANE_CMU_45(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4) 1291 + /* SPARX5 ONLY */ 1292 + /* SD25G_TARGET:CMU_GRP_2:CMU_45 */ 1293 + #define SD25G_LANE_CMU_45(t) \ 1294 + __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4) 1418 1295 1419 1296 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0 GENMASK(7, 0) 1420 1297 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\ ··· 1424 1297 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\ 1425 1298 FIELD_GET(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x) 1426 1299 1427 - /* SD25G_TARGET:CMU_GRP_2:CMU_46 */ 1428 - #define SD25G_LANE_CMU_46(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4) 1300 + /* SPARX5 ONLY */ 1301 + /* SD25G_TARGET:CMU_GRP_2:CMU_46 */ 1302 + #define SD25G_LANE_CMU_46(t) \ 1303 + __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4) 1429 1304 1430 1305 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8 GENMASK(7, 0) 1431 1306 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\ ··· 1435 1306 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\ 1436 1307 FIELD_GET(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x) 1437 1308 1438 - /* SD25G_TARGET:CMU_GRP_3:CMU_C0 */ 1439 - #define SD25G_LANE_CMU_C0(t) __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4) 1309 + /* SPARX5 ONLY */ 1310 + /* SD25G_TARGET:CMU_GRP_3:CMU_C0 */ 1311 + #define SD25G_LANE_CMU_C0(t) \ 1312 + __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4) 1440 1313 1441 1314 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0 GENMASK(3, 0) 1442 1315 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\ ··· 1452 1321 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\ 1453 1322 FIELD_GET(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x) 1454 1323 1455 - /* SD25G_TARGET:CMU_GRP_4:CMU_FF */ 1456 - #define SD25G_LANE_CMU_FF(t) __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4) 1324 + /* SPARX5 ONLY */ 1325 + /* SD25G_TARGET:CMU_GRP_4:CMU_FF */ 1326 + #define SD25G_LANE_CMU_FF(t) \ 1327 + __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4) 1457 1328 1458 1329 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX GENMASK(7, 0) 1459 1330 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\ ··· 1463 1330 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\ 1464 1331 FIELD_GET(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x) 1465 1332 1466 - /* SD25G_TARGET:LANE_GRP_0:LANE_00 */ 1467 - #define SD25G_LANE_LANE_00(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4) 1333 + /* SPARX5 ONLY */ 1334 + /* SD25G_TARGET:LANE_GRP_0:LANE_00 */ 1335 + #define SD25G_LANE_LANE_00(t) \ 1336 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4) 1468 1337 1469 1338 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0 GENMASK(3, 0) 1470 1339 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\ ··· 1480 1345 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\ 1481 1346 FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x) 1482 1347 1483 - /* SD25G_TARGET:LANE_GRP_0:LANE_01 */ 1484 - #define SD25G_LANE_LANE_01(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4) 1348 + /* SPARX5 ONLY */ 1349 + /* SD25G_TARGET:LANE_GRP_0:LANE_01 */ 1350 + #define SD25G_LANE_LANE_01(t) \ 1351 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4) 1485 1352 1486 1353 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0) 1487 1354 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ ··· 1497 1360 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\ 1498 1361 FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x) 1499 1362 1500 - /* SD25G_TARGET:LANE_GRP_0:LANE_03 */ 1501 - #define SD25G_LANE_LANE_03(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4) 1363 + /* SPARX5 ONLY */ 1364 + /* SD25G_TARGET:LANE_GRP_0:LANE_03 */ 1365 + #define SD25G_LANE_LANE_03(t) \ 1366 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4) 1502 1367 1503 1368 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0 GENMASK(4, 0) 1504 1369 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\ ··· 1508 1369 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\ 1509 1370 FIELD_GET(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x) 1510 1371 1511 - /* SD25G_TARGET:LANE_GRP_0:LANE_04 */ 1512 - #define SD25G_LANE_LANE_04(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4) 1372 + /* SPARX5 ONLY */ 1373 + /* SD25G_TARGET:LANE_GRP_0:LANE_04 */ 1374 + #define SD25G_LANE_LANE_04(t) \ 1375 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4) 1513 1376 1514 1377 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN BIT(0) 1515 1378 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\ ··· 1549 1408 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\ 1550 1409 FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x) 1551 1410 1552 - /* SD25G_TARGET:LANE_GRP_0:LANE_05 */ 1553 - #define SD25G_LANE_LANE_05(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4) 1411 + /* SPARX5 ONLY */ 1412 + /* SD25G_TARGET:LANE_GRP_0:LANE_05 */ 1413 + #define SD25G_LANE_LANE_05(t) \ 1414 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4) 1554 1415 1555 1416 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0 GENMASK(3, 0) 1556 1417 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\ ··· 1566 1423 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\ 1567 1424 FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x) 1568 1425 1569 - /* SD25G_TARGET:LANE_GRP_0:LANE_06 */ 1570 - #define SD25G_LANE_LANE_06(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4) 1426 + /* SPARX5 ONLY */ 1427 + /* SD25G_TARGET:LANE_GRP_0:LANE_06 */ 1428 + #define SD25G_LANE_LANE_06(t) \ 1429 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4) 1571 1430 1572 1431 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN BIT(0) 1573 1432 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\ ··· 1583 1438 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\ 1584 1439 FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x) 1585 1440 1586 - /* SD25G_TARGET:LANE_GRP_0:LANE_07 */ 1587 - #define SD25G_LANE_LANE_07(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4) 1441 + /* SPARX5 ONLY */ 1442 + /* SD25G_TARGET:LANE_GRP_0:LANE_07 */ 1443 + #define SD25G_LANE_LANE_07(t) \ 1444 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4) 1588 1445 1589 1446 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV BIT(0) 1590 1447 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\ ··· 1606 1459 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\ 1607 1460 FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x) 1608 1461 1609 - /* SD25G_TARGET:LANE_GRP_0:LANE_09 */ 1610 - #define SD25G_LANE_LANE_09(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4) 1462 + /* SPARX5 ONLY */ 1463 + /* SD25G_TARGET:LANE_GRP_0:LANE_09 */ 1464 + #define SD25G_LANE_LANE_09(t) \ 1465 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4) 1611 1466 1612 1467 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0 GENMASK(3, 0) 1613 1468 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\ ··· 1617 1468 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\ 1618 1469 FIELD_GET(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x) 1619 1470 1620 - /* SD25G_TARGET:LANE_GRP_0:LANE_0A */ 1621 - #define SD25G_LANE_LANE_0A(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4) 1471 + /* SPARX5 ONLY */ 1472 + /* SD25G_TARGET:LANE_GRP_0:LANE_0A */ 1473 + #define SD25G_LANE_LANE_0A(t) \ 1474 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4) 1622 1475 1623 1476 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0 GENMASK(5, 0) 1624 1477 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\ ··· 1628 1477 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\ 1629 1478 FIELD_GET(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x) 1630 1479 1631 - /* SD25G_TARGET:LANE_GRP_0:LANE_0B */ 1632 - #define SD25G_LANE_LANE_0B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4) 1480 + /* SPARX5 ONLY */ 1481 + /* SD25G_TARGET:LANE_GRP_0:LANE_0B */ 1482 + #define SD25G_LANE_LANE_0B(t) \ 1483 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4) 1633 1484 1634 1485 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN BIT(0) 1635 1486 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\ ··· 1651 1498 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\ 1652 1499 FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x) 1653 1500 1654 - /* SD25G_TARGET:LANE_GRP_0:LANE_0C */ 1655 - #define SD25G_LANE_LANE_0C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4) 1501 + /* SPARX5 ONLY */ 1502 + /* SD25G_TARGET:LANE_GRP_0:LANE_0C */ 1503 + #define SD25G_LANE_LANE_0C(t) \ 1504 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4) 1656 1505 1657 1506 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0) 1658 1507 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ ··· 1674 1519 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\ 1675 1520 FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x) 1676 1521 1677 - /* SD25G_TARGET:LANE_GRP_0:LANE_0D */ 1678 - #define SD25G_LANE_LANE_0D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4) 1522 + /* SPARX5 ONLY */ 1523 + /* SD25G_TARGET:LANE_GRP_0:LANE_0D */ 1524 + #define SD25G_LANE_LANE_0D(t) \ 1525 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4) 1679 1526 1680 1527 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0 GENMASK(2, 0) 1681 1528 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\ ··· 1709 1552 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\ 1710 1553 FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x) 1711 1554 1712 - /* SD25G_TARGET:LANE_GRP_0:LANE_0E */ 1713 - #define SD25G_LANE_LANE_0E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4) 1555 + /* SPARX5 ONLY */ 1556 + /* SD25G_TARGET:LANE_GRP_0:LANE_0E */ 1557 + #define SD25G_LANE_LANE_0E(t) \ 1558 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4) 1714 1559 1715 1560 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN BIT(0) 1716 1561 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\ ··· 1738 1579 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\ 1739 1580 FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x) 1740 1581 1741 - /* SD25G_TARGET:LANE_GRP_0:LANE_0F */ 1742 - #define SD25G_LANE_LANE_0F(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4) 1582 + /* SPARX5 ONLY */ 1583 + /* SD25G_TARGET:LANE_GRP_0:LANE_0F */ 1584 + #define SD25G_LANE_LANE_0F(t) \ 1585 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4) 1743 1586 1744 1587 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1 GENMASK(4, 0) 1745 1588 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\ ··· 1749 1588 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\ 1750 1589 FIELD_GET(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x) 1751 1590 1752 - /* SD25G_TARGET:LANE_GRP_0:LANE_18 */ 1753 - #define SD25G_LANE_LANE_18(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4) 1591 + /* SPARX5 ONLY */ 1592 + /* SD25G_TARGET:LANE_GRP_0:LANE_18 */ 1593 + #define SD25G_LANE_LANE_18(t) \ 1594 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4) 1754 1595 1755 1596 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN BIT(0) 1756 1597 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\ ··· 1784 1621 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\ 1785 1622 FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x) 1786 1623 1787 - /* SD25G_TARGET:LANE_GRP_0:LANE_19 */ 1788 - #define SD25G_LANE_LANE_19(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4) 1624 + /* SPARX5 ONLY */ 1625 + /* SD25G_TARGET:LANE_GRP_0:LANE_19 */ 1626 + #define SD25G_LANE_LANE_19(t) \ 1627 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4) 1789 1628 1790 1629 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD BIT(0) 1791 1630 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\ ··· 1837 1672 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\ 1838 1673 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x) 1839 1674 1840 - /* SD25G_TARGET:LANE_GRP_0:LANE_1A */ 1841 - #define SD25G_LANE_LANE_1A(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4) 1675 + /* SPARX5 ONLY */ 1676 + /* SD25G_TARGET:LANE_GRP_0:LANE_1A */ 1677 + #define SD25G_LANE_LANE_1A(t) \ 1678 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4) 1842 1679 1843 1680 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN BIT(0) 1844 1681 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\ ··· 1854 1687 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\ 1855 1688 FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x) 1856 1689 1857 - /* SD25G_TARGET:LANE_GRP_0:LANE_1B */ 1858 - #define SD25G_LANE_LANE_1B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4) 1690 + /* SPARX5 ONLY */ 1691 + /* SD25G_TARGET:LANE_GRP_0:LANE_1B */ 1692 + #define SD25G_LANE_LANE_1B(t) \ 1693 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4) 1859 1694 1860 1695 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0 GENMASK(7, 0) 1861 1696 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\ ··· 1865 1696 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\ 1866 1697 FIELD_GET(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x) 1867 1698 1868 - /* SD25G_TARGET:LANE_GRP_0:LANE_1C */ 1869 - #define SD25G_LANE_LANE_1C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4) 1699 + /* SPARX5 ONLY */ 1700 + /* SD25G_TARGET:LANE_GRP_0:LANE_1C */ 1701 + #define SD25G_LANE_LANE_1C(t) \ 1702 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4) 1870 1703 1871 1704 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN BIT(0) 1872 1705 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\ ··· 1894 1723 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\ 1895 1724 FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x) 1896 1725 1897 - /* SD25G_TARGET:LANE_GRP_0:LANE_1D */ 1898 - #define SD25G_LANE_LANE_1D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4) 1726 + /* SPARX5 ONLY */ 1727 + /* SD25G_TARGET:LANE_GRP_0:LANE_1D */ 1728 + #define SD25G_LANE_LANE_1D(t) \ 1729 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4) 1899 1730 1900 1731 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR BIT(0) 1901 1732 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\ ··· 1947 1774 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\ 1948 1775 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x) 1949 1776 1950 - /* SD25G_TARGET:LANE_GRP_0:LANE_1E */ 1951 - #define SD25G_LANE_LANE_1E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4) 1777 + /* SPARX5 ONLY */ 1778 + /* SD25G_TARGET:LANE_GRP_0:LANE_1E */ 1779 + #define SD25G_LANE_LANE_1E(t) \ 1780 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4) 1952 1781 1953 1782 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0 GENMASK(1, 0) 1954 1783 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\ ··· 1982 1807 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\ 1983 1808 FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x) 1984 1809 1985 - /* SD25G_TARGET:LANE_GRP_0:LANE_21 */ 1986 - #define SD25G_LANE_LANE_21(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4) 1810 + /* SPARX5 ONLY */ 1811 + /* SD25G_TARGET:LANE_GRP_0:LANE_21 */ 1812 + #define SD25G_LANE_LANE_21(t) \ 1813 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4) 1987 1814 1988 1815 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0 GENMASK(4, 0) 1989 1816 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\ ··· 1993 1816 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\ 1994 1817 FIELD_GET(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x) 1995 1818 1996 - /* SD25G_TARGET:LANE_GRP_0:LANE_22 */ 1997 - #define SD25G_LANE_LANE_22(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4) 1819 + /* SPARX5 ONLY */ 1820 + /* SD25G_TARGET:LANE_GRP_0:LANE_22 */ 1821 + #define SD25G_LANE_LANE_22(t) \ 1822 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4) 1998 1823 1999 1824 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0 GENMASK(3, 0) 2000 1825 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\ ··· 2004 1825 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\ 2005 1826 FIELD_GET(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x) 2006 1827 2007 - /* SD25G_TARGET:LANE_GRP_0:LANE_25 */ 2008 - #define SD25G_LANE_LANE_25(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4) 1828 + /* SPARX5 ONLY */ 1829 + /* SD25G_TARGET:LANE_GRP_0:LANE_25 */ 1830 + #define SD25G_LANE_LANE_25(t) \ 1831 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4) 2009 1832 2010 1833 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0 GENMASK(6, 0) 2011 1834 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\ ··· 2015 1834 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\ 2016 1835 FIELD_GET(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x) 2017 1836 2018 - /* SD25G_TARGET:LANE_GRP_0:LANE_26 */ 2019 - #define SD25G_LANE_LANE_26(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4) 1837 + /* SPARX5 ONLY */ 1838 + /* SD25G_TARGET:LANE_GRP_0:LANE_26 */ 1839 + #define SD25G_LANE_LANE_26(t) \ 1840 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4) 2020 1841 2021 1842 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0 GENMASK(6, 0) 2022 1843 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\ ··· 2026 1843 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\ 2027 1844 FIELD_GET(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x) 2028 1845 2029 - /* SD25G_TARGET:LANE_GRP_0:LANE_28 */ 2030 - #define SD25G_LANE_LANE_28(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4) 1846 + /* SPARX5 ONLY */ 1847 + /* SD25G_TARGET:LANE_GRP_0:LANE_28 */ 1848 + #define SD25G_LANE_LANE_28(t) \ 1849 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4) 2031 1850 2032 1851 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN BIT(0) 2033 1852 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\ ··· 2055 1870 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\ 2056 1871 FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x) 2057 1872 2058 - /* SD25G_TARGET:LANE_GRP_0:LANE_2B */ 2059 - #define SD25G_LANE_LANE_2B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4) 1873 + /* SPARX5 ONLY */ 1874 + /* SD25G_TARGET:LANE_GRP_0:LANE_2B */ 1875 + #define SD25G_LANE_LANE_2B(t) \ 1876 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4) 2060 1877 2061 1878 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0 GENMASK(3, 0) 2062 1879 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\ ··· 2078 1891 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\ 2079 1892 FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x) 2080 1893 2081 - /* SD25G_TARGET:LANE_GRP_0:LANE_2C */ 2082 - #define SD25G_LANE_LANE_2C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4) 1894 + /* SPARX5 ONLY */ 1895 + /* SD25G_TARGET:LANE_GRP_0:LANE_2C */ 1896 + #define SD25G_LANE_LANE_2C(t) \ 1897 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4) 2083 1898 2084 1899 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0 GENMASK(2, 0) 2085 1900 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\ ··· 2095 1906 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\ 2096 1907 FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x) 2097 1908 2098 - /* SD25G_TARGET:LANE_GRP_0:LANE_2D */ 2099 - #define SD25G_LANE_LANE_2D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4) 1909 + /* SPARX5 ONLY */ 1910 + /* SD25G_TARGET:LANE_GRP_0:LANE_2D */ 1911 + #define SD25G_LANE_LANE_2D(t) \ 1912 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4) 2100 1913 2101 1914 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0 GENMASK(2, 0) 2102 1915 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\ ··· 2112 1921 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\ 2113 1922 FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x) 2114 1923 2115 - /* SD25G_TARGET:LANE_GRP_0:LANE_2E */ 2116 - #define SD25G_LANE_LANE_2E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4) 1924 + /* SPARX5 ONLY */ 1925 + /* SD25G_TARGET:LANE_GRP_0:LANE_2E */ 1926 + #define SD25G_LANE_LANE_2E(t) \ 1927 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4) 2117 1928 2118 1929 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN BIT(0) 2119 1930 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\ ··· 2165 1972 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\ 2166 1973 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x) 2167 1974 2168 - /* SD25G_TARGET:LANE_GRP_0:LANE_40 */ 2169 - #define SD25G_LANE_LANE_40(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4) 1975 + /* SPARX5 ONLY */ 1976 + /* SD25G_TARGET:LANE_GRP_0:LANE_40 */ 1977 + #define SD25G_LANE_LANE_40(t) \ 1978 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4) 2170 1979 2171 1980 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE BIT(0) 2172 1981 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\ ··· 2212 2017 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\ 2213 2018 FIELD_GET(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x) 2214 2019 2215 - /* SD25G_TARGET:LANE_GRP_0:LANE_42 */ 2216 - #define SD25G_LANE_LANE_42(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4) 2020 + /* SPARX5 ONLY */ 2021 + /* SD25G_TARGET:LANE_GRP_0:LANE_42 */ 2022 + #define SD25G_LANE_LANE_42(t) \ 2023 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4) 2217 2024 2218 2025 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0 GENMASK(7, 0) 2219 2026 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\ ··· 2223 2026 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\ 2224 2027 FIELD_GET(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x) 2225 2028 2226 - /* SD25G_TARGET:LANE_GRP_0:LANE_43 */ 2227 - #define SD25G_LANE_LANE_43(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4) 2029 + /* SPARX5 ONLY */ 2030 + /* SD25G_TARGET:LANE_GRP_0:LANE_43 */ 2031 + #define SD25G_LANE_LANE_43(t) \ 2032 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4) 2228 2033 2229 2034 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8 GENMASK(7, 0) 2230 2035 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\ ··· 2234 2035 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\ 2235 2036 FIELD_GET(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x) 2236 2037 2237 - /* SD25G_TARGET:LANE_GRP_0:LANE_44 */ 2238 - #define SD25G_LANE_LANE_44(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4) 2038 + /* SPARX5 ONLY */ 2039 + /* SD25G_TARGET:LANE_GRP_0:LANE_44 */ 2040 + #define SD25G_LANE_LANE_44(t) \ 2041 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4) 2239 2042 2240 2043 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0 GENMASK(7, 0) 2241 2044 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\ ··· 2245 2044 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\ 2246 2045 FIELD_GET(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x) 2247 2046 2248 - /* SD25G_TARGET:LANE_GRP_0:LANE_45 */ 2249 - #define SD25G_LANE_LANE_45(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4) 2047 + /* SPARX5 ONLY */ 2048 + /* SD25G_TARGET:LANE_GRP_0:LANE_45 */ 2049 + #define SD25G_LANE_LANE_45(t) \ 2050 + __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4) 2250 2051 2251 2052 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8 GENMASK(7, 0) 2252 2053 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\ ··· 2256 2053 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\ 2257 2054 FIELD_GET(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x) 2258 2055 2259 - /* SD25G_TARGET:LANE_GRP_1:LANE_DE */ 2260 - #define SD25G_LANE_LANE_DE(t) __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4) 2056 + /* SPARX5 ONLY */ 2057 + /* SD25G_TARGET:LANE_GRP_1:LANE_DE */ 2058 + #define SD25G_LANE_LANE_DE(t) \ 2059 + __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4) 2261 2060 2262 2061 #define SD25G_LANE_LANE_DE_LN_LOL_UDL BIT(0) 2263 2062 #define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\ ··· 2285 2080 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\ 2286 2081 FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x) 2287 2082 2288 - /* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ 2289 - #define SD6G_LANE_LANE_DF(t) __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4) 2083 + /* SPARX5 ONLY */ 2084 + /* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ 2085 + #define SD6G_LANE_LANE_DF(t) \ 2086 + __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4) 2290 2087 2291 2088 #define SD6G_LANE_LANE_DF_LOL_UDL BIT(0) 2292 2089 #define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\ ··· 2314 2107 #define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\ 2315 2108 FIELD_GET(SD6G_LANE_LANE_DF_SQUELCH, x) 2316 2109 2317 - /* SD10G_CMU_TARGET:CMU_GRP_0:CMU_00 */ 2318 - #define SD_CMU_CMU_00(t) __REG(TARGET_SD_CMU, t, 14, 0, 0, 1, 20, 0, 0, 1, 4) 2110 + /* SD10G_CMU_TARGET:CMU_GRP_0:CMU_00 */ 2111 + #define SD_CMU_CMU_00(t) \ 2112 + __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 0, 0, 1, 20, 0, 0, 1, 4) 2319 2113 2320 2114 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE BIT(0) 2321 2115 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\ ··· 2342 2134 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\ 2343 2135 FIELD_GET(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x) 2344 2136 2345 - /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_05 */ 2346 - #define SD_CMU_CMU_05(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 0, 0, 1, 4) 2137 + /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_05 */ 2138 + #define SD_CMU_CMU_05(t) \ 2139 + __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 0, 0, 1, 4) 2347 2140 2348 2141 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN BIT(0) 2349 2142 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\ ··· 2358 2149 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\ 2359 2150 FIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x) 2360 2151 2361 - /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_06 */ 2362 - #define SD_CMU_CMU_06(t) \ 2363 - __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 4, 0, 1, 4) 2152 + /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_06 */ 2153 + #define SD_CMU_CMU_06(t) \ 2154 + __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 4, 0, 1, 4) 2364 2155 2365 2156 #define SD_CMU_CMU_06_CFG_DISLOS BIT(0) 2366 2157 #define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\ ··· 2410 2201 #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\ 2411 2202 FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x) 2412 2203 2413 - /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_08 */ 2414 - #define SD_CMU_CMU_08(t) \ 2415 - __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 12, 0, 1, 4) 2204 + /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_08 */ 2205 + #define SD_CMU_CMU_08(t) \ 2206 + __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 12, 0, 1, 4) 2416 2207 2417 2208 #define SD_CMU_CMU_08_CFG_VFILT2PAD BIT(0) 2418 2209 #define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\ ··· 2444 2235 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\ 2445 2236 FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x) 2446 2237 2447 - /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */ 2448 - #define SD_CMU_CMU_09(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 16, 0, 1, 4) 2238 + /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */ 2239 + #define SD_CMU_CMU_09(t) \ 2240 + __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 16, 0, 1, 4) 2449 2241 2450 2242 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP BIT(0) 2451 2243 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\ ··· 2472 2262 #define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\ 2473 2263 FIELD_GET(SD_CMU_CMU_09_CFG_SW_10G, x) 2474 2264 2475 - /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_0D */ 2476 - #define SD_CMU_CMU_0D(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 32, 0, 1, 4) 2265 + /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_0D */ 2266 + #define SD_CMU_CMU_0D(t) \ 2267 + __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 32, 0, 1, 4) 2477 2268 2478 2269 #define SD_CMU_CMU_0D_CFG_PD_DIV64 BIT(0) 2479 2270 #define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\ ··· 2506 2295 #define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\ 2507 2296 FIELD_GET(SD_CMU_CMU_0D_CFG_REFCK_PD, x) 2508 2297 2509 - /* SD10G_CMU_TARGET:CMU_GRP_3:CMU_1B */ 2510 - #define SD_CMU_CMU_1B(t) __REG(TARGET_SD_CMU, t, 14, 104, 0, 1, 20, 4, 0, 1, 4) 2298 + /* SD10G_CMU_TARGET:CMU_GRP_3:CMU_1B */ 2299 + #define SD_CMU_CMU_1B(t) \ 2300 + __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 104, 0, 1, 20, 4, 0, 1, 4) 2511 2301 2512 2302 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0 GENMASK(7, 0) 2513 2303 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\ ··· 2516 2304 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\ 2517 2305 FIELD_GET(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x) 2518 2306 2519 - /* SD10G_CMU_TARGET:CMU_GRP_4:CMU_1F */ 2520 - #define SD_CMU_CMU_1F(t) __REG(TARGET_SD_CMU, t, 14, 124, 0, 1, 68, 0, 0, 1, 4) 2307 + /* SD10G_CMU_TARGET:CMU_GRP_4:CMU_1F */ 2308 + #define SD_CMU_CMU_1F(t) \ 2309 + __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 124, 0, 1, 68, 0, 0, 1, 4) 2521 2310 2522 2311 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN BIT(0) 2523 2312 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\ ··· 2544 2331 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\ 2545 2332 FIELD_GET(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x) 2546 2333 2547 - /* SD10G_CMU_TARGET:CMU_GRP_5:CMU_30 */ 2548 - #define SD_CMU_CMU_30(t) __REG(TARGET_SD_CMU, t, 14, 192, 0, 1, 72, 0, 0, 1, 4) 2334 + /* SD10G_CMU_TARGET:CMU_GRP_5:CMU_30 */ 2335 + #define SD_CMU_CMU_30(t) \ 2336 + __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 192, 0, 1, 72, 0, 0, 1, 4) 2549 2337 2550 2338 #define SD_CMU_CMU_30_R_PLL_DLOL_EN BIT(0) 2551 2339 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\ ··· 2554 2340 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\ 2555 2341 FIELD_GET(SD_CMU_CMU_30_R_PLL_DLOL_EN, x) 2556 2342 2557 - /* SD10G_CMU_TARGET:CMU_GRP_6:CMU_44 */ 2558 - #define SD_CMU_CMU_44(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 8, 0, 1, 4) 2343 + /* SD10G_CMU_TARGET:CMU_GRP_6:CMU_44 */ 2344 + #define SD_CMU_CMU_44(t) \ 2345 + __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 8, 0, 1, 4) 2559 2346 2560 2347 #define SD_CMU_CMU_44_R_PLL_RSTN BIT(0) 2561 2348 #define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\ ··· 2570 2355 #define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\ 2571 2356 FIELD_GET(SD_CMU_CMU_44_R_CK_RESETB, x) 2572 2357 2573 - /* SD10G_CMU_TARGET:CMU_GRP_6:CMU_45 */ 2574 - #define SD_CMU_CMU_45(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 12, 0, 1, 4) 2358 + /* SD10G_CMU_TARGET:CMU_GRP_6:CMU_45 */ 2359 + #define SD_CMU_CMU_45(t) \ 2360 + __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 12, 0, 1, 4) 2575 2361 2576 2362 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL BIT(0) 2577 2363 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\ ··· 2622 2406 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\ 2623 2407 FIELD_GET(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x) 2624 2408 2625 - /* SD10G_CMU_TARGET:CMU_GRP_6:CMU_47 */ 2626 - #define SD_CMU_CMU_47(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 20, 0, 1, 4) 2409 + /* SD10G_CMU_TARGET:CMU_GRP_6:CMU_47 */ 2410 + #define SD_CMU_CMU_47(t) \ 2411 + __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 20, 0, 1, 4) 2627 2412 2628 2413 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0) 2629 2414 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\ ··· 2632 2415 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\ 2633 2416 FIELD_GET(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x) 2634 2417 2635 - /* SD10G_CMU_TARGET:CMU_GRP_7:CMU_E0 */ 2636 - #define SD_CMU_CMU_E0(t) __REG(TARGET_SD_CMU, t, 14, 896, 0, 1, 8, 0, 0, 1, 4) 2418 + /* SD10G_CMU_TARGET:CMU_GRP_7:CMU_E0 */ 2419 + #define SD_CMU_CMU_E0(t) \ 2420 + __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 896, 0, 1, 8, 0, 0, 1, 4) 2637 2421 2638 2422 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0 GENMASK(3, 0) 2639 2423 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\ ··· 2648 2430 #define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\ 2649 2431 FIELD_GET(SD_CMU_CMU_E0_PLL_LOL_UDL, x) 2650 2432 2651 - /* SD_CMU_TARGET:SD_CMU_CFG:SD_CMU_CFG */ 2652 - #define SD_CMU_CFG_SD_CMU_CFG(t) __REG(TARGET_SD_CMU_CFG, t, 14, 0, 0, 1, 8, 0, 0, 1, 4) 2433 + /* SD_CMU_TARGET:SD_CMU_CFG:SD_CMU_CFG */ 2434 + #define SD_CMU_CFG_SD_CMU_CFG(t) \ 2435 + __REG(TARGET_SD_CMU_CFG, t, TSIZE(TC_SD_CMU_CFG), 0, 0, 1, 8, 0, 0, 1, \ 2436 + 4) 2653 2437 2654 2438 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST BIT(0) 2655 2439 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\ ··· 2665 2445 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\ 2666 2446 FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x) 2667 2447 2668 - /* SD_LANE_TARGET:SD_RESET:SD_SER_RST */ 2669 - #define SD_LANE_SD_SER_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 0, 0, 1, 4) 2448 + /* SD_LANE_TARGET:SD_RESET:SD_SER_RST */ 2449 + #define SD_LANE_SD_SER_RST(t) \ 2450 + __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 0, 0, 1, 4) 2670 2451 2671 2452 #define SD_LANE_SD_SER_RST_SER_RST BIT(0) 2672 2453 #define SD_LANE_SD_SER_RST_SER_RST_SET(x)\ ··· 2675 2454 #define SD_LANE_SD_SER_RST_SER_RST_GET(x)\ 2676 2455 FIELD_GET(SD_LANE_SD_SER_RST_SER_RST, x) 2677 2456 2678 - /* SD_LANE_TARGET:SD_RESET:SD_DES_RST */ 2679 - #define SD_LANE_SD_DES_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 4, 0, 1, 4) 2457 + /* SD_LANE_TARGET:SD_RESET:SD_DES_RST */ 2458 + #define SD_LANE_SD_DES_RST(t) \ 2459 + __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 4, 0, 1, 4) 2680 2460 2681 2461 #define SD_LANE_SD_DES_RST_DES_RST BIT(0) 2682 2462 #define SD_LANE_SD_DES_RST_DES_RST_SET(x)\ ··· 2685 2463 #define SD_LANE_SD_DES_RST_DES_RST_GET(x)\ 2686 2464 FIELD_GET(SD_LANE_SD_DES_RST_DES_RST, x) 2687 2465 2688 - /* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ 2689 - #define SD_LANE_SD_LANE_CFG(t) __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 0, 0, 1, 4) 2466 + /* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ 2467 + #define SD_LANE_SD_LANE_CFG(t) \ 2468 + __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 0, 0, 1, 4) 2690 2469 2691 2470 #define SD_LANE_SD_LANE_CFG_MACRO_RST BIT(0) 2692 2471 #define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\ ··· 2731 2508 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\ 2732 2509 FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x) 2733 2510 2734 - /* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ 2735 - #define SD_LANE_SD_LANE_STAT(t) __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 4, 0, 1, 4) 2511 + /* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ 2512 + #define SD_LANE_SD_LANE_STAT(t) \ 2513 + __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 4, 0, 1, 4) 2736 2514 2737 2515 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE BIT(0) 2738 2516 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ ··· 2753 2529 #define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\ 2754 2530 FIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x) 2755 2531 2756 - /* SD_LANE_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ 2757 - #define SD_LANE_QUIET_MODE_6G(t) \ 2758 - __REG(TARGET_SD_LANE, t, 25, 24, 0, 1, 8, 4, 0, 1, 4) 2532 + /* SD_LANE_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ 2533 + #define SD_LANE_QUIET_MODE_6G(t) \ 2534 + __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 24, 0, 1, 8, 4, 0, 1, 4) 2759 2535 2760 2536 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0) 2761 2537 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\ ··· 2763 2539 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\ 2764 2540 FIELD_GET(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x) 2765 2541 2766 - /* SD_LANE_TARGET:CFG_STAT_FX100:MISC */ 2767 - #define SD_LANE_MISC(t) __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 0, 0, 1, 4) 2542 + /* SD_LANE_TARGET:CFG_STAT_FX100:MISC */ 2543 + #define SD_LANE_MISC(t) \ 2544 + __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 0, 0, 1, 4) 2768 2545 2769 2546 #define SD_LANE_MISC_SD_125_RST_DIS BIT(0) 2770 2547 #define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\ ··· 2785 2560 #define SD_LANE_MISC_MUX_ENA_GET(x)\ 2786 2561 FIELD_GET(SD_LANE_MISC_MUX_ENA, x) 2787 2562 2563 + /* SPARX5 ONLY */ 2788 2564 #define SD_LANE_MISC_CORE_CLK_FREQ GENMASK(5, 4) 2789 2565 #define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\ 2790 2566 FIELD_PREP(SD_LANE_MISC_CORE_CLK_FREQ, x) 2791 2567 #define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\ 2792 2568 FIELD_GET(SD_LANE_MISC_CORE_CLK_FREQ, x) 2793 2569 2794 - /* SD_LANE_TARGET:CFG_STAT_FX100:M_STAT_MISC */ 2795 - #define SD_LANE_M_STAT_MISC(t) __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 36, 0, 1, 4) 2570 + /* SD_LANE_TARGET:CFG_STAT_FX100:M_STAT_MISC */ 2571 + #define SD_LANE_M_STAT_MISC(t) \ 2572 + __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 36, 0, 1, 4) 2796 2573 2797 2574 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM GENMASK(21, 0) 2798 2575 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\ ··· 2808 2581 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\ 2809 2582 FIELD_GET(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x) 2810 2583 2811 - /* SD25G_CFG_TARGET:SD_RESET:SD_SER_RST */ 2812 - #define SD_LANE_25G_SD_SER_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4) 2584 + /* SPARX5 ONLY */ 2585 + /* SD25G_CFG_TARGET:SD_RESET:SD_SER_RST */ 2586 + #define SD_LANE_25G_SD_SER_RST(t) \ 2587 + __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4) 2813 2588 2814 2589 #define SD_LANE_25G_SD_SER_RST_SER_RST BIT(0) 2815 2590 #define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\ ··· 2819 2590 #define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\ 2820 2591 FIELD_GET(SD_LANE_25G_SD_SER_RST_SER_RST, x) 2821 2592 2822 - /* SD25G_CFG_TARGET:SD_RESET:SD_DES_RST */ 2823 - #define SD_LANE_25G_SD_DES_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4) 2593 + /* SPARX5 ONLY */ 2594 + /* SD25G_CFG_TARGET:SD_RESET:SD_DES_RST */ 2595 + #define SD_LANE_25G_SD_DES_RST(t) \ 2596 + __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4) 2824 2597 2825 2598 #define SD_LANE_25G_SD_DES_RST_DES_RST BIT(0) 2826 2599 #define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\ ··· 2830 2599 #define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\ 2831 2600 FIELD_GET(SD_LANE_25G_SD_DES_RST_DES_RST, x) 2832 2601 2833 - /* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ 2834 - #define SD_LANE_25G_SD_LANE_CFG(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4) 2602 + /* SPARX5 ONLY */ 2603 + /* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ 2604 + #define SD_LANE_25G_SD_LANE_CFG(t) \ 2605 + __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4) 2835 2606 2836 2607 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST BIT(0) 2837 2608 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\ ··· 2931 2698 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\ 2932 2699 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x) 2933 2700 2934 - /* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG2 */ 2935 - #define SD_LANE_25G_SD_LANE_CFG2(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4) 2701 + /* SPARX5 ONLY */ 2702 + /* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG2 */ 2703 + #define SD_LANE_25G_SD_LANE_CFG2(t) \ 2704 + __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4) 2936 2705 2937 2706 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL GENMASK(2, 0) 2938 2707 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\ ··· 3002 2767 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\ 3003 2768 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x) 3004 2769 3005 - /* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ 3006 - #define SD_LANE_25G_SD_LANE_STAT(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4) 2770 + /* SPARX5 ONLY */ 2771 + /* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ 2772 + #define SD_LANE_25G_SD_LANE_STAT(t) \ 2773 + __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4) 3007 2774 3008 2775 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE BIT(0) 3009 2776 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ ··· 3025 2788 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\ 3026 2789 FIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x) 3027 2790 3028 - /* SD25G_CFG_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ 3029 - #define SD_LANE_25G_QUIET_MODE_6G(t) \ 2791 + /* SPARX5 ONLY */ 2792 + /* SD25G_CFG_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ 2793 + #define SD_LANE_25G_QUIET_MODE_6G(t) \ 3030 2794 __REG(TARGET_SD_LANE_25G, t, 8, 28, 0, 1, 8, 4, 0, 1, 4) 3031 2795 3032 2796 #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0)