tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/amdgpu: switch UVD code to use UVD_NO_OP for padding

Replace packet2's with packet0 writes to UVD_NO_OP. The
value written to UVD_NO_OP does not matter.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher c8b4f288 4d6bdbad

+9 -5
+4 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
··· 957 957 ib->ptr[3] = addr >> 32; 958 958 ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); 959 959 ib->ptr[5] = 0; 960 - for (i = 6; i < 16; ++i) 961 - ib->ptr[i] = PACKET2(0); 960 + for (i = 6; i < 16; i += 2) { 961 + ib->ptr[i] = PACKET0(mmUVD_NO_OP, 0); 962 + ib->ptr[i+1] = 0; 963 + } 962 964 ib->length_dw = 16; 963 965 964 966 if (direct) {
+1 -1
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
··· 116 116 117 117 ring = &adev->uvd.ring; 118 118 sprintf(ring->name, "uvd"); 119 - r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, 119 + r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, 120 120 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); 121 121 122 122 return r;
+1 -1
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
··· 112 112 113 113 ring = &adev->uvd.ring; 114 114 sprintf(ring->name, "uvd"); 115 - r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, 115 + r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, 116 116 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); 117 117 118 118 return r;
+1 -1
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
··· 116 116 117 117 ring = &adev->uvd.ring; 118 118 sprintf(ring->name, "uvd"); 119 - r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, 119 + r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, 120 120 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); 121 121 122 122 return r;
+1
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h
··· 34 34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 35 35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 36 36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 37 + #define mmUVD_NO_OP 0x3bff 37 38 #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69 38 39 #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68 39 40 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67
+1
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h
··· 35 35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 36 36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 37 37 #define mmUVD_POWER_STATUS_U 0x3bfd 38 + #define mmUVD_NO_OP 0x3bff 38 39 #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69 39 40 #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68 40 41 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67