Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
clk: sunxi: add PRCM (Power/Reset/Clock Management) clks support
The PRCM (Power/Reset/Clock Management) unit provides several clock
devices:
- AR100 clk: used to clock the Power Management co-processor
- AHB0 clk: used to clock the AHB0 bus
- APB0 clk and gates: used to clk peripherals connected to the APB0 bus
Add support for these clks in a separate driver so that they can be probed
as platform devices instead of registered during early init.
This is needed to be able to probe PRCM MFD subdevices.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
authored by Boris BREZILLON and committed by Maxime Ripard c8a76cac efb3184c
+2
drivers/clk/sunxi/Makefile
+2
drivers/clk/sunxi/Makefile
+99
drivers/clk/sunxi/clk-sun6i-apb0-gates.c
+99
drivers/clk/sunxi/clk-sun6i-apb0-gates.c
···
···
1
+
/*
2
+
* Copyright (C) 2014 Free Electrons
3
+
*
4
+
* License Terms: GNU General Public License v2
5
+
* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
6
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*
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* Allwinner A31 APB0 clock gates driver
8
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*
9
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*/
10
+
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#include <linux/clk-provider.h>
12
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#include <linux/module.h>
13
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#include <linux/of.h>
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#include <linux/platform_device.h>
15
+
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#define SUN6I_APB0_GATES_MAX_SIZE 32
17
+
18
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static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
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+
{
20
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struct device_node *np = pdev->dev.of_node;
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struct clk_onecell_data *clk_data;
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const char *clk_parent;
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const char *clk_name;
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+
struct resource *r;
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+
void __iomem *reg;
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+
int gate_id;
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int ngates;
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int i;
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+
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(&pdev->dev, r);
32
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if (!reg)
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return PTR_ERR(reg);
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+
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clk_parent = of_clk_get_parent_name(np, 0);
36
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if (!clk_parent)
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return -EINVAL;
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+
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ngates = of_property_count_strings(np, "clock-output-names");
40
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if (ngates < 0)
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return ngates;
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+
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if (!ngates || ngates > SUN6I_APB0_GATES_MAX_SIZE)
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return -EINVAL;
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+
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clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data),
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GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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+
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clk_data->clks = devm_kzalloc(&pdev->dev,
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SUN6I_APB0_GATES_MAX_SIZE *
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sizeof(struct clk *),
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GFP_KERNEL);
55
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if (!clk_data->clks)
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return -ENOMEM;
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+
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for (i = 0; i < ngates; i++) {
59
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of_property_read_string_index(np, "clock-output-names",
60
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i, &clk_name);
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+
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gate_id = i;
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of_property_read_u32_index(np, "clock-indices", i, &gate_id);
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+
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WARN_ON(gate_id >= SUN6I_APB0_GATES_MAX_SIZE);
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if (gate_id >= SUN6I_APB0_GATES_MAX_SIZE)
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continue;
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+
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clk_data->clks[gate_id] = clk_register_gate(&pdev->dev,
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clk_name,
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clk_parent, 0,
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reg, gate_id,
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0, NULL);
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WARN_ON(IS_ERR(clk_data->clks[gate_id]));
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}
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+
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clk_data->clk_num = ngates;
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+
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return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
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}
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+
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const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
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{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk" },
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{ /* sentinel */ }
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};
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+
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static struct platform_driver sun6i_a31_apb0_gates_clk_driver = {
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.driver = {
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.name = "sun6i-a31-apb0-gates-clk",
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.owner = THIS_MODULE,
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.of_match_table = sun6i_a31_apb0_gates_clk_dt_ids,
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},
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.probe = sun6i_a31_apb0_gates_clk_probe,
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};
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module_platform_driver(sun6i_a31_apb0_gates_clk_driver);
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+
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MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
98
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MODULE_DESCRIPTION("Allwinner A31 APB0 gate clocks driver");
99
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MODULE_LICENSE("GPL v2");
+77
drivers/clk/sunxi/clk-sun6i-apb0.c
+77
drivers/clk/sunxi/clk-sun6i-apb0.c
···
···
1
+
/*
2
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* Copyright (C) 2014 Free Electrons
3
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*
4
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* License Terms: GNU General Public License v2
5
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
6
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*
7
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* Allwinner A31 APB0 clock driver
8
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*
9
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*/
10
+
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#include <linux/clk-provider.h>
12
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#include <linux/module.h>
13
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#include <linux/of.h>
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#include <linux/platform_device.h>
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+
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/*
17
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* The APB0 clk has a configurable divisor.
18
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*
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* We must use a clk_div_table and not a regular power of 2
20
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* divisor here, because the first 2 values divide the clock
21
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* by 2.
22
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*/
23
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static const struct clk_div_table sun6i_a31_apb0_divs[] = {
24
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{ .val = 0, .div = 2, },
25
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{ .val = 1, .div = 2, },
26
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{ .val = 2, .div = 4, },
27
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{ .val = 3, .div = 8, },
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{ /* sentinel */ },
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};
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+
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static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev)
32
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{
33
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struct device_node *np = pdev->dev.of_node;
34
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const char *clk_name = np->name;
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const char *clk_parent;
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struct resource *r;
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void __iomem *reg;
38
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struct clk *clk;
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+
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(&pdev->dev, r);
42
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if (IS_ERR(reg))
43
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return PTR_ERR(reg);
44
+
45
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clk_parent = of_clk_get_parent_name(np, 0);
46
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if (!clk_parent)
47
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return -EINVAL;
48
+
49
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of_property_read_string(np, "clock-output-names", &clk_name);
50
+
51
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clk = clk_register_divider_table(&pdev->dev, clk_name, clk_parent,
52
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0, reg, 0, 2, 0, sun6i_a31_apb0_divs,
53
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NULL);
54
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if (IS_ERR(clk))
55
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return PTR_ERR(clk);
56
+
57
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return of_clk_add_provider(np, of_clk_src_simple_get, clk);
58
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}
59
+
60
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const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = {
61
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{ .compatible = "allwinner,sun6i-a31-apb0-clk" },
62
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{ /* sentinel */ }
63
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};
64
+
65
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static struct platform_driver sun6i_a31_apb0_clk_driver = {
66
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.driver = {
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.name = "sun6i-a31-apb0-clk",
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.owner = THIS_MODULE,
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.of_match_table = sun6i_a31_apb0_clk_dt_ids,
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},
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.probe = sun6i_a31_apb0_clk_probe,
72
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};
73
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module_platform_driver(sun6i_a31_apb0_clk_driver);
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MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
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MODULE_DESCRIPTION("Allwinner A31 APB0 clock Driver");
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MODULE_LICENSE("GPL v2");
+233
drivers/clk/sunxi/clk-sun6i-ar100.c
+233
drivers/clk/sunxi/clk-sun6i-ar100.c
···
···
1
+
/*
2
+
* Copyright (C) 2014 Free Electrons
3
+
*
4
+
* License Terms: GNU General Public License v2
5
+
* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
6
+
*
7
+
* Allwinner A31 AR100 clock driver
8
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*
9
+
*/
10
+
11
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#include <linux/clk-provider.h>
12
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#include <linux/module.h>
13
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#include <linux/of.h>
14
+
#include <linux/platform_device.h>
15
+
16
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#define SUN6I_AR100_MAX_PARENTS 4
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#define SUN6I_AR100_SHIFT_MASK 0x3
18
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#define SUN6I_AR100_SHIFT_MAX SUN6I_AR100_SHIFT_MASK
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#define SUN6I_AR100_SHIFT_SHIFT 4
20
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#define SUN6I_AR100_DIV_MASK 0x1f
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#define SUN6I_AR100_DIV_MAX (SUN6I_AR100_DIV_MASK + 1)
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#define SUN6I_AR100_DIV_SHIFT 8
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#define SUN6I_AR100_MUX_MASK 0x3
24
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#define SUN6I_AR100_MUX_SHIFT 16
25
+
26
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struct ar100_clk {
27
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struct clk_hw hw;
28
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void __iomem *reg;
29
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};
30
+
31
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static inline struct ar100_clk *to_ar100_clk(struct clk_hw *hw)
32
+
{
33
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return container_of(hw, struct ar100_clk, hw);
34
+
}
35
+
36
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static unsigned long ar100_recalc_rate(struct clk_hw *hw,
37
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unsigned long parent_rate)
38
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{
39
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struct ar100_clk *clk = to_ar100_clk(hw);
40
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u32 val = readl(clk->reg);
41
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int shift = (val >> SUN6I_AR100_SHIFT_SHIFT) & SUN6I_AR100_SHIFT_MASK;
42
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int div = (val >> SUN6I_AR100_DIV_SHIFT) & SUN6I_AR100_DIV_MASK;
43
+
44
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return (parent_rate >> shift) / (div + 1);
45
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}
46
+
47
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static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate,
48
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unsigned long *best_parent_rate,
49
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struct clk **best_parent_clk)
50
+
{
51
+
int nparents = __clk_get_num_parents(hw->clk);
52
+
long best_rate = -EINVAL;
53
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int i;
54
+
55
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*best_parent_clk = NULL;
56
+
57
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for (i = 0; i < nparents; i++) {
58
+
unsigned long parent_rate;
59
+
unsigned long tmp_rate;
60
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struct clk *parent;
61
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unsigned long div;
62
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int shift;
63
+
64
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parent = clk_get_parent_by_index(hw->clk, i);
65
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parent_rate = __clk_get_rate(parent);
66
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div = DIV_ROUND_UP(parent_rate, rate);
67
+
68
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/*
69
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* The AR100 clk contains 2 divisors:
70
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* - one power of 2 divisor
71
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* - one regular divisor
72
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*
73
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* First check if we can safely shift (or divide by a power
74
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* of 2) without losing precision on the requested rate.
75
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*/
76
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shift = ffs(div) - 1;
77
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if (shift > SUN6I_AR100_SHIFT_MAX)
78
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shift = SUN6I_AR100_SHIFT_MAX;
79
+
80
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div >>= shift;
81
+
82
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/*
83
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* Then if the divisor is still bigger than what the HW
84
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* actually supports, use a bigger shift (or power of 2
85
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* divider) value and accept to lose some precision.
86
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*/
87
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while (div > SUN6I_AR100_DIV_MAX) {
88
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shift++;
89
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div >>= 1;
90
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if (shift > SUN6I_AR100_SHIFT_MAX)
91
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break;
92
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}
93
+
94
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/*
95
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* If the shift value (or power of 2 divider) is bigger
96
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* than what the HW actually support, skip this parent.
97
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*/
98
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if (shift > SUN6I_AR100_SHIFT_MAX)
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continue;
100
+
101
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tmp_rate = (parent_rate >> shift) / div;
102
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if (!*best_parent_clk || tmp_rate > best_rate) {
103
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*best_parent_clk = parent;
104
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*best_parent_rate = parent_rate;
105
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best_rate = tmp_rate;
106
+
}
107
+
}
108
+
109
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return best_rate;
110
+
}
111
+
112
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static int ar100_set_parent(struct clk_hw *hw, u8 index)
113
+
{
114
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struct ar100_clk *clk = to_ar100_clk(hw);
115
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u32 val = readl(clk->reg);
116
+
117
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if (index >= SUN6I_AR100_MAX_PARENTS)
118
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return -EINVAL;
119
+
120
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val &= ~(SUN6I_AR100_MUX_MASK << SUN6I_AR100_MUX_SHIFT);
121
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val |= (index << SUN6I_AR100_MUX_SHIFT);
122
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writel(val, clk->reg);
123
+
124
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return 0;
125
+
}
126
+
127
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static u8 ar100_get_parent(struct clk_hw *hw)
128
+
{
129
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struct ar100_clk *clk = to_ar100_clk(hw);
130
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return (readl(clk->reg) >> SUN6I_AR100_MUX_SHIFT) &
131
+
SUN6I_AR100_MUX_MASK;
132
+
}
133
+
134
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static int ar100_set_rate(struct clk_hw *hw, unsigned long rate,
135
+
unsigned long parent_rate)
136
+
{
137
+
unsigned long div = parent_rate / rate;
138
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struct ar100_clk *clk = to_ar100_clk(hw);
139
+
u32 val = readl(clk->reg);
140
+
int shift;
141
+
142
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if (parent_rate % rate)
143
+
return -EINVAL;
144
+
145
+
shift = ffs(div) - 1;
146
+
if (shift > SUN6I_AR100_SHIFT_MAX)
147
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shift = SUN6I_AR100_SHIFT_MAX;
148
+
149
+
div >>= shift;
150
+
151
+
if (div > SUN6I_AR100_DIV_MAX)
152
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return -EINVAL;
153
+
154
+
val &= ~((SUN6I_AR100_SHIFT_MASK << SUN6I_AR100_SHIFT_SHIFT) |
155
+
(SUN6I_AR100_DIV_MASK << SUN6I_AR100_DIV_SHIFT));
156
+
val |= (shift << SUN6I_AR100_SHIFT_SHIFT) |
157
+
(div << SUN6I_AR100_DIV_SHIFT);
158
+
writel(val, clk->reg);
159
+
160
+
return 0;
161
+
}
162
+
163
+
struct clk_ops ar100_ops = {
164
+
.recalc_rate = ar100_recalc_rate,
165
+
.determine_rate = ar100_determine_rate,
166
+
.set_parent = ar100_set_parent,
167
+
.get_parent = ar100_get_parent,
168
+
.set_rate = ar100_set_rate,
169
+
};
170
+
171
+
static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev)
172
+
{
173
+
const char *parents[SUN6I_AR100_MAX_PARENTS];
174
+
struct device_node *np = pdev->dev.of_node;
175
+
const char *clk_name = np->name;
176
+
struct clk_init_data init;
177
+
struct ar100_clk *ar100;
178
+
struct resource *r;
179
+
struct clk *clk;
180
+
int nparents;
181
+
int i;
182
+
183
+
ar100 = devm_kzalloc(&pdev->dev, sizeof(*ar100), GFP_KERNEL);
184
+
if (!ar100)
185
+
return -ENOMEM;
186
+
187
+
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
188
+
ar100->reg = devm_ioremap_resource(&pdev->dev, r);
189
+
if (IS_ERR(ar100->reg))
190
+
return PTR_ERR(ar100->reg);
191
+
192
+
nparents = of_clk_get_parent_count(np);
193
+
if (nparents > SUN6I_AR100_MAX_PARENTS)
194
+
nparents = SUN6I_AR100_MAX_PARENTS;
195
+
196
+
for (i = 0; i < nparents; i++)
197
+
parents[i] = of_clk_get_parent_name(np, i);
198
+
199
+
of_property_read_string(np, "clock-output-names", &clk_name);
200
+
201
+
init.name = clk_name;
202
+
init.ops = &ar100_ops;
203
+
init.parent_names = parents;
204
+
init.num_parents = nparents;
205
+
init.flags = 0;
206
+
207
+
ar100->hw.init = &init;
208
+
209
+
clk = clk_register(&pdev->dev, &ar100->hw);
210
+
if (IS_ERR(clk))
211
+
return PTR_ERR(clk);
212
+
213
+
return of_clk_add_provider(np, of_clk_src_simple_get, clk);
214
+
}
215
+
216
+
const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = {
217
+
{ .compatible = "allwinner,sun6i-a31-ar100-clk" },
218
+
{ /* sentinel */ }
219
+
};
220
+
221
+
static struct platform_driver sun6i_a31_ar100_clk_driver = {
222
+
.driver = {
223
+
.name = "sun6i-a31-ar100-clk",
224
+
.owner = THIS_MODULE,
225
+
.of_match_table = sun6i_a31_ar100_clk_dt_ids,
226
+
},
227
+
.probe = sun6i_a31_ar100_clk_probe,
228
+
};
229
+
module_platform_driver(sun6i_a31_ar100_clk_driver);
230
+
231
+
MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
232
+
MODULE_DESCRIPTION("Allwinner A31 AR100 clock Driver");
233
+
MODULE_LICENSE("GPL v2");