drm/amd/display: Pass DSC slice height to PSR FW

[Why]
When DSC is enabled, the PSRSU seletive update region
must be multiple number of DSC slice height number.
The original solution is to overwrite the SU Y granularity
by DSC slice height in DAL driver. However, the size
of the SU Y granularity variable only has 8 bytes
and the DSC slice height may over the 8 bytes size.

[How]
Instead of overwriting the SU Y granularity value,
add a new DSC slice height pararmeter and pass it
to DMUB PSRSU FW. The PSRSU FW will refer to the
DSC slice height value and extend the SU region.

Reviewed-by: Dennis Chan <[e-mail]>
Reviewed-by: ChunTao Tso <[e-mail]>
Acked-by: Alan Liu <[e-mail]>
Signed-off-by: Robin Chen <[e-mail]>
Tested-by: Daniel Wheeler <[e-mail]>
Signed-off-by: Alex Deucher <[e-mail]>

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

···
 		psr_config.allow_multi_disp_optimizations =
 			(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
 
-		if (!psr_su_set_y_granularity(dc, link, stream, &psr_config))
+		if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config))
 			return false;
 
 		ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);

drivers/gpu/drm/amd/display/dc/dc_types.h

···
 	uint8_t su_y_granularity;
 	unsigned int line_time_in_us;
 	uint8_t rate_control_caps;
+	uint16_t dsc_slice_height;
 };
 
 union dmcu_psr_level {
···
 	uint8_t su_y_granularity;
 	unsigned int line_time_in_us;
 	uint8_t rate_control_caps;
+	uint16_t dsc_slice_height;
 };
 
 struct colorspace_transform {

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

···
 	copy_settings_data->relock_delay_frame_cnt = 0;
 	if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
 		copy_settings_data->relock_delay_frame_cnt = 2;
+	copy_settings_data->dsc_slice_height = psr_context->dsc_slice_height;
 
 	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
 	dc_dmub_srv_cmd_execute(dc->dmub_srv);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

···
 	 */
 	psr_context->frame_delay = 0;
 
+	psr_context->dsc_slice_height = psr_config->dsc_slice_height;
+
 	if (psr) {
 		link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
 			link, psr_context, panel_inst);

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

···
 	 * Explicit padding to 2 byte boundary.
 	 */
 	uint8_t pad3;
+	/**
+	 * DSC Slice height.
+	 */
+	uint16_t dsc_slice_height;
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint16_t pad;
 };
 
 /**

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

···
 	return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal);
 }
 
-bool psr_su_set_y_granularity(struct dc *dc, struct dc_link *link,
+bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
 			      struct dc_stream_state *stream,
 			      struct psr_config *config)
 {
 	uint16_t pic_height;
-	uint8_t slice_height;
+	uint16_t slice_height;
 
+	config->dsc_slice_height = 0;
 	if ((link->connector_signal & SIGNAL_TYPE_EDP) &&
 	    (!dc->caps.edp_dsc_support ||
 	    link->panel_config.dsc.disable_dsc_edp ||
···
 	pic_height = stream->timing.v_addressable +
 		stream->timing.v_border_top + stream->timing.v_border_bottom;
 	slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;
+	config->dsc_slice_height = slice_height;
 
 	if (slice_height) {
 		if (config->su_y_granularity &&
···
 			ASSERT(0);
 			return false;
 		}
-
-		config->su_y_granularity = slice_height;
 	}
 
 	return true;

drivers/gpu/drm/amd/display/modules/power/power_helpers.h

···
 		const struct dc_stream_state *stream);
 bool mod_power_only_edp(const struct dc_state *context,
 		const struct dc_stream_state *stream);
-bool psr_su_set_y_granularity(struct dc *dc, struct dc_link *link,
+bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
 			      struct dc_stream_state *stream,
 			      struct psr_config *config);
 #endif /* MODULES_POWER_POWER_HELPERS_H_ */