tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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blackfin: dmc: Improve DDR2 write through in DMC effict controller.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Steven Miao <realmz6@gmail.com>

authored by

Sonic Zhang and committed by
Steven Miao c83a9171 c1be5a5b

+11
+9
arch/blackfin/include/asm/mem_init.h
··· 335 335 struct ddr_config { 336 336 u32 ddr_clk; 337 337 u32 dmc_ddrctl; 338 + u32 dmc_effctl; 338 339 u32 dmc_ddrcfg; 339 340 u32 dmc_ddrtr0; 340 341 u32 dmc_ddrtr1; ··· 349 348 [0] = { 350 349 .ddr_clk = 125, 351 350 .dmc_ddrctl = 0x00000904, 351 + .dmc_effctl = 0x004400C0, 352 352 .dmc_ddrcfg = 0x00000422, 353 353 .dmc_ddrtr0 = 0x20705212, 354 354 .dmc_ddrtr1 = 0x201003CF, ··· 360 358 [1] = { 361 359 .ddr_clk = 133, 362 360 .dmc_ddrctl = 0x00000904, 361 + .dmc_effctl = 0x004400C0, 363 362 .dmc_ddrcfg = 0x00000422, 364 363 .dmc_ddrtr0 = 0x20806313, 365 364 .dmc_ddrtr1 = 0x2013040D, ··· 371 368 [2] = { 372 369 .ddr_clk = 150, 373 370 .dmc_ddrctl = 0x00000904, 371 + .dmc_effctl = 0x004400C0, 374 372 .dmc_ddrcfg = 0x00000422, 375 373 .dmc_ddrtr0 = 0x20A07323, 376 374 .dmc_ddrtr1 = 0x20160492, ··· 382 378 [3] = { 383 379 .ddr_clk = 166, 384 380 .dmc_ddrctl = 0x00000904, 381 + .dmc_effctl = 0x004400C0, 385 382 .dmc_ddrcfg = 0x00000422, 386 383 .dmc_ddrtr0 = 0x20A07323, 387 384 .dmc_ddrtr1 = 0x2016050E, ··· 393 388 [4] = { 394 389 .ddr_clk = 200, 395 390 .dmc_ddrctl = 0x00000904, 391 + .dmc_effctl = 0x004400C0, 396 392 .dmc_ddrcfg = 0x00000422, 397 393 .dmc_ddrtr0 = 0x20a07323, 398 394 .dmc_ddrtr1 = 0x2016050f, ··· 404 398 [5] = { 405 399 .ddr_clk = 225, 406 400 .dmc_ddrctl = 0x00000904, 401 + .dmc_effctl = 0x004400C0, 407 402 .dmc_ddrcfg = 0x00000422, 408 403 .dmc_ddrtr0 = 0x20E0A424, 409 404 .dmc_ddrtr1 = 0x302006DB, ··· 415 408 [6] = { 416 409 .ddr_clk = 250, 417 410 .dmc_ddrctl = 0x00000904, 411 + .dmc_effctl = 0x004400C0, 418 412 .dmc_ddrcfg = 0x00000422, 419 413 .dmc_ddrtr0 = 0x20E0A424, 420 414 .dmc_ddrtr1 = 0x3020079E, ··· 477 469 bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2); 478 470 bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr); 479 471 bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1); 472 + bfin_write_DMC0_EFFCTL(ddr_config_table[i].dmc_effctl); 480 473 bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl); 481 474 break; 482 475 }
+2
arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
··· 312 312 #define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val) 313 313 #define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL) 314 314 #define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val) 315 + #define bfin_read_DMC0_EFFCTL() bfin_read32(DMC0_EFFCTL) 316 + #define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val) 315 317 #define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT) 316 318 #define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val) 317 319 #define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)