tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'net-stmmac-rk-use-phy_intf_sel_x'

Russell King says:

====================
net: stmmac: rk: use PHY_INTF_SEL_x

This series is a minimal conversion of the dwmac-rk huge driver to use
PHY_INTF_SEL_x constants.

Patch 2 appears to reorder the output functions making diffing the
generated code impossible.
====================

Link: https://patch.msgid.link/aRYZaKTIvfYoV3wE@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski c7b6dd2a 04ca7a69

+109 -136
+109 -136
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
··· 149 149 return clk_set_rate(clk_mac_speed, rate); 150 150 } 151 151 152 - #define HIWORD_UPDATE(val, mask, shift) \ 153 - (FIELD_PREP_WM16((mask) << (shift), (val))) 152 + #define GRF_FIELD(hi, lo, val) \ 153 + FIELD_PREP_WM16(GENMASK_U16(hi, lo), val) 154 + #define GRF_FIELD_CONST(hi, lo, val) \ 155 + FIELD_PREP_WM16_CONST(GENMASK_U16(hi, lo), val) 154 156 155 - #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 156 - #define GRF_CLR_BIT(nr) (BIT(nr+16)) 157 + #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 158 + #define GRF_CLR_BIT(nr) (BIT(nr+16)) 157 159 158 160 #define DELAY_ENABLE(soc, tx, rx) \ 159 161 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ ··· 169 167 #define RK_MACPHY_ENABLE GRF_BIT(0) 170 168 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) 171 169 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) 172 - #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) 173 - #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) 174 - #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) 170 + #define RK_GMAC2PHY_RMII_MODE GRF_FIELD(7, 6, 1) 171 + #define RK_GRF_CON2_MACPHY_ID GRF_FIELD(15, 0, 0x1234) 172 + #define RK_GRF_CON3_MACPHY_ID GRF_FIELD(5, 0, 0x35) 175 173 176 174 static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv) 177 175 { ··· 205 203 #define RK_FEPHY_SHUTDOWN GRF_BIT(1) 206 204 #define RK_FEPHY_POWERUP GRF_CLR_BIT(1) 207 205 #define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6) 208 - #define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9)) 206 + #define RK_FEPHY_24M_CLK_SEL GRF_FIELD(9, 8, 3) 209 207 #define RK_FEPHY_PHY_ID GRF_BIT(11) 210 208 211 209 static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv, ··· 234 232 #define PX30_GRF_GMAC_CON1 0x0904 235 233 236 234 /* PX30_GRF_GMAC_CON1 */ 237 - #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 238 - GRF_BIT(6)) 235 + #define PX30_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val) 239 236 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) 240 237 #define PX30_GMAC_SPEED_100M GRF_BIT(2) 241 238 242 239 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) 243 240 { 244 241 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 245 - PX30_GMAC_PHY_INTF_SEL_RMII); 242 + PX30_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII)); 246 243 } 247 244 248 245 static int px30_set_speed(struct rk_priv_data *bsp_priv, ··· 286 285 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 287 286 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 288 287 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 289 - #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 290 - #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 288 + #define RK3128_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val) 289 + #define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 291 290 292 291 /* RK3128_GRF_MAC_CON1 */ 293 - #define RK3128_GMAC_PHY_INTF_SEL_RGMII \ 294 - (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) 295 - #define RK3128_GMAC_PHY_INTF_SEL_RMII \ 296 - (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8)) 292 + #define RK3128_GMAC_PHY_INTF_SEL(val) GRF_FIELD(8, 6, val) 297 293 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) 298 294 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 299 295 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) 300 296 #define RK3128_GMAC_SPEED_100M GRF_BIT(10) 301 297 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) 302 298 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 303 - #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 304 - #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 305 - #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 299 + #define RK3128_GMAC_CLK_125M GRF_FIELD_CONST(13, 12, 0) 300 + #define RK3128_GMAC_CLK_25M GRF_FIELD_CONST(13, 12, 3) 301 + #define RK3128_GMAC_CLK_2_5M GRF_FIELD_CONST(13, 12, 2) 306 302 #define RK3128_GMAC_RMII_MODE GRF_BIT(14) 307 303 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 308 304 ··· 307 309 int tx_delay, int rx_delay) 308 310 { 309 311 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 310 - RK3128_GMAC_PHY_INTF_SEL_RGMII | 312 + RK3128_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 311 313 RK3128_GMAC_RMII_MODE_CLR); 312 314 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, 313 315 DELAY_ENABLE(RK3128, tx_delay, rx_delay) | ··· 318 320 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) 319 321 { 320 322 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 321 - RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE); 323 + RK3128_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 324 + RK3128_GMAC_RMII_MODE); 322 325 } 323 326 324 327 static const struct rk_reg_speed_data rk3128_reg_speed_data = { ··· 349 350 #define RK3228_GRF_CON_MUX 0x50 350 351 351 352 /* RK3228_GRF_MAC_CON0 */ 352 - #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 353 - #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 353 + #define RK3228_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val) 354 + #define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 354 355 355 356 /* RK3228_GRF_MAC_CON1 */ 356 - #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ 357 - (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 358 - #define RK3228_GMAC_PHY_INTF_SEL_RMII \ 359 - (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 357 + #define RK3228_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val) 360 358 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 361 359 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 362 360 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 363 361 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 364 362 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 365 363 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 366 - #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) 367 - #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) 368 - #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) 364 + #define RK3228_GMAC_CLK_125M GRF_FIELD_CONST(9, 8, 0) 365 + #define RK3228_GMAC_CLK_25M GRF_FIELD_CONST(9, 8, 3) 366 + #define RK3228_GMAC_CLK_2_5M GRF_FIELD_CONST(9, 8, 2) 369 367 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 370 368 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 371 369 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) ··· 377 381 int tx_delay, int rx_delay) 378 382 { 379 383 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 380 - RK3228_GMAC_PHY_INTF_SEL_RGMII | 384 + RK3228_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 381 385 RK3228_GMAC_RMII_MODE_CLR | 382 386 DELAY_ENABLE(RK3228, tx_delay, rx_delay)); 383 387 ··· 389 393 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 390 394 { 391 395 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 392 - RK3228_GMAC_PHY_INTF_SEL_RMII | 396 + RK3228_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 393 397 RK3228_GMAC_RMII_MODE); 394 398 395 399 /* set MAC to RMII mode */ ··· 431 435 #define RK3288_GRF_SOC_CON3 0x0250 432 436 433 437 /*RK3288_GRF_SOC_CON1*/ 434 - #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ 435 - GRF_CLR_BIT(8)) 436 - #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ 437 - GRF_BIT(8)) 438 + #define RK3288_GMAC_PHY_INTF_SEL(val) GRF_FIELD(8, 6, val) 438 439 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 439 440 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 440 441 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 441 442 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 442 443 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 443 444 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 444 - #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 445 - #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 446 - #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 445 + #define RK3288_GMAC_CLK_125M GRF_FIELD_CONST(13, 12, 0) 446 + #define RK3288_GMAC_CLK_25M GRF_FIELD_CONST(13, 12, 3) 447 + #define RK3288_GMAC_CLK_2_5M GRF_FIELD_CONST(13, 12, 2) 447 448 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 448 449 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 449 450 ··· 449 456 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 450 457 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 451 458 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 452 - #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 453 - #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 459 + #define RK3288_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val) 460 + #define RK3288_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 454 461 455 462 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 456 463 int tx_delay, int rx_delay) 457 464 { 458 465 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 459 - RK3288_GMAC_PHY_INTF_SEL_RGMII | 466 + RK3288_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 460 467 RK3288_GMAC_RMII_MODE_CLR); 461 468 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 462 469 DELAY_ENABLE(RK3288, tx_delay, rx_delay) | ··· 467 474 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 468 475 { 469 476 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 470 - RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); 477 + RK3288_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 478 + RK3288_GMAC_RMII_MODE); 471 479 } 472 480 473 481 static const struct rk_reg_speed_data rk3288_reg_speed_data = { ··· 495 501 #define RK3308_GRF_MAC_CON0 0x04a0 496 502 497 503 /* RK3308_GRF_MAC_CON0 */ 498 - #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \ 499 - GRF_BIT(4)) 504 + #define RK3308_GMAC_PHY_INTF_SEL(val) GRF_FIELD(4, 2, val) 500 505 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) 501 506 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 502 507 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0) ··· 504 511 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) 505 512 { 506 513 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 507 - RK3308_GMAC_PHY_INTF_SEL_RMII); 514 + RK3308_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII)); 508 515 } 509 516 510 517 static const struct rk_reg_speed_data rk3308_reg_speed_data = { ··· 530 537 #define RK3328_GRF_MACPHY_CON1 0xb04 531 538 532 539 /* RK3328_GRF_MAC_CON0 */ 533 - #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 534 - #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 540 + #define RK3328_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val) 541 + #define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 535 542 536 543 /* RK3328_GRF_MAC_CON1 */ 537 - #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ 538 - (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 539 - #define RK3328_GMAC_PHY_INTF_SEL_RMII \ 540 - (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 544 + #define RK3328_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val) 541 545 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 542 546 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 543 547 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) 544 548 #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 545 549 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 546 550 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 547 - #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) 548 - #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) 549 - #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) 551 + #define RK3328_GMAC_CLK_125M GRF_FIELD_CONST(12, 11, 0) 552 + #define RK3328_GMAC_CLK_25M GRF_FIELD_CONST(12, 11, 3) 553 + #define RK3328_GMAC_CLK_2_5M GRF_FIELD_CONST(12, 11, 2) 550 554 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 551 555 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 552 556 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) ··· 556 566 int tx_delay, int rx_delay) 557 567 { 558 568 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 559 - RK3328_GMAC_PHY_INTF_SEL_RGMII | 569 + RK3328_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 560 570 RK3328_GMAC_RMII_MODE_CLR | 561 571 RK3328_GMAC_RXCLK_DLY_ENABLE | 562 572 RK3328_GMAC_TXCLK_DLY_ENABLE); ··· 574 584 RK3328_GRF_MAC_CON1; 575 585 576 586 regmap_write(bsp_priv->grf, reg, 577 - RK3328_GMAC_PHY_INTF_SEL_RMII | 587 + RK3328_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 578 588 RK3328_GMAC_RMII_MODE); 579 589 } 580 590 ··· 620 630 #define RK3366_GRF_SOC_CON7 0x041c 621 631 622 632 /* RK3366_GRF_SOC_CON6 */ 623 - #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 624 - GRF_CLR_BIT(11)) 625 - #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 626 - GRF_BIT(11)) 633 + #define RK3366_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val) 627 634 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 628 635 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 629 636 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 630 637 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 631 638 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 632 639 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 633 - #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 634 - #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 635 - #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 640 + #define RK3366_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0) 641 + #define RK3366_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3) 642 + #define RK3366_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2) 636 643 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 637 644 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 638 645 ··· 638 651 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 639 652 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 640 653 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 641 - #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 642 - #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 654 + #define RK3366_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 655 + #define RK3366_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 643 656 644 657 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 645 658 int tx_delay, int rx_delay) 646 659 { 647 660 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 648 - RK3366_GMAC_PHY_INTF_SEL_RGMII | 661 + RK3366_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 649 662 RK3366_GMAC_RMII_MODE_CLR); 650 663 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 651 664 DELAY_ENABLE(RK3366, tx_delay, rx_delay) | ··· 656 669 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 657 670 { 658 671 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 659 - RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); 672 + RK3366_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 673 + RK3366_GMAC_RMII_MODE); 660 674 } 661 675 662 676 static const struct rk_reg_speed_data rk3366_reg_speed_data = { ··· 685 697 #define RK3368_GRF_SOC_CON16 0x0440 686 698 687 699 /* RK3368_GRF_SOC_CON15 */ 688 - #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 689 - GRF_CLR_BIT(11)) 690 - #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 691 - GRF_BIT(11)) 700 + #define RK3368_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val) 692 701 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 693 702 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 694 703 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 695 704 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 696 705 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 697 706 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 698 - #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 699 - #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 700 - #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 707 + #define RK3368_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0) 708 + #define RK3368_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3) 709 + #define RK3368_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2) 701 710 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 702 711 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 703 712 ··· 703 718 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 704 719 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 705 720 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 706 - #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 707 - #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 721 + #define RK3368_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 722 + #define RK3368_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 708 723 709 724 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 710 725 int tx_delay, int rx_delay) 711 726 { 712 727 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 713 - RK3368_GMAC_PHY_INTF_SEL_RGMII | 728 + RK3368_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 714 729 RK3368_GMAC_RMII_MODE_CLR); 715 730 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 716 731 DELAY_ENABLE(RK3368, tx_delay, rx_delay) | ··· 721 736 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 722 737 { 723 738 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 724 - RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); 739 + RK3368_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 740 + RK3368_GMAC_RMII_MODE); 725 741 } 726 742 727 743 static const struct rk_reg_speed_data rk3368_reg_speed_data = { ··· 750 764 #define RK3399_GRF_SOC_CON6 0xc218 751 765 752 766 /* RK3399_GRF_SOC_CON5 */ 753 - #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 754 - GRF_CLR_BIT(11)) 755 - #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 756 - GRF_BIT(11)) 767 + #define RK3399_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val) 757 768 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 758 769 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 759 770 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 760 771 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 761 772 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 762 773 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 763 - #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 764 - #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 765 - #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 774 + #define RK3399_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0) 775 + #define RK3399_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3) 776 + #define RK3399_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2) 766 777 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 767 778 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 768 779 ··· 768 785 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 769 786 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 770 787 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 771 - #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 772 - #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 788 + #define RK3399_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 789 + #define RK3399_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 773 790 774 791 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 775 792 int tx_delay, int rx_delay) 776 793 { 777 794 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 778 - RK3399_GMAC_PHY_INTF_SEL_RGMII | 795 + RK3399_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 779 796 RK3399_GMAC_RMII_MODE_CLR); 780 797 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 781 798 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | ··· 786 803 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 787 804 { 788 805 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 789 - RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); 806 + RK3399_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 807 + RK3399_GMAC_RMII_MODE); 790 808 } 791 809 792 810 static const struct rk_reg_speed_data rk3399_reg_speed_data = { ··· 885 901 #define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 886 902 #define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 887 903 888 - #define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 889 - #define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 904 + #define RK3528_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val) 905 + #define RK3528_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val) 890 906 891 907 #define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) 892 908 #define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) ··· 900 916 #define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) 901 917 #define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) 902 918 903 - #define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10)) 904 - #define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10)) 905 - #define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10)) 919 + #define RK3528_GMAC1_CLK_RGMII_DIV1 GRF_FIELD_CONST(11, 10, 0) 920 + #define RK3528_GMAC1_CLK_RGMII_DIV5 GRF_FIELD_CONST(11, 10, 3) 921 + #define RK3528_GMAC1_CLK_RGMII_DIV50 GRF_FIELD_CONST(11, 10, 2) 906 922 907 923 #define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) 908 924 #define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) ··· 1013 1029 #define RK3568_GRF_GMAC1_CON1 0x038c 1014 1030 1015 1031 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ 1016 - #define RK3568_GMAC_PHY_INTF_SEL_RGMII \ 1017 - (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 1018 - #define RK3568_GMAC_PHY_INTF_SEL_RMII \ 1019 - (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 1032 + #define RK3568_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val) 1020 1033 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) 1021 1034 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1022 1035 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) ··· 1022 1041 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 1023 1042 1024 1043 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ 1025 - #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1026 - #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1044 + #define RK3568_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 1045 + #define RK3568_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 1027 1046 1028 1047 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, 1029 1048 int tx_delay, int rx_delay) ··· 1040 1059 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); 1041 1060 1042 1061 regmap_write(bsp_priv->grf, con1, 1043 - RK3568_GMAC_PHY_INTF_SEL_RGMII | 1062 + RK3568_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 1044 1063 RK3568_GMAC_RXCLK_DLY_ENABLE | 1045 1064 RK3568_GMAC_TXCLK_DLY_ENABLE); 1046 1065 } ··· 1051 1070 1052 1071 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 1053 1072 RK3568_GRF_GMAC0_CON1; 1054 - regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII); 1073 + regmap_write(bsp_priv->grf, con1, 1074 + RK3568_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII)); 1055 1075 } 1056 1076 1057 1077 static const struct rk_gmac_ops rk3568_ops = { ··· 1078 1096 #define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 1079 1097 #define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 1080 1098 1081 - #define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1082 - #define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1099 + #define RK3576_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 1100 + #define RK3576_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 1083 1101 1084 1102 /* SDGMAC_GRF */ 1085 1103 #define RK3576_GRF_GMAC_CON0 0X0020 ··· 1094 1112 #define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) 1095 1113 #define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) 1096 1114 1097 - #define RK3576_GMAC_CLK_RGMII_DIV1 \ 1098 - (GRF_CLR_BIT(6) | GRF_CLR_BIT(5)) 1099 - #define RK3576_GMAC_CLK_RGMII_DIV5 \ 1100 - (GRF_BIT(6) | GRF_BIT(5)) 1101 - #define RK3576_GMAC_CLK_RGMII_DIV50 \ 1102 - (GRF_BIT(6) | GRF_CLR_BIT(5)) 1115 + #define RK3576_GMAC_CLK_RGMII_DIV1 GRF_FIELD_CONST(6, 5, 0) 1116 + #define RK3576_GMAC_CLK_RGMII_DIV5 GRF_FIELD_CONST(6, 5, 3) 1117 + #define RK3576_GMAC_CLK_RGMII_DIV50 GRF_FIELD_CONST(6, 5, 2) 1103 1118 1104 1119 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) 1105 1120 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) ··· 1199 1220 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2) 1200 1221 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2) 1201 1222 1202 - #define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 1203 - #define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 1223 + #define RK3588_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val) 1224 + #define RK3588_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val) 1204 1225 1205 1226 /* php_grf */ 1206 1227 #define RK3588_GRF_GMAC_CON0 0X0008 1207 1228 #define RK3588_GRF_CLK_CON1 0X0070 1208 1229 1209 - #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \ 1210 - (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6)) 1211 - #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \ 1212 - (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6)) 1230 + #define RK3588_GMAC_PHY_INTF_SEL(id, val) \ 1231 + (GRF_FIELD(5, 3, val) << ((id) * 6)) 1213 1232 1214 1233 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) 1215 1234 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) ··· 1219 1242 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2) 1220 1243 1221 1244 #define RK3588_GMAC_CLK_RGMII_DIV1(id) \ 1222 - (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3)) 1245 + (GRF_FIELD_CONST(3, 2, 0) << ((id) * 5)) 1223 1246 #define RK3588_GMAC_CLK_RGMII_DIV5(id) \ 1224 - (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1247 + (GRF_FIELD_CONST(3, 2, 3) << ((id) * 5)) 1225 1248 #define RK3588_GMAC_CLK_RGMII_DIV50(id) \ 1226 - (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1249 + (GRF_FIELD_CONST(3, 2, 2) << ((id) * 5)) 1227 1250 1228 1251 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) 1229 1252 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) ··· 1237 1260 RK3588_GRF_GMAC_CON8; 1238 1261 1239 1262 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1240 - RK3588_GMAC_PHY_INTF_SEL_RGMII(id)); 1263 + RK3588_GMAC_PHY_INTF_SEL(id, PHY_INTF_SEL_RGMII)); 1241 1264 1242 1265 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1243 1266 RK3588_GMAC_CLK_RGMII_MODE(id)); ··· 1254 1277 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) 1255 1278 { 1256 1279 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1257 - RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id)); 1280 + RK3588_GMAC_PHY_INTF_SEL(bsp_priv->id, PHY_INTF_SEL_RMII)); 1258 1281 1259 1282 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1260 1283 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); ··· 1324 1347 #define RV1108_GRF_GMAC_CON0 0X0900 1325 1348 1326 1349 /* RV1108_GRF_GMAC_CON0 */ 1327 - #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 1328 - GRF_BIT(6)) 1350 + #define RV1108_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val) 1329 1351 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 1330 1352 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1331 1353 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) ··· 1335 1359 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 1336 1360 { 1337 1361 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1338 - RV1108_GMAC_PHY_INTF_SEL_RMII); 1362 + RV1108_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII)); 1339 1363 } 1340 1364 1341 1365 static const struct rk_reg_speed_data rv1108_reg_speed_data = { ··· 1360 1384 #define RV1126_GRF_GMAC_CON2 0X0078 1361 1385 1362 1386 /* RV1126_GRF_GMAC_CON0 */ 1363 - #define RV1126_GMAC_PHY_INTF_SEL_RGMII \ 1364 - (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 1365 - #define RV1126_GMAC_PHY_INTF_SEL_RMII \ 1366 - (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 1387 + #define RV1126_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val) 1367 1388 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7) 1368 1389 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7) 1369 1390 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1) ··· 1373 1400 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2) 1374 1401 1375 1402 /* RV1126_GRF_GMAC_CON1 */ 1376 - #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1377 - #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1403 + #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 1404 + #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 1378 1405 /* RV1126_GRF_GMAC_CON2 */ 1379 - #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1380 - #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1406 + #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 1407 + #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 1381 1408 1382 1409 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, 1383 1410 int tx_delay, int rx_delay) 1384 1411 { 1385 1412 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1386 - RV1126_GMAC_PHY_INTF_SEL_RGMII | 1413 + RV1126_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 1387 1414 RV1126_GMAC_M0_RXCLK_DLY_ENABLE | 1388 1415 RV1126_GMAC_M0_TXCLK_DLY_ENABLE | 1389 1416 RV1126_GMAC_M1_RXCLK_DLY_ENABLE | ··· 1401 1428 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) 1402 1429 { 1403 1430 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1404 - RV1126_GMAC_PHY_INTF_SEL_RMII); 1431 + RV1126_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII)); 1405 1432 } 1406 1433 1407 1434 static const struct rk_gmac_ops rv1126_ops = {