Merge tag 'gvt-next-fixes-2021-04-29' of https://github.com/intel/gvt-linux into drm-intel-next-fixes

gvt-next-fixes-2021-04-29

- Fix possible divide error in vgpu display rate calculation (Colin)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210429085142.GT1551@zhen-hp.sh.intel.com

+3 -3
+3 -3
drivers/gpu/drm/i915/gvt/handlers.c
··· 669 669 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)); 670 670 671 671 /* Get H/V total from transcoder timing */ 672 - htotal = (vgpu_vreg_t(vgpu, HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT) + 1; 673 - vtotal = (vgpu_vreg_t(vgpu, VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT) + 1; 672 + htotal = (vgpu_vreg_t(vgpu, HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); 673 + vtotal = (vgpu_vreg_t(vgpu, VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); 674 674 675 675 if (dp_br && link_n && htotal && vtotal) { 676 676 u64 pixel_clk = 0; ··· 682 682 pixel_clk *= MSEC_PER_SEC; 683 683 684 684 /* Calcuate refresh rate by (pixel_clk / (h_total * v_total)) */ 685 - new_rate = DIV64_U64_ROUND_CLOSEST(pixel_clk, div64_u64(mul_u32_u32(htotal, vtotal), MSEC_PER_SEC)); 685 + new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1)); 686 686 687 687 if (*old_rate != new_rate) 688 688 *old_rate = new_rate;