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ARM: dts: Cygnus: Fix most DTC W=1 warnings
Fix the bulk of the unit_address_vs_reg warnings and unnecessary
\#address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+9
-11
+6
-6
arch/arm/boot/dts/bcm-cygnus-clock.dtsi
+6
-6
arch/arm/boot/dts/bcm-cygnus-clock.dtsi
···
42
42
};
43
43
44
44
/* Cygnus ARM PLL */
45
-
armpll: armpll {
45
+
armpll: armpll@19000000 {
46
46
#clock-cells = <0>;
47
47
compatible = "brcm,cygnus-armpll";
48
48
clocks = <&osc>;
···
67
67
clock-mult = <1>;
68
68
};
69
69
70
-
genpll: genpll {
70
+
genpll: genpll@301d000 {
71
71
#clock-cells = <1>;
72
72
compatible = "brcm,cygnus-genpll";
73
73
reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
···
94
94
clock-mult = <1>;
95
95
};
96
96
97
-
lcpll0: lcpll0 {
97
+
lcpll0: lcpll0@301d02c {
98
98
#clock-cells = <1>;
99
99
compatible = "brcm,cygnus-lcpll0";
100
100
reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>;
···
103
103
"usb_phy", "smart_card", "ch5";
104
104
};
105
105
106
-
mipipll: mipipll {
106
+
mipipll: mipipll@180a9800 {
107
107
#clock-cells = <1>;
108
108
compatible = "brcm,cygnus-mipipll";
109
109
reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>;
···
113
113
"ch5_unused";
114
114
};
115
115
116
-
asiu_clks: asiu_clks {
116
+
asiu_clks: asiu_clks@301d048 {
117
117
#clock-cells = <1>;
118
118
compatible = "brcm,cygnus-asiu-clk";
119
119
reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
···
122
122
clock-output-names = "keypad", "adc/touch", "pwm";
123
123
};
124
124
125
-
audiopll: audiopll {
125
+
audiopll: audiopll@180aeb00 {
126
126
#clock-cells = <1>;
127
127
compatible = "brcm,cygnus-audiopll";
128
128
reg = <0x180aeb00 0x68>;
+3
-3
arch/arm/boot/dts/bcm-cygnus.dtsi
+3
-3
arch/arm/boot/dts/bcm-cygnus.dtsi
···
45
45
ethernet0 = ð0;
46
46
};
47
47
48
-
memory {
48
+
memory@0 {
49
49
device_type = "memory";
50
50
reg = <0 0>;
51
51
};
···
69
69
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
70
70
};
71
71
72
-
core {
72
+
core@19000000 {
73
73
compatible = "simple-bus";
74
74
ranges = <0x00000000 0x19000000 0x1000000>;
75
75
#address-cells = <1>;
···
91
91
<0x20100 0x100>;
92
92
};
93
93
94
-
L2: l2-cache {
94
+
L2: l2-cache@22000 {
95
95
compatible = "arm,pl310-cache";
96
96
reg = <0x22000 0x1000>;
97
97
cache-unified;