tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

[ARM] nommu: rename compressed/head.S symbols to a new style

This patch renames symbols to a new style to prepare mpu support
code merging. e.g. __armv4_cache_on --> __armv4_mmu_cache_on

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

authored by

Hyok S. Choi and committed by
Russell King c76b6b41 48fa14f7

+41 -41
unified split
+41 -41
arch/arm/boot/compressed/head.S
··· 358 358 str r1, [r0] 359 359 mov pc, lr 360 360 361 - __armv4_cache_on: 361 + __armv4_mmu_cache_on: 362 362 mov r12, lr 363 363 bl __setup_mmu 364 364 mov r0, #0 ··· 367 367 mrc p15, 0, r0, c1, c0, 0 @ read control reg 368 368 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 369 369 orr r0, r0, #0x0030 370 - bl __common_cache_on 370 + bl __common_mmu_cache_on 371 371 mov r0, #0 372 372 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 373 373 mov pc, r12 374 374 375 - __arm6_cache_on: 375 + __arm6_mmu_cache_on: 376 376 mov r12, lr 377 377 bl __setup_mmu 378 378 mov r0, #0 379 379 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 380 380 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 381 381 mov r0, #0x30 382 - bl __common_cache_on 382 + bl __common_mmu_cache_on 383 383 mov r0, #0 384 384 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 385 385 mov pc, r12 386 386 387 - __common_cache_on: 387 + __common_mmu_cache_on: 388 388 #ifndef DEBUG 389 389 orr r0, r0, #0x000d @ Write buffer, mmu 390 390 #endif ··· 471 471 proc_types: 472 472 .word 0x41560600 @ ARM6/610 473 473 .word 0xffffffe0 474 - b __arm6_cache_off @ works, but slow 475 - b __arm6_cache_off 474 + b __arm6_mmu_cache_off @ works, but slow 475 + b __arm6_mmu_cache_off 476 476 mov pc, lr 477 - @ b __arm6_cache_on @ untested 478 - @ b __arm6_cache_off 479 - @ b __armv3_cache_flush 477 + @ b __arm6_mmu_cache_on @ untested 478 + @ b __arm6_mmu_cache_off 479 + @ b __armv3_mmu_cache_flush 480 480 481 481 .word 0x00000000 @ old ARM ID 482 482 .word 0x0000f000 ··· 486 486 487 487 .word 0x41007000 @ ARM7/710 488 488 .word 0xfff8fe00 489 - b __arm7_cache_off 490 - b __arm7_cache_off 489 + b __arm7_mmu_cache_off 490 + b __arm7_mmu_cache_off 491 491 mov pc, lr 492 492 493 493 .word 0x41807200 @ ARM720T (writethrough) 494 494 .word 0xffffff00 495 - b __armv4_cache_on 496 - b __armv4_cache_off 495 + b __armv4_mmu_cache_on 496 + b __armv4_mmu_cache_off 497 497 mov pc, lr 498 498 499 499 .word 0x00007000 @ ARM7 IDs ··· 506 506 507 507 .word 0x4401a100 @ sa110 / sa1100 508 508 .word 0xffffffe0 509 - b __armv4_cache_on 510 - b __armv4_cache_off 511 - b __armv4_cache_flush 509 + b __armv4_mmu_cache_on 510 + b __armv4_mmu_cache_off 511 + b __armv4_mmu_cache_flush 512 512 513 513 .word 0x6901b110 @ sa1110 514 514 .word 0xfffffff0 515 - b __armv4_cache_on 516 - b __armv4_cache_off 517 - b __armv4_cache_flush 515 + b __armv4_mmu_cache_on 516 + b __armv4_mmu_cache_off 517 + b __armv4_mmu_cache_flush 518 518 519 519 @ These match on the architecture ID 520 520 521 521 .word 0x00020000 @ ARMv4T 522 522 .word 0x000f0000 523 - b __armv4_cache_on 524 - b __armv4_cache_off 525 - b __armv4_cache_flush 523 + b __armv4_mmu_cache_on 524 + b __armv4_mmu_cache_off 525 + b __armv4_mmu_cache_flush 526 526 527 527 .word 0x00050000 @ ARMv5TE 528 528 .word 0x000f0000 529 - b __armv4_cache_on 530 - b __armv4_cache_off 531 - b __armv4_cache_flush 529 + b __armv4_mmu_cache_on 530 + b __armv4_mmu_cache_off 531 + b __armv4_mmu_cache_flush 532 532 533 533 .word 0x00060000 @ ARMv5TEJ 534 534 .word 0x000f0000 535 - b __armv4_cache_on 536 - b __armv4_cache_off 537 - b __armv4_cache_flush 535 + b __armv4_mmu_cache_on 536 + b __armv4_mmu_cache_off 537 + b __armv4_mmu_cache_flush 538 538 539 539 .word 0x00070000 @ ARMv6 540 540 .word 0x000f0000 541 - b __armv4_cache_on 542 - b __armv4_cache_off 543 - b __armv6_cache_flush 541 + b __armv4_mmu_cache_on 542 + b __armv4_mmu_cache_off 543 + b __armv6_mmu_cache_flush 544 544 545 545 .word 0 @ unrecognised type 546 546 .word 0 ··· 562 562 cache_off: mov r3, #12 @ cache_off function 563 563 b call_cache_fn 564 564 565 - __armv4_cache_off: 565 + __armv4_mmu_cache_off: 566 566 mrc p15, 0, r0, c1, c0 567 567 bic r0, r0, #0x000d 568 568 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off ··· 571 571 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 572 572 mov pc, lr 573 573 574 - __arm6_cache_off: 574 + __arm6_mmu_cache_off: 575 575 mov r0, #0x00000030 @ ARM6 control reg. 576 - b __armv3_cache_off 576 + b __armv3_mmu_cache_off 577 577 578 - __arm7_cache_off: 578 + __arm7_mmu_cache_off: 579 579 mov r0, #0x00000070 @ ARM7 control reg. 580 - b __armv3_cache_off 580 + b __armv3_mmu_cache_off 581 581 582 - __armv3_cache_off: 582 + __armv3_mmu_cache_off: 583 583 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off 584 584 mov r0, #0 585 585 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 ··· 601 601 mov r3, #16 602 602 b call_cache_fn 603 603 604 - __armv6_cache_flush: 604 + __armv6_mmu_cache_flush: 605 605 mov r1, #0 606 606 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D 607 607 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB ··· 609 609 mcr p15, 0, r1, c7, c10, 4 @ drain WB 610 610 mov pc, lr 611 611 612 - __armv4_cache_flush: 612 + __armv4_mmu_cache_flush: 613 613 mov r2, #64*1024 @ default: 32K dcache size (*2) 614 614 mov r11, #32 @ default: 32 byte line size 615 615 mrc p15, 0, r3, c0, c0, 1 @ read cache type ··· 637 637 mcr p15, 0, r1, c7, c10, 4 @ drain WB 638 638 mov pc, lr 639 639 640 - __armv3_cache_flush: 640 + __armv3_mmu_cache_flush: 641 641 mov r1, #0 642 642 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 643 643 mov pc, lr