tjh.dev / kernel
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cxgb3 - Fix direct XAUI support

Check all lanes for link status on direct XAUI cards.
Don't assume that direct XAUI always uses XGMAC 1.

Signed-off-by: Divy Le Ray <divy@chelsio.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

authored by Divy Le Ray and committed by Jeff Garzik c706bfb5 890de332

+10 -2
unified split
+8 -2
drivers/net/cxgb3/ael1002.c
··· 219 219 unsigned int status; 220 220 221 221 status = t3_read_reg(phy->adapter, 222 - XGM_REG(A_XGM_SERDES_STAT0, phy->addr)); 222 + XGM_REG(A_XGM_SERDES_STAT0, phy->addr)) | 223 + t3_read_reg(phy->adapter, 224 + XGM_REG(A_XGM_SERDES_STAT1, phy->addr)) | 225 + t3_read_reg(phy->adapter, 226 + XGM_REG(A_XGM_SERDES_STAT2, phy->addr)) | 227 + t3_read_reg(phy->adapter, 228 + XGM_REG(A_XGM_SERDES_STAT3, phy->addr)); 223 229 *link_ok = !(status & F_LOWSIG0); 224 230 } 225 231 if (speed) ··· 253 247 void t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter, 254 248 int phy_addr, const struct mdio_ops *mdio_ops) 255 249 { 256 - cphy_init(phy, adapter, 1, &xaui_direct_ops, mdio_ops); 250 + cphy_init(phy, adapter, phy_addr, &xaui_direct_ops, mdio_ops); 257 251 }
+2
drivers/net/cxgb3/regs.h
··· 2128 2128 #define F_RESETPLL01 V_RESETPLL01(1U) 2129 2129 2130 2130 #define A_XGM_SERDES_STAT0 0x8f0 2131 + #define A_XGM_SERDES_STAT1 0x8f4 2132 + #define A_XGM_SERDES_STAT2 0x8f8 2131 2133 2132 2134 #define S_LOWSIG0 0 2133 2135 #define V_LOWSIG0(x) ((x) << S_LOWSIG0)