Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

e1000e: Out of line __ew32_prepare/__ew32

Out of lining these two common inlines saves about 30k text size,
due to their errata workarounds.

14131431 2008136 1507328 17646895 10d452f vmlinux-before-e1000e
14101415 2004040 1507328 17612783 10cbfef vmlinux-e1000e

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

authored by

Andi Kleen and committed by
Jeff Kirsher
c6f3148c 50844bb7

+32 -29
+2 -29
drivers/net/ethernet/intel/e1000e/e1000.h
··· 575 575 576 576 #define er32(reg) __er32(hw, E1000_##reg) 577 577 578 - /** 579 - * __ew32_prepare - prepare to write to MAC CSR register on certain parts 580 - * @hw: pointer to the HW structure 581 - * 582 - * When updating the MAC CSR registers, the Manageability Engine (ME) could 583 - * be accessing the registers at the same time. Normally, this is handled in 584 - * h/w by an arbiter but on some parts there is a bug that acknowledges Host 585 - * accesses later than it should which could result in the register to have 586 - * an incorrect value. Workaround this by checking the FWSM register which 587 - * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 588 - * and try again a number of times. 589 - **/ 590 - static inline s32 __ew32_prepare(struct e1000_hw *hw) 591 - { 592 - s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 593 - 594 - while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 595 - udelay(50); 596 - 597 - return i; 598 - } 599 - 600 - static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 601 - { 602 - if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 603 - __ew32_prepare(hw); 604 - 605 - writel(val, hw->hw_addr + reg); 606 - } 578 + s32 __ew32_prepare(struct e1000_hw *hw); 579 + void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val); 607 580 608 581 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) 609 582
+30
drivers/net/ethernet/intel/e1000e/netdev.c
··· 124 124 }; 125 125 126 126 /** 127 + * __ew32_prepare - prepare to write to MAC CSR register on certain parts 128 + * @hw: pointer to the HW structure 129 + * 130 + * When updating the MAC CSR registers, the Manageability Engine (ME) could 131 + * be accessing the registers at the same time. Normally, this is handled in 132 + * h/w by an arbiter but on some parts there is a bug that acknowledges Host 133 + * accesses later than it should which could result in the register to have 134 + * an incorrect value. Workaround this by checking the FWSM register which 135 + * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 136 + * and try again a number of times. 137 + **/ 138 + s32 __ew32_prepare(struct e1000_hw *hw) 139 + { 140 + s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 141 + 142 + while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 143 + udelay(50); 144 + 145 + return i; 146 + } 147 + 148 + void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 149 + { 150 + if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 151 + __ew32_prepare(hw); 152 + 153 + writel(val, hw->hw_addr + reg); 154 + } 155 + 156 + /** 127 157 * e1000_regdump - register printout routine 128 158 * @hw: pointer to the HW structure 129 159 * @reginfo: pointer to the register info table