tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: sunxi-ng: Add A31/A31s clocks
Add a new style driver for the clock control unit in Allwinner A31/A31s.
A few clocks are still missing:
- MIPI PLL's HDMI mode support
- EMAC clock
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
authored by
Chen-Yu Tsai
and committed by
Maxime Ripard
c6e6c96d
8adfb086
+1613
-1
+2
-1
Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+2
-1
Documentation/devicetree/bindings/clock/sunxi-ccu.txt
···
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2
------------------------------------
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Required properties :
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-
- compatible: must contain one of the following compatible:
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- compatible: must contain one of the following compatibles:
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- "allwinner,sun6i-a31-ccu"
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- "allwinner,sun8i-h3-ccu"
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- reg: Must contain the registers base address and length
+10
drivers/clk/sunxi-ng/Kconfig
+10
drivers/clk/sunxi-ng/Kconfig
···
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# SoC Drivers
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config SUN6I_A31_CCU
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bool "Support for the Allwinner A31/A31s CCU"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_NK
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select SUNXI_CCU_NKM
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select SUNXI_CCU_NM
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select SUNXI_CCU_MP
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select SUNXI_CCU_PHASE
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default MACH_SUN6I
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+
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config SUN8I_H3_CCU
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bool "Support for the Allwinner H3 CCU"
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select SUNXI_CCU_DIV
+1
drivers/clk/sunxi-ng/Makefile
+1
drivers/clk/sunxi-ng/Makefile
+1235
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+1235
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
···
1
+
/*
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+
* Copyright (c) 2016 Chen-Yu Tsai
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+
*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* Based on ccu-sun8i-h3.c by Maxime Ripard.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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+
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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+
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#include "ccu_common.h"
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+
#include "ccu_reset.h"
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+
24
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#include "ccu_div.h"
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+
#include "ccu_gate.h"
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+
#include "ccu_mp.h"
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+
#include "ccu_mult.h"
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+
#include "ccu_mux.h"
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#include "ccu_nk.h"
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#include "ccu_nkm.h"
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#include "ccu_nkmp.h"
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+
#include "ccu_nm.h"
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+
#include "ccu_phase.h"
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+
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#include "ccu-sun6i-a31.h"
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+
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static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
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"osc24M", 0x000,
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8, 5, /* N */
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4, 2, /* K */
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0, 2, /* M */
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BIT(31), /* gate */
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BIT(28), /* lock */
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0);
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+
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/*
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* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
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+
* the base (2x, 4x and 8x), and one variable divider (the one true
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* pll audio).
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*
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* We don't have any need for the variable divider for now, so we just
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* hardcode it to match with the clock names
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+
*/
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#define SUN6I_A31_PLL_AUDIO_REG 0x008
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+
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static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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"osc24M", 0x008,
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8, 7, /* N */
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0, 5, /* M */
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BIT(31), /* gate */
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+
BIT(28), /* lock */
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0);
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+
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
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"osc24M", 0x010,
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8, 7, /* N */
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+
0, 4, /* M */
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+
BIT(24), /* frac enable */
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+
BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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+
297000000, /* frac rate 1 */
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+
BIT(31), /* gate */
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+
BIT(28), /* lock */
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+
0);
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+
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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+
"osc24M", 0x018,
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+
8, 7, /* N */
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+
0, 4, /* M */
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+
BIT(24), /* frac enable */
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+
BIT(25), /* frac select */
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+
270000000, /* frac rate 0 */
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+
297000000, /* frac rate 1 */
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BIT(31), /* gate */
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+
BIT(28), /* lock */
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0);
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+
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static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
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"osc24M", 0x020,
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8, 5, /* N */
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+
4, 2, /* K */
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+
0, 2, /* M */
93
+
BIT(31), /* gate */
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+
BIT(28), /* lock */
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+
0);
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+
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+
static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
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+
"osc24M", 0x028,
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+
8, 5, /* N */
100
+
4, 2, /* K */
101
+
BIT(31), /* gate */
102
+
BIT(28), /* lock */
103
+
2, /* post-div */
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+
0);
105
+
106
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
107
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"osc24M", 0x030,
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+
8, 7, /* N */
109
+
0, 4, /* M */
110
+
BIT(24), /* frac enable */
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+
BIT(25), /* frac select */
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+
270000000, /* frac rate 0 */
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+
297000000, /* frac rate 1 */
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+
BIT(31), /* gate */
115
+
BIT(28), /* lock */
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+
0);
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+
118
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
119
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"osc24M", 0x038,
120
+
8, 7, /* N */
121
+
0, 4, /* M */
122
+
BIT(24), /* frac enable */
123
+
BIT(25), /* frac select */
124
+
270000000, /* frac rate 0 */
125
+
297000000, /* frac rate 1 */
126
+
BIT(31), /* gate */
127
+
BIT(28), /* lock */
128
+
0);
129
+
130
+
/*
131
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* The MIPI PLL has 2 modes: "MIPI" and "HDMI".
132
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*
133
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* The MIPI mode is a standard NKM-style clock. The HDMI mode is an
134
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* integer / fractional clock with switchable multipliers and dividers.
135
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* This is not supported here. We hardcode the PLL to MIPI mode.
136
+
*/
137
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#define SUN6I_A31_PLL_MIPI_REG 0x040
138
+
139
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static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" };
140
+
static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
141
+
pll_mipi_parents, 0x040,
142
+
8, 4, /* N */
143
+
4, 2, /* K */
144
+
0, 4, /* M */
145
+
21, 0, /* mux */
146
+
BIT(31), /* gate */
147
+
BIT(28), /* lock */
148
+
0);
149
+
150
+
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll9_clk, "pll9",
151
+
"osc24M", 0x044,
152
+
8, 7, /* N */
153
+
0, 4, /* M */
154
+
BIT(24), /* frac enable */
155
+
BIT(25), /* frac select */
156
+
270000000, /* frac rate 0 */
157
+
297000000, /* frac rate 1 */
158
+
BIT(31), /* gate */
159
+
BIT(28), /* lock */
160
+
0);
161
+
162
+
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll10_clk, "pll10",
163
+
"osc24M", 0x048,
164
+
8, 7, /* N */
165
+
0, 4, /* M */
166
+
BIT(24), /* frac enable */
167
+
BIT(25), /* frac select */
168
+
270000000, /* frac rate 0 */
169
+
297000000, /* frac rate 1 */
170
+
BIT(31), /* gate */
171
+
BIT(28), /* lock */
172
+
0);
173
+
174
+
static const char * const cpux_parents[] = { "osc32k", "osc24M",
175
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"pll-cpu", "pll-cpu" };
176
+
static SUNXI_CCU_MUX(cpu_clk, "cpu", cpux_parents,
177
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0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
178
+
179
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static struct clk_div_table axi_div_table[] = {
180
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{ .val = 0, .div = 1 },
181
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{ .val = 1, .div = 2 },
182
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{ .val = 2, .div = 3 },
183
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{ .val = 3, .div = 4 },
184
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{ .val = 4, .div = 4 },
185
+
{ .val = 5, .div = 4 },
186
+
{ .val = 6, .div = 4 },
187
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{ .val = 7, .div = 4 },
188
+
{ /* Sentinel */ },
189
+
};
190
+
191
+
static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
192
+
0x050, 0, 3, axi_div_table, 0);
193
+
194
+
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
195
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"axi", "pll-periph" };
196
+
197
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static struct ccu_div ahb1_clk = {
198
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.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
199
+
200
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.mux = {
201
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.shift = 12,
202
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.width = 2,
203
+
204
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.variable_prediv = {
205
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.index = 3,
206
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.shift = 6,
207
+
.width = 2,
208
+
},
209
+
},
210
+
211
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.common = {
212
+
.reg = 0x054,
213
+
.features = CCU_FEATURE_VARIABLE_PREDIV,
214
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.hw.init = CLK_HW_INIT_PARENTS("ahb1",
215
+
ahb1_parents,
216
+
&ccu_div_ops,
217
+
0),
218
+
},
219
+
};
220
+
221
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static struct clk_div_table apb1_div_table[] = {
222
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{ .val = 0, .div = 2 },
223
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{ .val = 1, .div = 2 },
224
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{ .val = 2, .div = 4 },
225
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{ .val = 3, .div = 8 },
226
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{ /* Sentinel */ },
227
+
};
228
+
229
+
static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
230
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0x054, 8, 2, apb1_div_table, 0);
231
+
232
+
static const char * const apb2_parents[] = { "osc32k", "osc24M",
233
+
"pll-periph", "pll-periph" };
234
+
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
235
+
0, 5, /* M */
236
+
16, 2, /* P */
237
+
24, 2, /* mux */
238
+
0);
239
+
240
+
static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
241
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0x060, BIT(1), 0);
242
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static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
243
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0x060, BIT(5), 0);
244
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static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
245
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0x060, BIT(6), 0);
246
+
static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
247
+
0x060, BIT(8), 0);
248
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static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
249
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0x060, BIT(9), 0);
250
+
static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
251
+
0x060, BIT(10), 0);
252
+
static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
253
+
0x060, BIT(12), 0);
254
+
static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
255
+
0x060, BIT(13), 0);
256
+
static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
257
+
0x060, BIT(13), 0);
258
+
static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
259
+
0x060, BIT(14), 0);
260
+
static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1",
261
+
0x060, BIT(17), 0);
262
+
static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1",
263
+
0x060, BIT(18), 0);
264
+
static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1",
265
+
0x060, BIT(19), 0);
266
+
static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1",
267
+
0x060, BIT(20), 0);
268
+
static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1",
269
+
0x060, BIT(21), 0);
270
+
static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1",
271
+
0x060, BIT(22), 0);
272
+
static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1",
273
+
0x060, BIT(23), 0);
274
+
static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1",
275
+
0x060, BIT(24), 0);
276
+
static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1",
277
+
0x060, BIT(26), 0);
278
+
static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1",
279
+
0x060, BIT(27), 0);
280
+
static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1",
281
+
0x060, BIT(29), 0);
282
+
static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1",
283
+
0x060, BIT(30), 0);
284
+
static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1",
285
+
0x060, BIT(31), 0);
286
+
287
+
static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1",
288
+
0x064, BIT(0), 0);
289
+
static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1",
290
+
0x064, BIT(4), 0);
291
+
static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1",
292
+
0x064, BIT(5), 0);
293
+
static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1",
294
+
0x064, BIT(8), 0);
295
+
static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1",
296
+
0x064, BIT(11), 0);
297
+
static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1",
298
+
0x064, BIT(12), 0);
299
+
static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1",
300
+
0x064, BIT(13), 0);
301
+
static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1",
302
+
0x064, BIT(14), 0);
303
+
static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1",
304
+
0x064, BIT(15), 0);
305
+
static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1",
306
+
0x064, BIT(18), 0);
307
+
static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1",
308
+
0x064, BIT(20), 0);
309
+
static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1",
310
+
0x064, BIT(23), 0);
311
+
static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1",
312
+
0x064, BIT(24), 0);
313
+
static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1",
314
+
0x064, BIT(25), 0);
315
+
static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1",
316
+
0x064, BIT(26), 0);
317
+
318
+
static SUNXI_CCU_GATE(apb1_codec_clk, "apb1-codec", "apb1",
319
+
0x068, BIT(0), 0);
320
+
static SUNXI_CCU_GATE(apb1_spdif_clk, "apb1-spdif", "apb1",
321
+
0x068, BIT(1), 0);
322
+
static SUNXI_CCU_GATE(apb1_digital_mic_clk, "apb1-digital-mic", "apb1",
323
+
0x068, BIT(4), 0);
324
+
static SUNXI_CCU_GATE(apb1_pio_clk, "apb1-pio", "apb1",
325
+
0x068, BIT(5), 0);
326
+
static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1",
327
+
0x068, BIT(12), 0);
328
+
static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1",
329
+
0x068, BIT(13), 0);
330
+
331
+
static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2",
332
+
0x06c, BIT(0), 0);
333
+
static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2",
334
+
0x06c, BIT(1), 0);
335
+
static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2",
336
+
0x06c, BIT(2), 0);
337
+
static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2",
338
+
0x06c, BIT(3), 0);
339
+
static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2",
340
+
0x06c, BIT(16), 0);
341
+
static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2",
342
+
0x06c, BIT(17), 0);
343
+
static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2",
344
+
0x06c, BIT(18), 0);
345
+
static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2",
346
+
0x06c, BIT(19), 0);
347
+
static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2",
348
+
0x06c, BIT(20), 0);
349
+
static SUNXI_CCU_GATE(apb2_uart5_clk, "apb2-uart5", "apb2",
350
+
0x06c, BIT(21), 0);
351
+
352
+
static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
353
+
static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", mod0_default_parents,
354
+
0x080,
355
+
0, 4, /* M */
356
+
16, 2, /* P */
357
+
24, 2, /* mux */
358
+
BIT(31), /* gate */
359
+
0);
360
+
361
+
static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", mod0_default_parents,
362
+
0x084,
363
+
0, 4, /* M */
364
+
16, 2, /* P */
365
+
24, 2, /* mux */
366
+
BIT(31), /* gate */
367
+
0);
368
+
369
+
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
370
+
0x088,
371
+
0, 4, /* M */
372
+
16, 2, /* P */
373
+
24, 2, /* mux */
374
+
BIT(31), /* gate */
375
+
0);
376
+
377
+
static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
378
+
0x088, 20, 3, 0);
379
+
static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
380
+
0x088, 8, 3, 0);
381
+
382
+
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
383
+
0x08c,
384
+
0, 4, /* M */
385
+
16, 2, /* P */
386
+
24, 2, /* mux */
387
+
BIT(31), /* gate */
388
+
0);
389
+
390
+
static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
391
+
0x08c, 20, 3, 0);
392
+
static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
393
+
0x08c, 8, 3, 0);
394
+
395
+
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
396
+
0x090,
397
+
0, 4, /* M */
398
+
16, 2, /* P */
399
+
24, 2, /* mux */
400
+
BIT(31), /* gate */
401
+
0);
402
+
403
+
static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
404
+
0x090, 20, 3, 0);
405
+
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
406
+
0x090, 8, 3, 0);
407
+
408
+
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents,
409
+
0x094,
410
+
0, 4, /* M */
411
+
16, 2, /* P */
412
+
24, 2, /* mux */
413
+
BIT(31), /* gate */
414
+
0);
415
+
416
+
static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
417
+
0x094, 20, 3, 0);
418
+
static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
419
+
0x094, 8, 3, 0);
420
+
421
+
static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
422
+
0, 4, /* M */
423
+
16, 2, /* P */
424
+
24, 2, /* mux */
425
+
BIT(31), /* gate */
426
+
0);
427
+
428
+
static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
429
+
0, 4, /* M */
430
+
16, 2, /* P */
431
+
24, 2, /* mux */
432
+
BIT(31), /* gate */
433
+
0);
434
+
435
+
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
436
+
0, 4, /* M */
437
+
16, 2, /* P */
438
+
24, 2, /* mux */
439
+
BIT(31), /* gate */
440
+
0);
441
+
442
+
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
443
+
0, 4, /* M */
444
+
16, 2, /* P */
445
+
24, 2, /* mux */
446
+
BIT(31), /* gate */
447
+
0);
448
+
static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
449
+
0, 4, /* M */
450
+
16, 2, /* P */
451
+
24, 2, /* mux */
452
+
BIT(31), /* gate */
453
+
0);
454
+
455
+
static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
456
+
0, 4, /* M */
457
+
16, 2, /* P */
458
+
24, 2, /* mux */
459
+
BIT(31), /* gate */
460
+
0);
461
+
462
+
static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x",
463
+
"pll-audio-2x", "pll-audio" };
464
+
static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents,
465
+
0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
466
+
static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents,
467
+
0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
468
+
469
+
static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
470
+
0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
471
+
472
+
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
473
+
0x0cc, BIT(8), 0);
474
+
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
475
+
0x0cc, BIT(9), 0);
476
+
static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
477
+
0x0cc, BIT(10), 0);
478
+
static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
479
+
0x0cc, BIT(16), 0);
480
+
static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
481
+
0x0cc, BIT(17), 0);
482
+
static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
483
+
0x0cc, BIT(18), 0);
484
+
485
+
/* TODO emac clk not supported yet */
486
+
487
+
static const char * const dram_parents[] = { "pll-ddr", "pll-periph" };
488
+
static SUNXI_CCU_MP_WITH_MUX_GATE(mdfs_clk, "mdfs", dram_parents, 0x0f0,
489
+
0, 4, /* M */
490
+
16, 2, /* P */
491
+
24, 2, /* mux */
492
+
BIT(31), /* gate */
493
+
CLK_IS_CRITICAL);
494
+
495
+
static SUNXI_CCU_M_WITH_MUX(sdram0_clk, "sdram0", dram_parents,
496
+
0x0f4, 0, 4, 4, 1, CLK_IS_CRITICAL);
497
+
static SUNXI_CCU_M_WITH_MUX(sdram1_clk, "sdram1", dram_parents,
498
+
0x0f4, 8, 4, 12, 1, CLK_IS_CRITICAL);
499
+
500
+
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "mdfs",
501
+
0x100, BIT(0), 0);
502
+
static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs",
503
+
0x100, BIT(1), 0);
504
+
static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "mdfs",
505
+
0x100, BIT(3), 0);
506
+
static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "mdfs",
507
+
0x100, BIT(16), 0);
508
+
static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "mdfs",
509
+
0x100, BIT(17), 0);
510
+
static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "mdfs",
511
+
0x100, BIT(18), 0);
512
+
static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "mdfs",
513
+
0x100, BIT(19), 0);
514
+
static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "mdfs",
515
+
0x100, BIT(24), 0);
516
+
static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "mdfs",
517
+
0x100, BIT(25), 0);
518
+
static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "mdfs",
519
+
0x100, BIT(26), 0);
520
+
static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "mdfs",
521
+
0x100, BIT(27), 0);
522
+
static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "mdfs",
523
+
0x100, BIT(28), 0);
524
+
525
+
static const char * const de_parents[] = { "pll-video0", "pll-video1",
526
+
"pll-periph-2x", "pll-gpu",
527
+
"pll9", "pll10" };
528
+
static SUNXI_CCU_M_WITH_MUX_GATE(be0_clk, "be0", de_parents,
529
+
0x104, 0, 4, 24, 3, BIT(31), 0);
530
+
static SUNXI_CCU_M_WITH_MUX_GATE(be1_clk, "be1", de_parents,
531
+
0x108, 0, 4, 24, 3, BIT(31), 0);
532
+
static SUNXI_CCU_M_WITH_MUX_GATE(fe0_clk, "fe0", de_parents,
533
+
0x10c, 0, 4, 24, 3, BIT(31), 0);
534
+
static SUNXI_CCU_M_WITH_MUX_GATE(fe1_clk, "fe1", de_parents,
535
+
0x110, 0, 4, 24, 3, BIT(31), 0);
536
+
537
+
static const char * const mp_parents[] = { "pll-video0", "pll-video1",
538
+
"pll9", "pll10" };
539
+
static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", mp_parents,
540
+
0x114, 0, 4, 24, 3, BIT(31), 0);
541
+
542
+
static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1",
543
+
"pll-video0-2x",
544
+
"pll-video1-2x", "pll-mipi" };
545
+
static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents,
546
+
0x118, 24, 2, BIT(31), 0);
547
+
static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents,
548
+
0x11c, 24, 2, BIT(31), 0);
549
+
550
+
static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1",
551
+
"pll-video0-2x",
552
+
"pll-video1-2x" };
553
+
static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
554
+
0x12c, 0, 4, 24, 3, BIT(31), 0);
555
+
static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
556
+
0x12c, 0, 4, 24, 3, BIT(31), 0);
557
+
558
+
static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
559
+
"pll9", "pll10", "pll-mipi",
560
+
"pll-ve" };
561
+
static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents,
562
+
0x134, 16, 4, 24, 3, BIT(31), 0);
563
+
564
+
static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1",
565
+
"osc24M" };
566
+
static const u8 csi_mclk_table[] = { 0, 1, 5 };
567
+
static struct ccu_div csi0_mclk_clk = {
568
+
.enable = BIT(15),
569
+
.div = _SUNXI_CCU_DIV(0, 4),
570
+
.mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
571
+
.common = {
572
+
.reg = 0x134,
573
+
.hw.init = CLK_HW_INIT_PARENTS("csi0-mclk",
574
+
csi_mclk_parents,
575
+
&ccu_div_ops,
576
+
0),
577
+
},
578
+
};
579
+
580
+
static struct ccu_div csi1_mclk_clk = {
581
+
.enable = BIT(15),
582
+
.div = _SUNXI_CCU_DIV(0, 4),
583
+
.mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
584
+
.common = {
585
+
.reg = 0x138,
586
+
.hw.init = CLK_HW_INIT_PARENTS("csi1-mclk",
587
+
csi_mclk_parents,
588
+
&ccu_div_ops,
589
+
0),
590
+
},
591
+
};
592
+
593
+
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
594
+
0x13c, 16, 3, BIT(31), 0);
595
+
596
+
static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
597
+
0x140, BIT(31), CLK_SET_RATE_PARENT);
598
+
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
599
+
0x144, BIT(31), 0);
600
+
static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio",
601
+
0x148, BIT(31), CLK_SET_RATE_PARENT);
602
+
603
+
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents,
604
+
0x150, 0, 4, 24, 2, BIT(31), 0);
605
+
606
+
static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(31), 0);
607
+
608
+
static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
609
+
610
+
static const char * const mbus_parents[] = { "osc24M", "pll-periph",
611
+
"pll-ddr" };
612
+
static SUNXI_CCU_MP_WITH_MUX_GATE(mbus0_clk, "mbus0", mbus_parents, 0x15c,
613
+
0, 3, /* M */
614
+
16, 2, /* P */
615
+
24, 2, /* mux */
616
+
BIT(31), /* gate */
617
+
CLK_IS_CRITICAL);
618
+
619
+
static SUNXI_CCU_MP_WITH_MUX_GATE(mbus1_clk, "mbus1", mbus_parents, 0x160,
620
+
0, 3, /* M */
621
+
16, 2, /* P */
622
+
24, 2, /* mux */
623
+
BIT(31), /* gate */
624
+
CLK_IS_CRITICAL);
625
+
626
+
static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents,
627
+
0x168, 16, 3, 24, 2, BIT(31), 0);
628
+
static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy",
629
+
lcd_ch1_parents, 0x168, 0, 3, 8, 2,
630
+
BIT(15), 0);
631
+
static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy",
632
+
lcd_ch1_parents, 0x168, 0, 3, 8, 2,
633
+
BIT(15), 0);
634
+
635
+
static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents,
636
+
0x180, 0, 3, 24, 2, BIT(31), 0);
637
+
static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents,
638
+
0x184, 0, 3, 24, 2, BIT(31), 0);
639
+
static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents,
640
+
0x188, 0, 3, 24, 2, BIT(31), 0);
641
+
static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents,
642
+
0x18c, 0, 3, 24, 2, BIT(31), 0);
643
+
644
+
static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x",
645
+
"pll-video0", "pll-video1",
646
+
"pll9", "pll10" };
647
+
static const struct ccu_mux_fixed_prediv gpu_predivs[] = {
648
+
{ .index = 1, .div = 3, },
649
+
};
650
+
651
+
static struct ccu_div gpu_core_clk = {
652
+
.enable = BIT(31),
653
+
.div = _SUNXI_CCU_DIV(0, 3),
654
+
.mux = {
655
+
.shift = 24,
656
+
.width = 3,
657
+
.fixed_predivs = gpu_predivs,
658
+
.n_predivs = ARRAY_SIZE(gpu_predivs),
659
+
},
660
+
.common = {
661
+
.reg = 0x1a0,
662
+
.features = CCU_FEATURE_FIXED_PREDIV,
663
+
.hw.init = CLK_HW_INIT_PARENTS("gpu-core",
664
+
gpu_parents,
665
+
&ccu_div_ops,
666
+
0),
667
+
},
668
+
};
669
+
670
+
static struct ccu_div gpu_memory_clk = {
671
+
.enable = BIT(31),
672
+
.div = _SUNXI_CCU_DIV(0, 3),
673
+
.mux = {
674
+
.shift = 24,
675
+
.width = 3,
676
+
.fixed_predivs = gpu_predivs,
677
+
.n_predivs = ARRAY_SIZE(gpu_predivs),
678
+
},
679
+
.common = {
680
+
.reg = 0x1a4,
681
+
.features = CCU_FEATURE_FIXED_PREDIV,
682
+
.hw.init = CLK_HW_INIT_PARENTS("gpu-memory",
683
+
gpu_parents,
684
+
&ccu_div_ops,
685
+
0),
686
+
},
687
+
};
688
+
689
+
static struct ccu_div gpu_hyd_clk = {
690
+
.enable = BIT(31),
691
+
.div = _SUNXI_CCU_DIV(0, 3),
692
+
.mux = {
693
+
.shift = 24,
694
+
.width = 3,
695
+
.fixed_predivs = gpu_predivs,
696
+
.n_predivs = ARRAY_SIZE(gpu_predivs),
697
+
},
698
+
.common = {
699
+
.reg = 0x1a8,
700
+
.features = CCU_FEATURE_FIXED_PREDIV,
701
+
.hw.init = CLK_HW_INIT_PARENTS("gpu-hyd",
702
+
gpu_parents,
703
+
&ccu_div_ops,
704
+
0),
705
+
},
706
+
};
707
+
708
+
static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", mod0_default_parents, 0x1b0,
709
+
0, 3, /* M */
710
+
24, 2, /* mux */
711
+
BIT(31), /* gate */
712
+
0);
713
+
714
+
static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", mod0_default_parents,
715
+
0x1b0,
716
+
0, 3, /* M */
717
+
24, 2, /* mux */
718
+
BIT(31), /* gate */
719
+
0);
720
+
721
+
static const char * const clk_out_parents[] = { "osc24M", "osc32k", "osc24M",
722
+
"axi", "ahb1" };
723
+
static const u8 clk_out_table[] = { 0, 1, 2, 11, 13 };
724
+
725
+
static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
726
+
{ .index = 0, .div = 750, },
727
+
{ .index = 3, .div = 4, },
728
+
{ .index = 4, .div = 4, },
729
+
};
730
+
731
+
static struct ccu_mp out_a_clk = {
732
+
.enable = BIT(31),
733
+
.m = _SUNXI_CCU_DIV(8, 5),
734
+
.p = _SUNXI_CCU_DIV(20, 2),
735
+
.mux = {
736
+
.shift = 24,
737
+
.width = 4,
738
+
.table = clk_out_table,
739
+
.fixed_predivs = clk_out_predivs,
740
+
.n_predivs = ARRAY_SIZE(clk_out_predivs),
741
+
},
742
+
.common = {
743
+
.reg = 0x300,
744
+
.features = CCU_FEATURE_FIXED_PREDIV,
745
+
.hw.init = CLK_HW_INIT_PARENTS("out-a",
746
+
clk_out_parents,
747
+
&ccu_div_ops,
748
+
0),
749
+
},
750
+
};
751
+
752
+
static struct ccu_mp out_b_clk = {
753
+
.enable = BIT(31),
754
+
.m = _SUNXI_CCU_DIV(8, 5),
755
+
.p = _SUNXI_CCU_DIV(20, 2),
756
+
.mux = {
757
+
.shift = 24,
758
+
.width = 4,
759
+
.table = clk_out_table,
760
+
.fixed_predivs = clk_out_predivs,
761
+
.n_predivs = ARRAY_SIZE(clk_out_predivs),
762
+
},
763
+
.common = {
764
+
.reg = 0x304,
765
+
.features = CCU_FEATURE_FIXED_PREDIV,
766
+
.hw.init = CLK_HW_INIT_PARENTS("out-b",
767
+
clk_out_parents,
768
+
&ccu_div_ops,
769
+
0),
770
+
},
771
+
};
772
+
773
+
static struct ccu_mp out_c_clk = {
774
+
.enable = BIT(31),
775
+
.m = _SUNXI_CCU_DIV(8, 5),
776
+
.p = _SUNXI_CCU_DIV(20, 2),
777
+
.mux = {
778
+
.shift = 24,
779
+
.width = 4,
780
+
.table = clk_out_table,
781
+
.fixed_predivs = clk_out_predivs,
782
+
.n_predivs = ARRAY_SIZE(clk_out_predivs),
783
+
},
784
+
.common = {
785
+
.reg = 0x308,
786
+
.features = CCU_FEATURE_FIXED_PREDIV,
787
+
.hw.init = CLK_HW_INIT_PARENTS("out-c",
788
+
clk_out_parents,
789
+
&ccu_div_ops,
790
+
0),
791
+
},
792
+
};
793
+
794
+
static struct ccu_common *sun6i_a31_ccu_clks[] = {
795
+
&pll_cpu_clk.common,
796
+
&pll_audio_base_clk.common,
797
+
&pll_video0_clk.common,
798
+
&pll_ve_clk.common,
799
+
&pll_ddr_clk.common,
800
+
&pll_periph_clk.common,
801
+
&pll_video1_clk.common,
802
+
&pll_gpu_clk.common,
803
+
&pll_mipi_clk.common,
804
+
&pll9_clk.common,
805
+
&pll10_clk.common,
806
+
&cpu_clk.common,
807
+
&axi_clk.common,
808
+
&ahb1_clk.common,
809
+
&apb1_clk.common,
810
+
&apb2_clk.common,
811
+
&ahb1_mipidsi_clk.common,
812
+
&ahb1_ss_clk.common,
813
+
&ahb1_dma_clk.common,
814
+
&ahb1_mmc0_clk.common,
815
+
&ahb1_mmc1_clk.common,
816
+
&ahb1_mmc2_clk.common,
817
+
&ahb1_mmc3_clk.common,
818
+
&ahb1_nand1_clk.common,
819
+
&ahb1_nand0_clk.common,
820
+
&ahb1_sdram_clk.common,
821
+
&ahb1_emac_clk.common,
822
+
&ahb1_ts_clk.common,
823
+
&ahb1_hstimer_clk.common,
824
+
&ahb1_spi0_clk.common,
825
+
&ahb1_spi1_clk.common,
826
+
&ahb1_spi2_clk.common,
827
+
&ahb1_spi3_clk.common,
828
+
&ahb1_otg_clk.common,
829
+
&ahb1_ehci0_clk.common,
830
+
&ahb1_ehci1_clk.common,
831
+
&ahb1_ohci0_clk.common,
832
+
&ahb1_ohci1_clk.common,
833
+
&ahb1_ohci2_clk.common,
834
+
&ahb1_ve_clk.common,
835
+
&ahb1_lcd0_clk.common,
836
+
&ahb1_lcd1_clk.common,
837
+
&ahb1_csi_clk.common,
838
+
&ahb1_hdmi_clk.common,
839
+
&ahb1_be0_clk.common,
840
+
&ahb1_be1_clk.common,
841
+
&ahb1_fe0_clk.common,
842
+
&ahb1_fe1_clk.common,
843
+
&ahb1_mp_clk.common,
844
+
&ahb1_gpu_clk.common,
845
+
&ahb1_deu0_clk.common,
846
+
&ahb1_deu1_clk.common,
847
+
&ahb1_drc0_clk.common,
848
+
&ahb1_drc1_clk.common,
849
+
&apb1_codec_clk.common,
850
+
&apb1_spdif_clk.common,
851
+
&apb1_digital_mic_clk.common,
852
+
&apb1_pio_clk.common,
853
+
&apb1_daudio0_clk.common,
854
+
&apb1_daudio1_clk.common,
855
+
&apb2_i2c0_clk.common,
856
+
&apb2_i2c1_clk.common,
857
+
&apb2_i2c2_clk.common,
858
+
&apb2_i2c3_clk.common,
859
+
&apb2_uart0_clk.common,
860
+
&apb2_uart1_clk.common,
861
+
&apb2_uart2_clk.common,
862
+
&apb2_uart3_clk.common,
863
+
&apb2_uart4_clk.common,
864
+
&apb2_uart5_clk.common,
865
+
&nand0_clk.common,
866
+
&nand1_clk.common,
867
+
&mmc0_clk.common,
868
+
&mmc0_sample_clk.common,
869
+
&mmc0_output_clk.common,
870
+
&mmc1_clk.common,
871
+
&mmc1_sample_clk.common,
872
+
&mmc1_output_clk.common,
873
+
&mmc2_clk.common,
874
+
&mmc2_sample_clk.common,
875
+
&mmc2_output_clk.common,
876
+
&mmc3_clk.common,
877
+
&mmc3_sample_clk.common,
878
+
&mmc3_output_clk.common,
879
+
&ts_clk.common,
880
+
&ss_clk.common,
881
+
&spi0_clk.common,
882
+
&spi1_clk.common,
883
+
&spi2_clk.common,
884
+
&spi3_clk.common,
885
+
&daudio0_clk.common,
886
+
&daudio1_clk.common,
887
+
&spdif_clk.common,
888
+
&usb_phy0_clk.common,
889
+
&usb_phy1_clk.common,
890
+
&usb_phy2_clk.common,
891
+
&usb_ohci0_clk.common,
892
+
&usb_ohci1_clk.common,
893
+
&usb_ohci2_clk.common,
894
+
&mdfs_clk.common,
895
+
&sdram0_clk.common,
896
+
&sdram1_clk.common,
897
+
&dram_ve_clk.common,
898
+
&dram_csi_isp_clk.common,
899
+
&dram_ts_clk.common,
900
+
&dram_drc0_clk.common,
901
+
&dram_drc1_clk.common,
902
+
&dram_deu0_clk.common,
903
+
&dram_deu1_clk.common,
904
+
&dram_fe0_clk.common,
905
+
&dram_fe1_clk.common,
906
+
&dram_be0_clk.common,
907
+
&dram_be1_clk.common,
908
+
&dram_mp_clk.common,
909
+
&be0_clk.common,
910
+
&be1_clk.common,
911
+
&fe0_clk.common,
912
+
&fe1_clk.common,
913
+
&mp_clk.common,
914
+
&lcd0_ch0_clk.common,
915
+
&lcd1_ch0_clk.common,
916
+
&lcd0_ch1_clk.common,
917
+
&lcd1_ch1_clk.common,
918
+
&csi0_sclk_clk.common,
919
+
&csi0_mclk_clk.common,
920
+
&csi1_mclk_clk.common,
921
+
&ve_clk.common,
922
+
&codec_clk.common,
923
+
&avs_clk.common,
924
+
&digital_mic_clk.common,
925
+
&hdmi_clk.common,
926
+
&hdmi_ddc_clk.common,
927
+
&ps_clk.common,
928
+
&mbus0_clk.common,
929
+
&mbus1_clk.common,
930
+
&mipi_dsi_clk.common,
931
+
&mipi_dsi_dphy_clk.common,
932
+
&mipi_csi_dphy_clk.common,
933
+
&iep_drc0_clk.common,
934
+
&iep_drc1_clk.common,
935
+
&iep_deu0_clk.common,
936
+
&iep_deu1_clk.common,
937
+
&gpu_core_clk.common,
938
+
&gpu_memory_clk.common,
939
+
&gpu_hyd_clk.common,
940
+
&ats_clk.common,
941
+
&trace_clk.common,
942
+
&out_a_clk.common,
943
+
&out_b_clk.common,
944
+
&out_c_clk.common,
945
+
};
946
+
947
+
/* We hardcode the divider to 4 for now */
948
+
static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
949
+
"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
950
+
static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
951
+
"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
952
+
static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
953
+
"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
954
+
static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
955
+
"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
956
+
static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
957
+
"pll-periph", 1, 2, 0);
958
+
static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
959
+
"pll-video0", 1, 2, 0);
960
+
static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
961
+
"pll-video1", 1, 2, 0);
962
+
963
+
static struct clk_hw_onecell_data sun6i_a31_hw_clks = {
964
+
.hws = {
965
+
[CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
966
+
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
967
+
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
968
+
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
969
+
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
970
+
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
971
+
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
972
+
[CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
973
+
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
974
+
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
975
+
[CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
976
+
[CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
977
+
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
978
+
[CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
979
+
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
980
+
[CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
981
+
[CLK_PLL9] = &pll9_clk.common.hw,
982
+
[CLK_PLL10] = &pll10_clk.common.hw,
983
+
[CLK_CPU] = &cpu_clk.common.hw,
984
+
[CLK_AXI] = &axi_clk.common.hw,
985
+
[CLK_AHB1] = &ahb1_clk.common.hw,
986
+
[CLK_APB1] = &apb1_clk.common.hw,
987
+
[CLK_APB2] = &apb2_clk.common.hw,
988
+
[CLK_AHB1_MIPIDSI] = &ahb1_mipidsi_clk.common.hw,
989
+
[CLK_AHB1_SS] = &ahb1_ss_clk.common.hw,
990
+
[CLK_AHB1_DMA] = &ahb1_dma_clk.common.hw,
991
+
[CLK_AHB1_MMC0] = &ahb1_mmc0_clk.common.hw,
992
+
[CLK_AHB1_MMC1] = &ahb1_mmc1_clk.common.hw,
993
+
[CLK_AHB1_MMC2] = &ahb1_mmc2_clk.common.hw,
994
+
[CLK_AHB1_MMC3] = &ahb1_mmc3_clk.common.hw,
995
+
[CLK_AHB1_NAND1] = &ahb1_nand1_clk.common.hw,
996
+
[CLK_AHB1_NAND0] = &ahb1_nand0_clk.common.hw,
997
+
[CLK_AHB1_SDRAM] = &ahb1_sdram_clk.common.hw,
998
+
[CLK_AHB1_EMAC] = &ahb1_emac_clk.common.hw,
999
+
[CLK_AHB1_TS] = &ahb1_ts_clk.common.hw,
1000
+
[CLK_AHB1_HSTIMER] = &ahb1_hstimer_clk.common.hw,
1001
+
[CLK_AHB1_SPI0] = &ahb1_spi0_clk.common.hw,
1002
+
[CLK_AHB1_SPI1] = &ahb1_spi1_clk.common.hw,
1003
+
[CLK_AHB1_SPI2] = &ahb1_spi2_clk.common.hw,
1004
+
[CLK_AHB1_SPI3] = &ahb1_spi3_clk.common.hw,
1005
+
[CLK_AHB1_OTG] = &ahb1_otg_clk.common.hw,
1006
+
[CLK_AHB1_EHCI0] = &ahb1_ehci0_clk.common.hw,
1007
+
[CLK_AHB1_EHCI1] = &ahb1_ehci1_clk.common.hw,
1008
+
[CLK_AHB1_OHCI0] = &ahb1_ohci0_clk.common.hw,
1009
+
[CLK_AHB1_OHCI1] = &ahb1_ohci1_clk.common.hw,
1010
+
[CLK_AHB1_OHCI2] = &ahb1_ohci2_clk.common.hw,
1011
+
[CLK_AHB1_VE] = &ahb1_ve_clk.common.hw,
1012
+
[CLK_AHB1_LCD0] = &ahb1_lcd0_clk.common.hw,
1013
+
[CLK_AHB1_LCD1] = &ahb1_lcd1_clk.common.hw,
1014
+
[CLK_AHB1_CSI] = &ahb1_csi_clk.common.hw,
1015
+
[CLK_AHB1_HDMI] = &ahb1_hdmi_clk.common.hw,
1016
+
[CLK_AHB1_BE0] = &ahb1_be0_clk.common.hw,
1017
+
[CLK_AHB1_BE1] = &ahb1_be1_clk.common.hw,
1018
+
[CLK_AHB1_FE0] = &ahb1_fe0_clk.common.hw,
1019
+
[CLK_AHB1_FE1] = &ahb1_fe1_clk.common.hw,
1020
+
[CLK_AHB1_MP] = &ahb1_mp_clk.common.hw,
1021
+
[CLK_AHB1_GPU] = &ahb1_gpu_clk.common.hw,
1022
+
[CLK_AHB1_DEU0] = &ahb1_deu0_clk.common.hw,
1023
+
[CLK_AHB1_DEU1] = &ahb1_deu1_clk.common.hw,
1024
+
[CLK_AHB1_DRC0] = &ahb1_drc0_clk.common.hw,
1025
+
[CLK_AHB1_DRC1] = &ahb1_drc1_clk.common.hw,
1026
+
[CLK_APB1_CODEC] = &apb1_codec_clk.common.hw,
1027
+
[CLK_APB1_SPDIF] = &apb1_spdif_clk.common.hw,
1028
+
[CLK_APB1_DIGITAL_MIC] = &apb1_digital_mic_clk.common.hw,
1029
+
[CLK_APB1_PIO] = &apb1_pio_clk.common.hw,
1030
+
[CLK_APB1_DAUDIO0] = &apb1_daudio0_clk.common.hw,
1031
+
[CLK_APB1_DAUDIO1] = &apb1_daudio1_clk.common.hw,
1032
+
[CLK_APB2_I2C0] = &apb2_i2c0_clk.common.hw,
1033
+
[CLK_APB2_I2C1] = &apb2_i2c1_clk.common.hw,
1034
+
[CLK_APB2_I2C2] = &apb2_i2c2_clk.common.hw,
1035
+
[CLK_APB2_I2C3] = &apb2_i2c3_clk.common.hw,
1036
+
[CLK_APB2_UART0] = &apb2_uart0_clk.common.hw,
1037
+
[CLK_APB2_UART1] = &apb2_uart1_clk.common.hw,
1038
+
[CLK_APB2_UART2] = &apb2_uart2_clk.common.hw,
1039
+
[CLK_APB2_UART3] = &apb2_uart3_clk.common.hw,
1040
+
[CLK_APB2_UART4] = &apb2_uart4_clk.common.hw,
1041
+
[CLK_APB2_UART5] = &apb2_uart5_clk.common.hw,
1042
+
[CLK_NAND0] = &nand0_clk.common.hw,
1043
+
[CLK_NAND1] = &nand1_clk.common.hw,
1044
+
[CLK_MMC0] = &mmc0_clk.common.hw,
1045
+
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
1046
+
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
1047
+
[CLK_MMC1] = &mmc1_clk.common.hw,
1048
+
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
1049
+
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
1050
+
[CLK_MMC2] = &mmc2_clk.common.hw,
1051
+
[CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
1052
+
[CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
1053
+
[CLK_MMC3] = &mmc3_clk.common.hw,
1054
+
[CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,
1055
+
[CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,
1056
+
[CLK_TS] = &ts_clk.common.hw,
1057
+
[CLK_SS] = &ss_clk.common.hw,
1058
+
[CLK_SPI0] = &spi0_clk.common.hw,
1059
+
[CLK_SPI1] = &spi1_clk.common.hw,
1060
+
[CLK_SPI2] = &spi2_clk.common.hw,
1061
+
[CLK_SPI3] = &spi3_clk.common.hw,
1062
+
[CLK_DAUDIO0] = &daudio0_clk.common.hw,
1063
+
[CLK_DAUDIO1] = &daudio1_clk.common.hw,
1064
+
[CLK_SPDIF] = &spdif_clk.common.hw,
1065
+
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
1066
+
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
1067
+
[CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
1068
+
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1069
+
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1070
+
[CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
1071
+
[CLK_MDFS] = &mdfs_clk.common.hw,
1072
+
[CLK_SDRAM0] = &sdram0_clk.common.hw,
1073
+
[CLK_SDRAM1] = &sdram1_clk.common.hw,
1074
+
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
1075
+
[CLK_DRAM_CSI_ISP] = &dram_csi_isp_clk.common.hw,
1076
+
[CLK_DRAM_TS] = &dram_ts_clk.common.hw,
1077
+
[CLK_DRAM_DRC0] = &dram_drc0_clk.common.hw,
1078
+
[CLK_DRAM_DRC1] = &dram_drc1_clk.common.hw,
1079
+
[CLK_DRAM_DEU0] = &dram_deu0_clk.common.hw,
1080
+
[CLK_DRAM_DEU1] = &dram_deu1_clk.common.hw,
1081
+
[CLK_DRAM_FE0] = &dram_fe0_clk.common.hw,
1082
+
[CLK_DRAM_FE1] = &dram_fe1_clk.common.hw,
1083
+
[CLK_DRAM_BE0] = &dram_be0_clk.common.hw,
1084
+
[CLK_DRAM_BE1] = &dram_be1_clk.common.hw,
1085
+
[CLK_DRAM_MP] = &dram_mp_clk.common.hw,
1086
+
[CLK_BE0] = &be0_clk.common.hw,
1087
+
[CLK_BE1] = &be1_clk.common.hw,
1088
+
[CLK_FE0] = &fe0_clk.common.hw,
1089
+
[CLK_FE1] = &fe1_clk.common.hw,
1090
+
[CLK_MP] = &mp_clk.common.hw,
1091
+
[CLK_LCD0_CH0] = &lcd0_ch0_clk.common.hw,
1092
+
[CLK_LCD1_CH0] = &lcd1_ch0_clk.common.hw,
1093
+
[CLK_LCD0_CH1] = &lcd0_ch1_clk.common.hw,
1094
+
[CLK_LCD1_CH1] = &lcd1_ch1_clk.common.hw,
1095
+
[CLK_CSI0_SCLK] = &csi0_sclk_clk.common.hw,
1096
+
[CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
1097
+
[CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
1098
+
[CLK_VE] = &ve_clk.common.hw,
1099
+
[CLK_CODEC] = &codec_clk.common.hw,
1100
+
[CLK_AVS] = &avs_clk.common.hw,
1101
+
[CLK_DIGITAL_MIC] = &digital_mic_clk.common.hw,
1102
+
[CLK_HDMI] = &hdmi_clk.common.hw,
1103
+
[CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
1104
+
[CLK_PS] = &ps_clk.common.hw,
1105
+
[CLK_MBUS0] = &mbus0_clk.common.hw,
1106
+
[CLK_MBUS1] = &mbus1_clk.common.hw,
1107
+
[CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
1108
+
[CLK_MIPI_DSI_DPHY] = &mipi_dsi_dphy_clk.common.hw,
1109
+
[CLK_MIPI_CSI_DPHY] = &mipi_csi_dphy_clk.common.hw,
1110
+
[CLK_IEP_DRC0] = &iep_drc0_clk.common.hw,
1111
+
[CLK_IEP_DRC1] = &iep_drc1_clk.common.hw,
1112
+
[CLK_IEP_DEU0] = &iep_deu0_clk.common.hw,
1113
+
[CLK_IEP_DEU1] = &iep_deu1_clk.common.hw,
1114
+
[CLK_GPU_CORE] = &gpu_core_clk.common.hw,
1115
+
[CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw,
1116
+
[CLK_GPU_HYD] = &gpu_hyd_clk.common.hw,
1117
+
[CLK_ATS] = &ats_clk.common.hw,
1118
+
[CLK_TRACE] = &trace_clk.common.hw,
1119
+
[CLK_OUT_A] = &out_a_clk.common.hw,
1120
+
[CLK_OUT_B] = &out_b_clk.common.hw,
1121
+
[CLK_OUT_C] = &out_c_clk.common.hw,
1122
+
},
1123
+
.num = CLK_NUMBER,
1124
+
};
1125
+
1126
+
static struct ccu_reset_map sun6i_a31_ccu_resets[] = {
1127
+
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
1128
+
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
1129
+
[RST_USB_PHY2] = { 0x0cc, BIT(2) },
1130
+
1131
+
[RST_AHB1_MIPI_DSI] = { 0x2c0, BIT(1) },
1132
+
[RST_AHB1_SS] = { 0x2c0, BIT(5) },
1133
+
[RST_AHB1_DMA] = { 0x2c0, BIT(6) },
1134
+
[RST_AHB1_MMC0] = { 0x2c0, BIT(8) },
1135
+
[RST_AHB1_MMC1] = { 0x2c0, BIT(9) },
1136
+
[RST_AHB1_MMC2] = { 0x2c0, BIT(10) },
1137
+
[RST_AHB1_MMC3] = { 0x2c0, BIT(11) },
1138
+
[RST_AHB1_NAND1] = { 0x2c0, BIT(12) },
1139
+
[RST_AHB1_NAND0] = { 0x2c0, BIT(13) },
1140
+
[RST_AHB1_SDRAM] = { 0x2c0, BIT(14) },
1141
+
[RST_AHB1_EMAC] = { 0x2c0, BIT(17) },
1142
+
[RST_AHB1_TS] = { 0x2c0, BIT(18) },
1143
+
[RST_AHB1_HSTIMER] = { 0x2c0, BIT(19) },
1144
+
[RST_AHB1_SPI0] = { 0x2c0, BIT(20) },
1145
+
[RST_AHB1_SPI1] = { 0x2c0, BIT(21) },
1146
+
[RST_AHB1_SPI2] = { 0x2c0, BIT(22) },
1147
+
[RST_AHB1_SPI3] = { 0x2c0, BIT(23) },
1148
+
[RST_AHB1_OTG] = { 0x2c0, BIT(24) },
1149
+
[RST_AHB1_EHCI0] = { 0x2c0, BIT(26) },
1150
+
[RST_AHB1_EHCI1] = { 0x2c0, BIT(27) },
1151
+
[RST_AHB1_OHCI0] = { 0x2c0, BIT(29) },
1152
+
[RST_AHB1_OHCI1] = { 0x2c0, BIT(30) },
1153
+
[RST_AHB1_OHCI2] = { 0x2c0, BIT(31) },
1154
+
1155
+
[RST_AHB1_VE] = { 0x2c4, BIT(0) },
1156
+
[RST_AHB1_LCD0] = { 0x2c4, BIT(4) },
1157
+
[RST_AHB1_LCD1] = { 0x2c4, BIT(5) },
1158
+
[RST_AHB1_CSI] = { 0x2c4, BIT(8) },
1159
+
[RST_AHB1_HDMI] = { 0x2c4, BIT(11) },
1160
+
[RST_AHB1_BE0] = { 0x2c4, BIT(12) },
1161
+
[RST_AHB1_BE1] = { 0x2c4, BIT(13) },
1162
+
[RST_AHB1_FE0] = { 0x2c4, BIT(14) },
1163
+
[RST_AHB1_FE1] = { 0x2c4, BIT(15) },
1164
+
[RST_AHB1_MP] = { 0x2c4, BIT(18) },
1165
+
[RST_AHB1_GPU] = { 0x2c4, BIT(20) },
1166
+
[RST_AHB1_DEU0] = { 0x2c4, BIT(23) },
1167
+
[RST_AHB1_DEU1] = { 0x2c4, BIT(24) },
1168
+
[RST_AHB1_DRC0] = { 0x2c4, BIT(25) },
1169
+
[RST_AHB1_DRC1] = { 0x2c4, BIT(26) },
1170
+
[RST_AHB1_LVDS] = { 0x2c8, BIT(0) },
1171
+
1172
+
[RST_APB1_CODEC] = { 0x2d0, BIT(0) },
1173
+
[RST_APB1_SPDIF] = { 0x2d0, BIT(1) },
1174
+
[RST_APB1_DIGITAL_MIC] = { 0x2d0, BIT(4) },
1175
+
[RST_APB1_DAUDIO0] = { 0x2d0, BIT(12) },
1176
+
[RST_APB1_DAUDIO1] = { 0x2d0, BIT(13) },
1177
+
1178
+
[RST_APB2_I2C0] = { 0x2d8, BIT(0) },
1179
+
[RST_APB2_I2C1] = { 0x2d8, BIT(1) },
1180
+
[RST_APB2_I2C2] = { 0x2d8, BIT(2) },
1181
+
[RST_APB2_I2C3] = { 0x2d8, BIT(3) },
1182
+
[RST_APB2_UART0] = { 0x2d8, BIT(16) },
1183
+
[RST_APB2_UART1] = { 0x2d8, BIT(17) },
1184
+
[RST_APB2_UART2] = { 0x2d8, BIT(18) },
1185
+
[RST_APB2_UART3] = { 0x2d8, BIT(19) },
1186
+
[RST_APB2_UART4] = { 0x2d8, BIT(20) },
1187
+
[RST_APB2_UART5] = { 0x2d8, BIT(21) },
1188
+
};
1189
+
1190
+
static const struct sunxi_ccu_desc sun6i_a31_ccu_desc = {
1191
+
.ccu_clks = sun6i_a31_ccu_clks,
1192
+
.num_ccu_clks = ARRAY_SIZE(sun6i_a31_ccu_clks),
1193
+
1194
+
.hw_clks = &sun6i_a31_hw_clks,
1195
+
1196
+
.resets = sun6i_a31_ccu_resets,
1197
+
.num_resets = ARRAY_SIZE(sun6i_a31_ccu_resets),
1198
+
};
1199
+
1200
+
static struct ccu_mux_nb sun6i_a31_cpu_nb = {
1201
+
.common = &cpu_clk.common,
1202
+
.cm = &cpu_clk.mux,
1203
+
.delay_us = 1, /* > 8 clock cycles at 24 MHz */
1204
+
.bypass_index = 1, /* index of 24 MHz oscillator */
1205
+
};
1206
+
1207
+
static void __init sun6i_a31_ccu_setup(struct device_node *node)
1208
+
{
1209
+
void __iomem *reg;
1210
+
u32 val;
1211
+
1212
+
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1213
+
if (IS_ERR(reg)) {
1214
+
pr_err("%s: Could not map the clock registers\n",
1215
+
of_node_full_name(node));
1216
+
return;
1217
+
}
1218
+
1219
+
/* Force the PLL-Audio-1x divider to 4 */
1220
+
val = readl(reg + SUN6I_A31_PLL_AUDIO_REG);
1221
+
val &= ~GENMASK(19, 16);
1222
+
writel(val | (3 << 16), reg + SUN6I_A31_PLL_AUDIO_REG);
1223
+
1224
+
/* Force PLL-MIPI to MIPI mode */
1225
+
val = readl(reg + SUN6I_A31_PLL_MIPI_REG);
1226
+
val &= BIT(16);
1227
+
writel(val, reg + SUN6I_A31_PLL_MIPI_REG);
1228
+
1229
+
sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc);
1230
+
1231
+
ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
1232
+
&sun6i_a31_cpu_nb);
1233
+
}
1234
+
CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu",
1235
+
sun6i_a31_ccu_setup);
+72
drivers/clk/sunxi-ng/ccu-sun6i-a31.h
+72
drivers/clk/sunxi-ng/ccu-sun6i-a31.h
···
1
+
/*
2
+
* Copyright 2016 Chen-Yu Tsai
3
+
*
4
+
* Chen-Yu Tsai <wens@csie.org>
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License as published by
8
+
* the Free Software Foundation; either version 2 of the License, or
9
+
* (at your option) any later version.
10
+
*
11
+
* This program is distributed in the hope that it will be useful,
12
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
+
* GNU General Public License for more details.
15
+
*/
16
+
17
+
#ifndef _CCU_SUN6I_A31_H_
18
+
#define _CCU_SUN6I_A31_H_
19
+
20
+
#include <dt-bindings/clock/sun6i-a31-ccu.h>
21
+
#include <dt-bindings/reset/sun6i-a31-ccu.h>
22
+
23
+
#define CLK_PLL_CPU 0
24
+
#define CLK_PLL_AUDIO_BASE 1
25
+
#define CLK_PLL_AUDIO 2
26
+
#define CLK_PLL_AUDIO_2X 3
27
+
#define CLK_PLL_AUDIO_4X 4
28
+
#define CLK_PLL_AUDIO_8X 5
29
+
#define CLK_PLL_VIDEO0 6
30
+
#define CLK_PLL_VIDEO0_2X 7
31
+
#define CLK_PLL_VE 8
32
+
#define CLK_PLL_DDR 9
33
+
34
+
/* The PLL_PERIPH clock is exported */
35
+
36
+
#define CLK_PLL_PERIPH_2X 11
37
+
#define CLK_PLL_VIDEO1 12
38
+
#define CLK_PLL_VIDEO1_2X 13
39
+
#define CLK_PLL_GPU 14
40
+
#define CLK_PLL_MIPI 15
41
+
#define CLK_PLL9 16
42
+
#define CLK_PLL10 17
43
+
44
+
/* The CPUX clock is exported */
45
+
46
+
#define CLK_AXI 19
47
+
#define CLK_AHB1 20
48
+
#define CLK_APB1 21
49
+
#define CLK_APB2 22
50
+
51
+
/* All the bus gates are exported */
52
+
53
+
/* The first bunch of module clocks are exported */
54
+
55
+
/* EMAC clock is not implemented */
56
+
57
+
#define CLK_MDFS 107
58
+
#define CLK_SDRAM0 108
59
+
#define CLK_SDRAM1 109
60
+
61
+
/* All the DRAM gates are exported */
62
+
63
+
/* Some more module clocks are exported */
64
+
65
+
#define CLK_MBUS0 141
66
+
#define CLK_MBUS1 142
67
+
68
+
/* Some more module clocks and external clock outputs are exported */
69
+
70
+
#define CLK_NUMBER (CLK_OUT_C + 1)
71
+
72
+
#endif /* _CCU_SUN6I_A31_H_ */
+187
include/dt-bindings/clock/sun6i-a31-ccu.h
+187
include/dt-bindings/clock/sun6i-a31-ccu.h
···
1
+
/*
2
+
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
3
+
*
4
+
* This file is dual-licensed: you can use it either under the terms
5
+
* of the GPL or the X11 license, at your option. Note that this dual
6
+
* licensing only applies to this file, and not this project as a
7
+
* whole.
8
+
*
9
+
* a) This file is free software; you can redistribute it and/or
10
+
* modify it under the terms of the GNU General Public License as
11
+
* published by the Free Software Foundation; either version 2 of the
12
+
* License, or (at your option) any later version.
13
+
*
14
+
* This file is distributed in the hope that it will be useful,
15
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
16
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17
+
* GNU General Public License for more details.
18
+
*
19
+
* Or, alternatively,
20
+
*
21
+
* b) Permission is hereby granted, free of charge, to any person
22
+
* obtaining a copy of this software and associated documentation
23
+
* files (the "Software"), to deal in the Software without
24
+
* restriction, including without limitation the rights to use,
25
+
* copy, modify, merge, publish, distribute, sublicense, and/or
26
+
* sell copies of the Software, and to permit persons to whom the
27
+
* Software is furnished to do so, subject to the following
28
+
* conditions:
29
+
*
30
+
* The above copyright notice and this permission notice shall be
31
+
* included in all copies or substantial portions of the Software.
32
+
*
33
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34
+
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35
+
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36
+
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37
+
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38
+
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39
+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40
+
* OTHER DEALINGS IN THE SOFTWARE.
41
+
*/
42
+
43
+
#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
44
+
#define _DT_BINDINGS_CLK_SUN6I_A31_H_
45
+
46
+
#define CLK_PLL_PERIPH 10
47
+
48
+
#define CLK_CPU 18
49
+
50
+
#define CLK_AHB1_MIPIDSI 23
51
+
#define CLK_AHB1_SS 24
52
+
#define CLK_AHB1_DMA 25
53
+
#define CLK_AHB1_MMC0 26
54
+
#define CLK_AHB1_MMC1 27
55
+
#define CLK_AHB1_MMC2 28
56
+
#define CLK_AHB1_MMC3 29
57
+
#define CLK_AHB1_NAND1 30
58
+
#define CLK_AHB1_NAND0 31
59
+
#define CLK_AHB1_SDRAM 32
60
+
#define CLK_AHB1_EMAC 33
61
+
#define CLK_AHB1_TS 34
62
+
#define CLK_AHB1_HSTIMER 35
63
+
#define CLK_AHB1_SPI0 36
64
+
#define CLK_AHB1_SPI1 37
65
+
#define CLK_AHB1_SPI2 38
66
+
#define CLK_AHB1_SPI3 39
67
+
#define CLK_AHB1_OTG 40
68
+
#define CLK_AHB1_EHCI0 41
69
+
#define CLK_AHB1_EHCI1 42
70
+
#define CLK_AHB1_OHCI0 43
71
+
#define CLK_AHB1_OHCI1 44
72
+
#define CLK_AHB1_OHCI2 45
73
+
#define CLK_AHB1_VE 46
74
+
#define CLK_AHB1_LCD0 47
75
+
#define CLK_AHB1_LCD1 48
76
+
#define CLK_AHB1_CSI 49
77
+
#define CLK_AHB1_HDMI 50
78
+
#define CLK_AHB1_BE0 51
79
+
#define CLK_AHB1_BE1 52
80
+
#define CLK_AHB1_FE0 53
81
+
#define CLK_AHB1_FE1 54
82
+
#define CLK_AHB1_MP 55
83
+
#define CLK_AHB1_GPU 56
84
+
#define CLK_AHB1_DEU0 57
85
+
#define CLK_AHB1_DEU1 58
86
+
#define CLK_AHB1_DRC0 59
87
+
#define CLK_AHB1_DRC1 60
88
+
89
+
#define CLK_APB1_CODEC 61
90
+
#define CLK_APB1_SPDIF 62
91
+
#define CLK_APB1_DIGITAL_MIC 63
92
+
#define CLK_APB1_PIO 64
93
+
#define CLK_APB1_DAUDIO0 65
94
+
#define CLK_APB1_DAUDIO1 66
95
+
96
+
#define CLK_APB2_I2C0 67
97
+
#define CLK_APB2_I2C1 68
98
+
#define CLK_APB2_I2C2 69
99
+
#define CLK_APB2_I2C3 70
100
+
#define CLK_APB2_UART0 71
101
+
#define CLK_APB2_UART1 72
102
+
#define CLK_APB2_UART2 73
103
+
#define CLK_APB2_UART3 74
104
+
#define CLK_APB2_UART4 75
105
+
#define CLK_APB2_UART5 76
106
+
107
+
#define CLK_NAND0 77
108
+
#define CLK_NAND1 78
109
+
#define CLK_MMC0 79
110
+
#define CLK_MMC0_SAMPLE 80
111
+
#define CLK_MMC0_OUTPUT 81
112
+
#define CLK_MMC1 82
113
+
#define CLK_MMC1_SAMPLE 83
114
+
#define CLK_MMC1_OUTPUT 84
115
+
#define CLK_MMC2 85
116
+
#define CLK_MMC2_SAMPLE 86
117
+
#define CLK_MMC2_OUTPUT 87
118
+
#define CLK_MMC3 88
119
+
#define CLK_MMC3_SAMPLE 89
120
+
#define CLK_MMC3_OUTPUT 90
121
+
#define CLK_TS 91
122
+
#define CLK_SS 92
123
+
#define CLK_SPI0 93
124
+
#define CLK_SPI1 94
125
+
#define CLK_SPI2 95
126
+
#define CLK_SPI3 96
127
+
#define CLK_DAUDIO0 97
128
+
#define CLK_DAUDIO1 98
129
+
#define CLK_SPDIF 99
130
+
#define CLK_USB_PHY0 100
131
+
#define CLK_USB_PHY1 101
132
+
#define CLK_USB_PHY2 102
133
+
#define CLK_USB_OHCI0 103
134
+
#define CLK_USB_OHCI1 104
135
+
#define CLK_USB_OHCI2 105
136
+
137
+
#define CLK_DRAM_VE 110
138
+
#define CLK_DRAM_CSI_ISP 111
139
+
#define CLK_DRAM_TS 112
140
+
#define CLK_DRAM_DRC0 113
141
+
#define CLK_DRAM_DRC1 114
142
+
#define CLK_DRAM_DEU0 115
143
+
#define CLK_DRAM_DEU1 116
144
+
#define CLK_DRAM_FE0 117
145
+
#define CLK_DRAM_FE1 118
146
+
#define CLK_DRAM_BE0 119
147
+
#define CLK_DRAM_BE1 120
148
+
#define CLK_DRAM_MP 121
149
+
150
+
#define CLK_BE0 122
151
+
#define CLK_BE1 123
152
+
#define CLK_FE0 124
153
+
#define CLK_FE1 125
154
+
#define CLK_MP 126
155
+
#define CLK_LCD0_CH0 127
156
+
#define CLK_LCD1_CH0 128
157
+
#define CLK_LCD0_CH1 129
158
+
#define CLK_LCD1_CH1 130
159
+
#define CLK_CSI0_SCLK 131
160
+
#define CLK_CSI0_MCLK 132
161
+
#define CLK_CSI1_MCLK 133
162
+
#define CLK_VE 134
163
+
#define CLK_CODEC 135
164
+
#define CLK_AVS 136
165
+
#define CLK_DIGITAL_MIC 137
166
+
#define CLK_HDMI 138
167
+
#define CLK_HDMI_DDC 139
168
+
#define CLK_PS 140
169
+
170
+
#define CLK_MIPI_DSI 143
171
+
#define CLK_MIPI_DSI_DPHY 144
172
+
#define CLK_MIPI_CSI_DPHY 145
173
+
#define CLK_IEP_DRC0 146
174
+
#define CLK_IEP_DRC1 147
175
+
#define CLK_IEP_DEU0 148
176
+
#define CLK_IEP_DEU1 149
177
+
#define CLK_GPU_CORE 150
178
+
#define CLK_GPU_MEMORY 151
179
+
#define CLK_GPU_HYD 152
180
+
#define CLK_ATS 153
181
+
#define CLK_TRACE 154
182
+
183
+
#define CLK_OUT_A 155
184
+
#define CLK_OUT_B 156
185
+
#define CLK_OUT_C 157
186
+
187
+
#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */
+106
include/dt-bindings/reset/sun6i-a31-ccu.h
+106
include/dt-bindings/reset/sun6i-a31-ccu.h
···
1
+
/*
2
+
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
3
+
*
4
+
* This file is dual-licensed: you can use it either under the terms
5
+
* of the GPL or the X11 license, at your option. Note that this dual
6
+
* licensing only applies to this file, and not this project as a
7
+
* whole.
8
+
*
9
+
* a) This file is free software; you can redistribute it and/or
10
+
* modify it under the terms of the GNU General Public License as
11
+
* published by the Free Software Foundation; either version 2 of the
12
+
* License, or (at your option) any later version.
13
+
*
14
+
* This file is distributed in the hope that it will be useful,
15
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
16
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17
+
* GNU General Public License for more details.
18
+
*
19
+
* Or, alternatively,
20
+
*
21
+
* b) Permission is hereby granted, free of charge, to any person
22
+
* obtaining a copy of this software and associated documentation
23
+
* files (the "Software"), to deal in the Software without
24
+
* restriction, including without limitation the rights to use,
25
+
* copy, modify, merge, publish, distribute, sublicense, and/or
26
+
* sell copies of the Software, and to permit persons to whom the
27
+
* Software is furnished to do so, subject to the following
28
+
* conditions:
29
+
*
30
+
* The above copyright notice and this permission notice shall be
31
+
* included in all copies or substantial portions of the Software.
32
+
*
33
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34
+
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35
+
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36
+
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37
+
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38
+
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39
+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40
+
* OTHER DEALINGS IN THE SOFTWARE.
41
+
*/
42
+
43
+
#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_
44
+
#define _DT_BINDINGS_RST_SUN6I_A31_H_
45
+
46
+
#define RST_USB_PHY0 0
47
+
#define RST_USB_PHY1 1
48
+
#define RST_USB_PHY2 2
49
+
50
+
#define RST_AHB1_MIPI_DSI 3
51
+
#define RST_AHB1_SS 4
52
+
#define RST_AHB1_DMA 5
53
+
#define RST_AHB1_MMC0 6
54
+
#define RST_AHB1_MMC1 7
55
+
#define RST_AHB1_MMC2 8
56
+
#define RST_AHB1_MMC3 9
57
+
#define RST_AHB1_NAND1 10
58
+
#define RST_AHB1_NAND0 11
59
+
#define RST_AHB1_SDRAM 12
60
+
#define RST_AHB1_EMAC 13
61
+
#define RST_AHB1_TS 14
62
+
#define RST_AHB1_HSTIMER 15
63
+
#define RST_AHB1_SPI0 16
64
+
#define RST_AHB1_SPI1 17
65
+
#define RST_AHB1_SPI2 18
66
+
#define RST_AHB1_SPI3 19
67
+
#define RST_AHB1_OTG 20
68
+
#define RST_AHB1_EHCI0 21
69
+
#define RST_AHB1_EHCI1 22
70
+
#define RST_AHB1_OHCI0 23
71
+
#define RST_AHB1_OHCI1 24
72
+
#define RST_AHB1_OHCI2 25
73
+
#define RST_AHB1_VE 26
74
+
#define RST_AHB1_LCD0 27
75
+
#define RST_AHB1_LCD1 28
76
+
#define RST_AHB1_CSI 29
77
+
#define RST_AHB1_HDMI 30
78
+
#define RST_AHB1_BE0 31
79
+
#define RST_AHB1_BE1 32
80
+
#define RST_AHB1_FE0 33
81
+
#define RST_AHB1_FE1 34
82
+
#define RST_AHB1_MP 35
83
+
#define RST_AHB1_GPU 36
84
+
#define RST_AHB1_DEU0 37
85
+
#define RST_AHB1_DEU1 38
86
+
#define RST_AHB1_DRC0 39
87
+
#define RST_AHB1_DRC1 40
88
+
#define RST_AHB1_LVDS 41
89
+
90
+
#define RST_APB1_CODEC 42
91
+
#define RST_APB1_SPDIF 43
92
+
#define RST_APB1_DIGITAL_MIC 44
93
+
#define RST_APB1_DAUDIO0 45
94
+
#define RST_APB1_DAUDIO1 46
95
+
#define RST_APB2_I2C0 47
96
+
#define RST_APB2_I2C1 48
97
+
#define RST_APB2_I2C2 49
98
+
#define RST_APB2_I2C3 50
99
+
#define RST_APB2_UART0 51
100
+
#define RST_APB2_UART1 52
101
+
#define RST_APB2_UART2 53
102
+
#define RST_APB2_UART3 54
103
+
#define RST_APB2_UART4 55
104
+
#define RST_APB2_UART5 56
105
+
106
+
#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */