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[PATCH] ppc32: Fix PPC440SP SRAM controller DCRs

Fixes the incorrect DCR base value for the 440SP SRAM controller.

Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

authored by Matt Porter and committed by Linus Torvalds c6a3ea22 28cd1d17

-4
unified split
-4
include/asm-ppc/ibm44x.h
··· 423 #define MQ0_CONFIG_SIZE_2G 0x0000c000 424 425 /* Internal SRAM Controller 440GX/440SP */ 426 - #ifdef CONFIG_440SP 427 - #define DCRN_SRAM0_BASE 0x100 428 - #else /* 440GX */ 429 #define DCRN_SRAM0_BASE 0x000 430 - #endif 431 432 #define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) 433 #define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021)
··· 423 #define MQ0_CONFIG_SIZE_2G 0x0000c000 424 425 /* Internal SRAM Controller 440GX/440SP */ 426 #define DCRN_SRAM0_BASE 0x000 427 428 #define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) 429 #define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021)