[PATCH] ata_piix: allow 01b MAP for both ICH6M and ICH7M

ICH7M was separated from ICH6M to allow undocumented MAP value 01b
which was spotted on an ASUS notebook. However, there is also
notebooks with MAP value 01b on ICH6M. This patch re-merges ICH6M and
ICH7M entries and allows MAP value 01b for both.

This problem has been reported and initial patch provided by Jonathan
Dieter.

Signed-off-by: Tejun Heo <htejun@gmail.com>
Cc: Jonathan Dieter <jdieter@gmail.com>
Cc: Tom Deblauwe <tom.deblauwe@telenet.be>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

authored by Tejun Heo and committed by Jeff Garzik c6446a4c 6e42acc4

+5 -32
+5 -32
drivers/ata/ata_piix.c
··· 126 ich6_sata = 7, 127 ich6_sata_ahci = 8, 128 ich6m_sata_ahci = 9, 129 - ich7m_sata_ahci = 10, 130 - ich8_sata_ahci = 11, 131 132 /* constants for mapping table */ 133 P0 = 0, /* port 0 */ ··· 227 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 228 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 229 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 230 - { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7m_sata_ahci }, 231 /* Enterprise Southbridge 2 (where's the datasheet?) */ 232 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 233 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */ ··· 399 .mask = 0x3, 400 .port_enable = 0x5, 401 .present_shift = 4, 402 - .map = { 403 - /* PM PS SM SS MAP */ 404 - { P0, P2, RV, RV }, /* 00b */ 405 - { RV, RV, RV, RV }, 406 - { P0, P2, IDE, IDE }, /* 10b */ 407 - { RV, RV, RV, RV }, 408 - }, 409 - }; 410 - 411 - static const struct piix_map_db ich7m_map_db = { 412 - .mask = 0x3, 413 - .port_enable = 0x5, 414 - .present_shift = 4, 415 416 /* Map 01b isn't specified in the doc but some notebooks use 417 - * it anyway. ATM, the only case spotted carries subsystem ID 418 - * 1025:0107. This is the only difference from ich6m. 419 */ 420 .map = { 421 /* PM PS SM SS MAP */ ··· 432 [ich6_sata] = &ich6_map_db, 433 [ich6_sata_ahci] = &ich6_map_db, 434 [ich6m_sata_ahci] = &ich6m_map_db, 435 - [ich7m_sata_ahci] = &ich7m_map_db, 436 [ich8_sata_ahci] = &ich8_map_db, 437 }; 438 ··· 542 .port_ops = &piix_sata_ops, 543 }, 544 545 - /* ich7m_sata_ahci: 10 */ 546 - { 547 - .sht = &piix_sht, 548 - .flags = ATA_FLAG_SATA | 549 - PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR | 550 - PIIX_FLAG_AHCI, 551 - .pio_mask = 0x1f, /* pio0-4 */ 552 - .mwdma_mask = 0x07, /* mwdma0-2 */ 553 - .udma_mask = 0x7f, /* udma0-6 */ 554 - .port_ops = &piix_sata_ops, 555 - }, 556 - 557 - /* ich8_sata_ahci: 11 */ 558 { 559 .sht = &piix_sht, 560 .flags = ATA_FLAG_SATA |
··· 126 ich6_sata = 7, 127 ich6_sata_ahci = 8, 128 ich6m_sata_ahci = 9, 129 + ich8_sata_ahci = 10, 130 131 /* constants for mapping table */ 132 P0 = 0, /* port 0 */ ··· 228 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 229 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 230 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 231 + { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, 232 /* Enterprise Southbridge 2 (where's the datasheet?) */ 233 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 234 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */ ··· 400 .mask = 0x3, 401 .port_enable = 0x5, 402 .present_shift = 4, 403 404 /* Map 01b isn't specified in the doc but some notebooks use 405 + * it anyway. MAP 01b have been spotted on both ICH6M and 406 + * ICH7M. 407 */ 408 .map = { 409 /* PM PS SM SS MAP */ ··· 446 [ich6_sata] = &ich6_map_db, 447 [ich6_sata_ahci] = &ich6_map_db, 448 [ich6m_sata_ahci] = &ich6m_map_db, 449 [ich8_sata_ahci] = &ich8_map_db, 450 }; 451 ··· 557 .port_ops = &piix_sata_ops, 558 }, 559 560 + /* ich8_sata_ahci: 10 */ 561 { 562 .sht = &piix_sht, 563 .flags = ATA_FLAG_SATA |