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linux
[ARM] 4111/1: Allow VFP to work with thread migration on SMP
The current lazy saving of the VFP registers is no longer possible
with thread migration on SMP. This patch implements a per-CPU
vfp-state pointer and the saving of the VFP registers at every context
switch. The registers restoring is still performed in a lazy way.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
authored by
Catalin Marinas
and committed by
Russell King
c6428464
412489af
+58
-6
+1
arch/arm/vfp/entry.S
+1
arch/arm/vfp/entry.S
+4
arch/arm/vfp/vfp.h
+4
arch/arm/vfp/vfp.h
+24
-2
arch/arm/vfp/vfphw.S
+24
-2
arch/arm/vfp/vfphw.S
···
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@ r2 = faulted PC+4
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@ r9 = successful return
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@ r10 = vfp_state union
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+
@ r11 = CPU number
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@ lr = failure return
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.globl vfp_support_entry
···
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DBGSTR1 "enable %x", r10
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ldr r3, last_VFP_context_address
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orr r1, r1, #FPEXC_ENABLE @ user FPEXC has the enable bit set
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-
ldr r4, [r3] @ last_VFP_context pointer
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ldr r4, [r3, r11, lsl #2] @ last_VFP_context pointer
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bic r5, r1, #FPEXC_EXCEPTION @ make sure exceptions are disabled
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cmp r4, r10
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beq check_for_exception @ we are returning to the same
···
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@ exceptions, so we can get at the
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@ rest of it
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#ifndef CONFIG_SMP
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@ Save out the current registers to the old thread state
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@ No need for SMP since this is not done lazily
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DBGSTR1 "save old state %p", r4
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cmp r4, #0
···
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stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
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@ and point r4 at the word at the
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@ start of the register dump
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#endif
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no_old_VFP_process:
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DBGSTR1 "load state %p", r10
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-
str r10, [r3] @ update the last_VFP_context pointer
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str r10, [r3, r11, lsl #2] @ update the last_VFP_context pointer
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@ Load the saved state back into the VFP
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VFPFLDMIA r10 @ reload the working registers while
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@ FPEXC is in a safe state
···
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@ code will raise an exception if
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@ required. If not, the user code will
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@ retry the faulted instruction
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#ifdef CONFIG_SMP
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.globl vfp_save_state
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.type vfp_save_state, %function
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vfp_save_state:
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@ Save the current VFP state
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@ r0 - save location
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@ r1 - FPEXC
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DBGSTR1 "save VFP state %p", r0
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VFPFMRX r2, FPSCR @ current status
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VFPFMRX r3, FPINST @ FPINST (always there, rev0 onwards)
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tst r1, #FPEXC_FPV2 @ is there an FPINST2 to read?
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VFPFMRX r12, FPINST2, NE @ FPINST2 if needed - avoids reading
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@ nonexistant reg on rev0
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VFPFSTMIA r0 @ save the working registers
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stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
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mov pc, lr
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#endif
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last_VFP_context_address:
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.word last_VFP_context
+26
-4
arch/arm/vfp/vfpmodule.c
+26
-4
arch/arm/vfp/vfpmodule.c
···
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void vfp_support_entry(void);
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void (*vfp_vector)(void) = vfp_testing_entry;
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-
union vfp_state *last_VFP_context;
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union vfp_state *last_VFP_context[NR_CPUS];
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/*
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* Dual-use variable.
···
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{
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struct thread_info *thread = v;
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union vfp_state *vfp;
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__u32 cpu = thread->cpu;
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if (likely(cmd == THREAD_NOTIFY_SWITCH)) {
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u32 fpexc = fmrx(FPEXC);
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+
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#ifdef CONFIG_SMP
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/*
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* On SMP, if VFP is enabled, save the old state in
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* case the thread migrates to a different CPU. The
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* restoring is done lazily.
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*/
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if ((fpexc & FPEXC_ENABLE) && last_VFP_context[cpu]) {
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vfp_save_state(last_VFP_context[cpu], fpexc);
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last_VFP_context[cpu]->hard.cpu = cpu;
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}
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/*
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* Thread migration, just force the reloading of the
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* state on the new CPU in case the VFP registers
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* contain stale data.
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*/
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if (thread->vfpstate.hard.cpu != cpu)
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last_VFP_context[cpu] = NULL;
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#endif
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+
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/*
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* Always disable VFP so we can lazily save/restore the
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* old state.
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*/
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fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_ENABLE);
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fmxr(FPEXC, fpexc & ~FPEXC_ENABLE);
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return NOTIFY_DONE;
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}
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···
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}
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/* flush and release case: Per-thread VFP cleanup. */
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-
if (last_VFP_context == vfp)
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last_VFP_context = NULL;
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if (last_VFP_context[cpu] == vfp)
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last_VFP_context[cpu] = NULL;
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return NOTIFY_DONE;
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}