tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/amdgpu/include: Add sdma0/1 4.2 register headerfiles. (v3)

These are the System DMA register headers for vega20.

v2: cleanups (Alex)
v3: add missing licenses (Alex)

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Feifei Xu and committed by
Alex Deucher c62d3cd0 1f902ede

+8026
+1047
drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h
··· 1 + /* 2 + * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _sdma0_4_2_0_OFFSET_HEADER 22 + #define _sdma0_4_2_0_OFFSET_HEADER 23 + 24 + 25 + 26 + // addressBlock: sdma0_sdma0dec 27 + // base address: 0x4980 28 + #define mmSDMA0_UCODE_ADDR 0x0000 29 + #define mmSDMA0_UCODE_ADDR_BASE_IDX 0 30 + #define mmSDMA0_UCODE_DATA 0x0001 31 + #define mmSDMA0_UCODE_DATA_BASE_IDX 0 32 + #define mmSDMA0_VM_CNTL 0x0004 33 + #define mmSDMA0_VM_CNTL_BASE_IDX 0 34 + #define mmSDMA0_VM_CTX_LO 0x0005 35 + #define mmSDMA0_VM_CTX_LO_BASE_IDX 0 36 + #define mmSDMA0_VM_CTX_HI 0x0006 37 + #define mmSDMA0_VM_CTX_HI_BASE_IDX 0 38 + #define mmSDMA0_ACTIVE_FCN_ID 0x0007 39 + #define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 40 + #define mmSDMA0_VM_CTX_CNTL 0x0008 41 + #define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 42 + #define mmSDMA0_VIRT_RESET_REQ 0x0009 43 + #define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 44 + #define mmSDMA0_VF_ENABLE 0x000a 45 + #define mmSDMA0_VF_ENABLE_BASE_IDX 0 46 + #define mmSDMA0_CONTEXT_REG_TYPE0 0x000b 47 + #define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 48 + #define mmSDMA0_CONTEXT_REG_TYPE1 0x000c 49 + #define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 50 + #define mmSDMA0_CONTEXT_REG_TYPE2 0x000d 51 + #define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 52 + #define mmSDMA0_CONTEXT_REG_TYPE3 0x000e 53 + #define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 54 + #define mmSDMA0_PUB_REG_TYPE0 0x000f 55 + #define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 56 + #define mmSDMA0_PUB_REG_TYPE1 0x0010 57 + #define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 58 + #define mmSDMA0_PUB_REG_TYPE2 0x0011 59 + #define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 60 + #define mmSDMA0_PUB_REG_TYPE3 0x0012 61 + #define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 62 + #define mmSDMA0_MMHUB_CNTL 0x0013 63 + #define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 64 + #define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 65 + #define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 66 + #define mmSDMA0_POWER_CNTL 0x001a 67 + #define mmSDMA0_POWER_CNTL_BASE_IDX 0 68 + #define mmSDMA0_CLK_CTRL 0x001b 69 + #define mmSDMA0_CLK_CTRL_BASE_IDX 0 70 + #define mmSDMA0_CNTL 0x001c 71 + #define mmSDMA0_CNTL_BASE_IDX 0 72 + #define mmSDMA0_CHICKEN_BITS 0x001d 73 + #define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 74 + #define mmSDMA0_GB_ADDR_CONFIG 0x001e 75 + #define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 76 + #define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f 77 + #define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 78 + #define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 79 + #define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 80 + #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 81 + #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 82 + #define mmSDMA0_RB_RPTR_FETCH 0x0022 83 + #define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 84 + #define mmSDMA0_IB_OFFSET_FETCH 0x0023 85 + #define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 86 + #define mmSDMA0_PROGRAM 0x0024 87 + #define mmSDMA0_PROGRAM_BASE_IDX 0 88 + #define mmSDMA0_STATUS_REG 0x0025 89 + #define mmSDMA0_STATUS_REG_BASE_IDX 0 90 + #define mmSDMA0_STATUS1_REG 0x0026 91 + #define mmSDMA0_STATUS1_REG_BASE_IDX 0 92 + #define mmSDMA0_RD_BURST_CNTL 0x0027 93 + #define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 94 + #define mmSDMA0_HBM_PAGE_CONFIG 0x0028 95 + #define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 96 + #define mmSDMA0_UCODE_CHECKSUM 0x0029 97 + #define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 98 + #define mmSDMA0_F32_CNTL 0x002a 99 + #define mmSDMA0_F32_CNTL_BASE_IDX 0 100 + #define mmSDMA0_FREEZE 0x002b 101 + #define mmSDMA0_FREEZE_BASE_IDX 0 102 + #define mmSDMA0_PHASE0_QUANTUM 0x002c 103 + #define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 104 + #define mmSDMA0_PHASE1_QUANTUM 0x002d 105 + #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 106 + #define mmSDMA_POWER_GATING 0x002e 107 + #define mmSDMA_POWER_GATING_BASE_IDX 0 108 + #define mmSDMA_PGFSM_CONFIG 0x002f 109 + #define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 110 + #define mmSDMA_PGFSM_WRITE 0x0030 111 + #define mmSDMA_PGFSM_WRITE_BASE_IDX 0 112 + #define mmSDMA_PGFSM_READ 0x0031 113 + #define mmSDMA_PGFSM_READ_BASE_IDX 0 114 + #define mmSDMA0_EDC_CONFIG 0x0032 115 + #define mmSDMA0_EDC_CONFIG_BASE_IDX 0 116 + #define mmSDMA0_BA_THRESHOLD 0x0033 117 + #define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 118 + #define mmSDMA0_ID 0x0034 119 + #define mmSDMA0_ID_BASE_IDX 0 120 + #define mmSDMA0_VERSION 0x0035 121 + #define mmSDMA0_VERSION_BASE_IDX 0 122 + #define mmSDMA0_EDC_COUNTER 0x0036 123 + #define mmSDMA0_EDC_COUNTER_BASE_IDX 0 124 + #define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 125 + #define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 126 + #define mmSDMA0_STATUS2_REG 0x0038 127 + #define mmSDMA0_STATUS2_REG_BASE_IDX 0 128 + #define mmSDMA0_ATOMIC_CNTL 0x0039 129 + #define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 130 + #define mmSDMA0_ATOMIC_PREOP_LO 0x003a 131 + #define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 132 + #define mmSDMA0_ATOMIC_PREOP_HI 0x003b 133 + #define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 134 + #define mmSDMA0_UTCL1_CNTL 0x003c 135 + #define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 136 + #define mmSDMA0_UTCL1_WATERMK 0x003d 137 + #define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 138 + #define mmSDMA0_UTCL1_RD_STATUS 0x003e 139 + #define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 140 + #define mmSDMA0_UTCL1_WR_STATUS 0x003f 141 + #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 142 + #define mmSDMA0_UTCL1_INV0 0x0040 143 + #define mmSDMA0_UTCL1_INV0_BASE_IDX 0 144 + #define mmSDMA0_UTCL1_INV1 0x0041 145 + #define mmSDMA0_UTCL1_INV1_BASE_IDX 0 146 + #define mmSDMA0_UTCL1_INV2 0x0042 147 + #define mmSDMA0_UTCL1_INV2_BASE_IDX 0 148 + #define mmSDMA0_UTCL1_RD_XNACK0 0x0043 149 + #define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 150 + #define mmSDMA0_UTCL1_RD_XNACK1 0x0044 151 + #define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 152 + #define mmSDMA0_UTCL1_WR_XNACK0 0x0045 153 + #define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 154 + #define mmSDMA0_UTCL1_WR_XNACK1 0x0046 155 + #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 156 + #define mmSDMA0_UTCL1_TIMEOUT 0x0047 157 + #define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 158 + #define mmSDMA0_UTCL1_PAGE 0x0048 159 + #define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 160 + #define mmSDMA0_POWER_CNTL_IDLE 0x0049 161 + #define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 162 + #define mmSDMA0_RELAX_ORDERING_LUT 0x004a 163 + #define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 164 + #define mmSDMA0_CHICKEN_BITS_2 0x004b 165 + #define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 166 + #define mmSDMA0_STATUS3_REG 0x004c 167 + #define mmSDMA0_STATUS3_REG_BASE_IDX 0 168 + #define mmSDMA0_PHYSICAL_ADDR_LO 0x004d 169 + #define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 170 + #define mmSDMA0_PHYSICAL_ADDR_HI 0x004e 171 + #define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 172 + #define mmSDMA0_PHASE2_QUANTUM 0x004f 173 + #define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 174 + #define mmSDMA0_ERROR_LOG 0x0050 175 + #define mmSDMA0_ERROR_LOG_BASE_IDX 0 176 + #define mmSDMA0_PUB_DUMMY_REG0 0x0051 177 + #define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 178 + #define mmSDMA0_PUB_DUMMY_REG1 0x0052 179 + #define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 180 + #define mmSDMA0_PUB_DUMMY_REG2 0x0053 181 + #define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 182 + #define mmSDMA0_PUB_DUMMY_REG3 0x0054 183 + #define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 184 + #define mmSDMA0_F32_COUNTER 0x0055 185 + #define mmSDMA0_F32_COUNTER_BASE_IDX 0 186 + #define mmSDMA0_PERFMON_CNTL 0x0057 187 + #define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 188 + #define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 189 + #define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 190 + #define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 191 + #define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 192 + #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a 193 + #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 194 + #define mmSDMA0_CRD_CNTL 0x005b 195 + #define mmSDMA0_CRD_CNTL_BASE_IDX 0 196 + #define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d 197 + #define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 198 + #define mmSDMA0_ULV_CNTL 0x005e 199 + #define mmSDMA0_ULV_CNTL_BASE_IDX 0 200 + #define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 201 + #define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 202 + #define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 203 + #define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 204 + #define mmSDMA0_GFX_RB_CNTL 0x0080 205 + #define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 206 + #define mmSDMA0_GFX_RB_BASE 0x0081 207 + #define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 208 + #define mmSDMA0_GFX_RB_BASE_HI 0x0082 209 + #define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 210 + #define mmSDMA0_GFX_RB_RPTR 0x0083 211 + #define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 212 + #define mmSDMA0_GFX_RB_RPTR_HI 0x0084 213 + #define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 214 + #define mmSDMA0_GFX_RB_WPTR 0x0085 215 + #define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 216 + #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 217 + #define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 218 + #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 219 + #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 220 + #define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 221 + #define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 222 + #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 223 + #define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 224 + #define mmSDMA0_GFX_IB_CNTL 0x008a 225 + #define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 226 + #define mmSDMA0_GFX_IB_RPTR 0x008b 227 + #define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 228 + #define mmSDMA0_GFX_IB_OFFSET 0x008c 229 + #define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 230 + #define mmSDMA0_GFX_IB_BASE_LO 0x008d 231 + #define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 232 + #define mmSDMA0_GFX_IB_BASE_HI 0x008e 233 + #define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 234 + #define mmSDMA0_GFX_IB_SIZE 0x008f 235 + #define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 236 + #define mmSDMA0_GFX_SKIP_CNTL 0x0090 237 + #define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 238 + #define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 239 + #define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 240 + #define mmSDMA0_GFX_DOORBELL 0x0092 241 + #define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 242 + #define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 243 + #define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 244 + #define mmSDMA0_GFX_STATUS 0x00a8 245 + #define mmSDMA0_GFX_STATUS_BASE_IDX 0 246 + #define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 247 + #define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 248 + #define mmSDMA0_GFX_WATERMARK 0x00aa 249 + #define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 250 + #define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab 251 + #define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 252 + #define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac 253 + #define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 254 + #define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad 255 + #define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 256 + #define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af 257 + #define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 258 + #define mmSDMA0_GFX_PREEMPT 0x00b0 259 + #define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 260 + #define mmSDMA0_GFX_DUMMY_REG 0x00b1 261 + #define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 262 + #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 263 + #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 264 + #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 265 + #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 266 + #define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 267 + #define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 268 + #define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 269 + #define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 270 + #define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 271 + #define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 272 + #define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 273 + #define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 274 + #define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 275 + #define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 276 + #define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 277 + #define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 278 + #define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 279 + #define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 280 + #define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 281 + #define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 282 + #define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 283 + #define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 284 + #define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 285 + #define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 286 + #define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 287 + #define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 288 + #define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 289 + #define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 290 + #define mmSDMA0_PAGE_RB_CNTL 0x00e0 291 + #define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 292 + #define mmSDMA0_PAGE_RB_BASE 0x00e1 293 + #define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 294 + #define mmSDMA0_PAGE_RB_BASE_HI 0x00e2 295 + #define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 296 + #define mmSDMA0_PAGE_RB_RPTR 0x00e3 297 + #define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 298 + #define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4 299 + #define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 300 + #define mmSDMA0_PAGE_RB_WPTR 0x00e5 301 + #define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 302 + #define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6 303 + #define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 304 + #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7 305 + #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 306 + #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8 307 + #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 308 + #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9 309 + #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 310 + #define mmSDMA0_PAGE_IB_CNTL 0x00ea 311 + #define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 312 + #define mmSDMA0_PAGE_IB_RPTR 0x00eb 313 + #define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 314 + #define mmSDMA0_PAGE_IB_OFFSET 0x00ec 315 + #define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 316 + #define mmSDMA0_PAGE_IB_BASE_LO 0x00ed 317 + #define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 318 + #define mmSDMA0_PAGE_IB_BASE_HI 0x00ee 319 + #define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 320 + #define mmSDMA0_PAGE_IB_SIZE 0x00ef 321 + #define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 322 + #define mmSDMA0_PAGE_SKIP_CNTL 0x00f0 323 + #define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 324 + #define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1 325 + #define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 326 + #define mmSDMA0_PAGE_DOORBELL 0x00f2 327 + #define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 328 + #define mmSDMA0_PAGE_STATUS 0x0108 329 + #define mmSDMA0_PAGE_STATUS_BASE_IDX 0 330 + #define mmSDMA0_PAGE_DOORBELL_LOG 0x0109 331 + #define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 332 + #define mmSDMA0_PAGE_WATERMARK 0x010a 333 + #define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 334 + #define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b 335 + #define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 336 + #define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c 337 + #define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 338 + #define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d 339 + #define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 340 + #define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f 341 + #define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 342 + #define mmSDMA0_PAGE_PREEMPT 0x0110 343 + #define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 344 + #define mmSDMA0_PAGE_DUMMY_REG 0x0111 345 + #define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 346 + #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 347 + #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 348 + #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 349 + #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 350 + #define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114 351 + #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 352 + #define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115 353 + #define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 354 + #define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120 355 + #define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 356 + #define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121 357 + #define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 358 + #define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122 359 + #define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 360 + #define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123 361 + #define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 362 + #define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124 363 + #define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 364 + #define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125 365 + #define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 366 + #define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126 367 + #define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 368 + #define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127 369 + #define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 370 + #define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128 371 + #define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 372 + #define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129 373 + #define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 374 + #define mmSDMA0_RLC0_RB_CNTL 0x0140 375 + #define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 376 + #define mmSDMA0_RLC0_RB_BASE 0x0141 377 + #define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 378 + #define mmSDMA0_RLC0_RB_BASE_HI 0x0142 379 + #define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 380 + #define mmSDMA0_RLC0_RB_RPTR 0x0143 381 + #define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 382 + #define mmSDMA0_RLC0_RB_RPTR_HI 0x0144 383 + #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 384 + #define mmSDMA0_RLC0_RB_WPTR 0x0145 385 + #define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 386 + #define mmSDMA0_RLC0_RB_WPTR_HI 0x0146 387 + #define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 388 + #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147 389 + #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 390 + #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148 391 + #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 392 + #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149 393 + #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 394 + #define mmSDMA0_RLC0_IB_CNTL 0x014a 395 + #define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 396 + #define mmSDMA0_RLC0_IB_RPTR 0x014b 397 + #define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 398 + #define mmSDMA0_RLC0_IB_OFFSET 0x014c 399 + #define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 400 + #define mmSDMA0_RLC0_IB_BASE_LO 0x014d 401 + #define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 402 + #define mmSDMA0_RLC0_IB_BASE_HI 0x014e 403 + #define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 404 + #define mmSDMA0_RLC0_IB_SIZE 0x014f 405 + #define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 406 + #define mmSDMA0_RLC0_SKIP_CNTL 0x0150 407 + #define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 408 + #define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151 409 + #define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 410 + #define mmSDMA0_RLC0_DOORBELL 0x0152 411 + #define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 412 + #define mmSDMA0_RLC0_STATUS 0x0168 413 + #define mmSDMA0_RLC0_STATUS_BASE_IDX 0 414 + #define mmSDMA0_RLC0_DOORBELL_LOG 0x0169 415 + #define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 416 + #define mmSDMA0_RLC0_WATERMARK 0x016a 417 + #define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 418 + #define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b 419 + #define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 420 + #define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c 421 + #define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 422 + #define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d 423 + #define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 424 + #define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f 425 + #define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 426 + #define mmSDMA0_RLC0_PREEMPT 0x0170 427 + #define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 428 + #define mmSDMA0_RLC0_DUMMY_REG 0x0171 429 + #define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 430 + #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 431 + #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 432 + #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 433 + #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 434 + #define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174 435 + #define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 436 + #define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175 437 + #define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 438 + #define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180 439 + #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 440 + #define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181 441 + #define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 442 + #define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182 443 + #define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 444 + #define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183 445 + #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 446 + #define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184 447 + #define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 448 + #define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185 449 + #define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 450 + #define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186 451 + #define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 452 + #define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187 453 + #define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 454 + #define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188 455 + #define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 456 + #define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189 457 + #define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 458 + #define mmSDMA0_RLC1_RB_CNTL 0x01a0 459 + #define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 460 + #define mmSDMA0_RLC1_RB_BASE 0x01a1 461 + #define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 462 + #define mmSDMA0_RLC1_RB_BASE_HI 0x01a2 463 + #define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 464 + #define mmSDMA0_RLC1_RB_RPTR 0x01a3 465 + #define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 466 + #define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4 467 + #define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 468 + #define mmSDMA0_RLC1_RB_WPTR 0x01a5 469 + #define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 470 + #define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6 471 + #define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 472 + #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7 473 + #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 474 + #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8 475 + #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 476 + #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9 477 + #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 478 + #define mmSDMA0_RLC1_IB_CNTL 0x01aa 479 + #define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 480 + #define mmSDMA0_RLC1_IB_RPTR 0x01ab 481 + #define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 482 + #define mmSDMA0_RLC1_IB_OFFSET 0x01ac 483 + #define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 484 + #define mmSDMA0_RLC1_IB_BASE_LO 0x01ad 485 + #define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 486 + #define mmSDMA0_RLC1_IB_BASE_HI 0x01ae 487 + #define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 488 + #define mmSDMA0_RLC1_IB_SIZE 0x01af 489 + #define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 490 + #define mmSDMA0_RLC1_SKIP_CNTL 0x01b0 491 + #define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 492 + #define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1 493 + #define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 494 + #define mmSDMA0_RLC1_DOORBELL 0x01b2 495 + #define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 496 + #define mmSDMA0_RLC1_STATUS 0x01c8 497 + #define mmSDMA0_RLC1_STATUS_BASE_IDX 0 498 + #define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9 499 + #define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 500 + #define mmSDMA0_RLC1_WATERMARK 0x01ca 501 + #define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 502 + #define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb 503 + #define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 504 + #define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc 505 + #define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 506 + #define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd 507 + #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 508 + #define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf 509 + #define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 510 + #define mmSDMA0_RLC1_PREEMPT 0x01d0 511 + #define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 512 + #define mmSDMA0_RLC1_DUMMY_REG 0x01d1 513 + #define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 514 + #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 515 + #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 516 + #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 517 + #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 518 + #define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4 519 + #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 520 + #define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5 521 + #define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 522 + #define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0 523 + #define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 524 + #define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1 525 + #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 526 + #define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2 527 + #define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 528 + #define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3 529 + #define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 530 + #define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4 531 + #define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 532 + #define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5 533 + #define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 534 + #define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6 535 + #define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 536 + #define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7 537 + #define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 538 + #define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8 539 + #define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 540 + #define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9 541 + #define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 542 + #define mmSDMA0_RLC2_RB_CNTL 0x0200 543 + #define mmSDMA0_RLC2_RB_CNTL_BASE_IDX 0 544 + #define mmSDMA0_RLC2_RB_BASE 0x0201 545 + #define mmSDMA0_RLC2_RB_BASE_BASE_IDX 0 546 + #define mmSDMA0_RLC2_RB_BASE_HI 0x0202 547 + #define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX 0 548 + #define mmSDMA0_RLC2_RB_RPTR 0x0203 549 + #define mmSDMA0_RLC2_RB_RPTR_BASE_IDX 0 550 + #define mmSDMA0_RLC2_RB_RPTR_HI 0x0204 551 + #define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX 0 552 + #define mmSDMA0_RLC2_RB_WPTR 0x0205 553 + #define mmSDMA0_RLC2_RB_WPTR_BASE_IDX 0 554 + #define mmSDMA0_RLC2_RB_WPTR_HI 0x0206 555 + #define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX 0 556 + #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x0207 557 + #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 558 + #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI 0x0208 559 + #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 560 + #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO 0x0209 561 + #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 562 + #define mmSDMA0_RLC2_IB_CNTL 0x020a 563 + #define mmSDMA0_RLC2_IB_CNTL_BASE_IDX 0 564 + #define mmSDMA0_RLC2_IB_RPTR 0x020b 565 + #define mmSDMA0_RLC2_IB_RPTR_BASE_IDX 0 566 + #define mmSDMA0_RLC2_IB_OFFSET 0x020c 567 + #define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX 0 568 + #define mmSDMA0_RLC2_IB_BASE_LO 0x020d 569 + #define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX 0 570 + #define mmSDMA0_RLC2_IB_BASE_HI 0x020e 571 + #define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX 0 572 + #define mmSDMA0_RLC2_IB_SIZE 0x020f 573 + #define mmSDMA0_RLC2_IB_SIZE_BASE_IDX 0 574 + #define mmSDMA0_RLC2_SKIP_CNTL 0x0210 575 + #define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX 0 576 + #define mmSDMA0_RLC2_CONTEXT_STATUS 0x0211 577 + #define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX 0 578 + #define mmSDMA0_RLC2_DOORBELL 0x0212 579 + #define mmSDMA0_RLC2_DOORBELL_BASE_IDX 0 580 + #define mmSDMA0_RLC2_STATUS 0x0228 581 + #define mmSDMA0_RLC2_STATUS_BASE_IDX 0 582 + #define mmSDMA0_RLC2_DOORBELL_LOG 0x0229 583 + #define mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX 0 584 + #define mmSDMA0_RLC2_WATERMARK 0x022a 585 + #define mmSDMA0_RLC2_WATERMARK_BASE_IDX 0 586 + #define mmSDMA0_RLC2_DOORBELL_OFFSET 0x022b 587 + #define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX 0 588 + #define mmSDMA0_RLC2_CSA_ADDR_LO 0x022c 589 + #define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX 0 590 + #define mmSDMA0_RLC2_CSA_ADDR_HI 0x022d 591 + #define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX 0 592 + #define mmSDMA0_RLC2_IB_SUB_REMAIN 0x022f 593 + #define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX 0 594 + #define mmSDMA0_RLC2_PREEMPT 0x0230 595 + #define mmSDMA0_RLC2_PREEMPT_BASE_IDX 0 596 + #define mmSDMA0_RLC2_DUMMY_REG 0x0231 597 + #define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX 0 598 + #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0x0232 599 + #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 600 + #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0x0233 601 + #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 602 + #define mmSDMA0_RLC2_RB_AQL_CNTL 0x0234 603 + #define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX 0 604 + #define mmSDMA0_RLC2_MINOR_PTR_UPDATE 0x0235 605 + #define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 606 + #define mmSDMA0_RLC2_MIDCMD_DATA0 0x0240 607 + #define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX 0 608 + #define mmSDMA0_RLC2_MIDCMD_DATA1 0x0241 609 + #define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX 0 610 + #define mmSDMA0_RLC2_MIDCMD_DATA2 0x0242 611 + #define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX 0 612 + #define mmSDMA0_RLC2_MIDCMD_DATA3 0x0243 613 + #define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX 0 614 + #define mmSDMA0_RLC2_MIDCMD_DATA4 0x0244 615 + #define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX 0 616 + #define mmSDMA0_RLC2_MIDCMD_DATA5 0x0245 617 + #define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX 0 618 + #define mmSDMA0_RLC2_MIDCMD_DATA6 0x0246 619 + #define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX 0 620 + #define mmSDMA0_RLC2_MIDCMD_DATA7 0x0247 621 + #define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX 0 622 + #define mmSDMA0_RLC2_MIDCMD_DATA8 0x0248 623 + #define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX 0 624 + #define mmSDMA0_RLC2_MIDCMD_CNTL 0x0249 625 + #define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX 0 626 + #define mmSDMA0_RLC3_RB_CNTL 0x0260 627 + #define mmSDMA0_RLC3_RB_CNTL_BASE_IDX 0 628 + #define mmSDMA0_RLC3_RB_BASE 0x0261 629 + #define mmSDMA0_RLC3_RB_BASE_BASE_IDX 0 630 + #define mmSDMA0_RLC3_RB_BASE_HI 0x0262 631 + #define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX 0 632 + #define mmSDMA0_RLC3_RB_RPTR 0x0263 633 + #define mmSDMA0_RLC3_RB_RPTR_BASE_IDX 0 634 + #define mmSDMA0_RLC3_RB_RPTR_HI 0x0264 635 + #define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX 0 636 + #define mmSDMA0_RLC3_RB_WPTR 0x0265 637 + #define mmSDMA0_RLC3_RB_WPTR_BASE_IDX 0 638 + #define mmSDMA0_RLC3_RB_WPTR_HI 0x0266 639 + #define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX 0 640 + #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x0267 641 + #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 642 + #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI 0x0268 643 + #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 644 + #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO 0x0269 645 + #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 646 + #define mmSDMA0_RLC3_IB_CNTL 0x026a 647 + #define mmSDMA0_RLC3_IB_CNTL_BASE_IDX 0 648 + #define mmSDMA0_RLC3_IB_RPTR 0x026b 649 + #define mmSDMA0_RLC3_IB_RPTR_BASE_IDX 0 650 + #define mmSDMA0_RLC3_IB_OFFSET 0x026c 651 + #define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX 0 652 + #define mmSDMA0_RLC3_IB_BASE_LO 0x026d 653 + #define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX 0 654 + #define mmSDMA0_RLC3_IB_BASE_HI 0x026e 655 + #define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX 0 656 + #define mmSDMA0_RLC3_IB_SIZE 0x026f 657 + #define mmSDMA0_RLC3_IB_SIZE_BASE_IDX 0 658 + #define mmSDMA0_RLC3_SKIP_CNTL 0x0270 659 + #define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX 0 660 + #define mmSDMA0_RLC3_CONTEXT_STATUS 0x0271 661 + #define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX 0 662 + #define mmSDMA0_RLC3_DOORBELL 0x0272 663 + #define mmSDMA0_RLC3_DOORBELL_BASE_IDX 0 664 + #define mmSDMA0_RLC3_STATUS 0x0288 665 + #define mmSDMA0_RLC3_STATUS_BASE_IDX 0 666 + #define mmSDMA0_RLC3_DOORBELL_LOG 0x0289 667 + #define mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX 0 668 + #define mmSDMA0_RLC3_WATERMARK 0x028a 669 + #define mmSDMA0_RLC3_WATERMARK_BASE_IDX 0 670 + #define mmSDMA0_RLC3_DOORBELL_OFFSET 0x028b 671 + #define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX 0 672 + #define mmSDMA0_RLC3_CSA_ADDR_LO 0x028c 673 + #define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX 0 674 + #define mmSDMA0_RLC3_CSA_ADDR_HI 0x028d 675 + #define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX 0 676 + #define mmSDMA0_RLC3_IB_SUB_REMAIN 0x028f 677 + #define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX 0 678 + #define mmSDMA0_RLC3_PREEMPT 0x0290 679 + #define mmSDMA0_RLC3_PREEMPT_BASE_IDX 0 680 + #define mmSDMA0_RLC3_DUMMY_REG 0x0291 681 + #define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX 0 682 + #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0x0292 683 + #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 684 + #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0x0293 685 + #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 686 + #define mmSDMA0_RLC3_RB_AQL_CNTL 0x0294 687 + #define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX 0 688 + #define mmSDMA0_RLC3_MINOR_PTR_UPDATE 0x0295 689 + #define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 690 + #define mmSDMA0_RLC3_MIDCMD_DATA0 0x02a0 691 + #define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX 0 692 + #define mmSDMA0_RLC3_MIDCMD_DATA1 0x02a1 693 + #define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX 0 694 + #define mmSDMA0_RLC3_MIDCMD_DATA2 0x02a2 695 + #define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX 0 696 + #define mmSDMA0_RLC3_MIDCMD_DATA3 0x02a3 697 + #define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX 0 698 + #define mmSDMA0_RLC3_MIDCMD_DATA4 0x02a4 699 + #define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX 0 700 + #define mmSDMA0_RLC3_MIDCMD_DATA5 0x02a5 701 + #define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX 0 702 + #define mmSDMA0_RLC3_MIDCMD_DATA6 0x02a6 703 + #define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX 0 704 + #define mmSDMA0_RLC3_MIDCMD_DATA7 0x02a7 705 + #define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX 0 706 + #define mmSDMA0_RLC3_MIDCMD_DATA8 0x02a8 707 + #define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX 0 708 + #define mmSDMA0_RLC3_MIDCMD_CNTL 0x02a9 709 + #define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX 0 710 + #define mmSDMA0_RLC4_RB_CNTL 0x02c0 711 + #define mmSDMA0_RLC4_RB_CNTL_BASE_IDX 0 712 + #define mmSDMA0_RLC4_RB_BASE 0x02c1 713 + #define mmSDMA0_RLC4_RB_BASE_BASE_IDX 0 714 + #define mmSDMA0_RLC4_RB_BASE_HI 0x02c2 715 + #define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX 0 716 + #define mmSDMA0_RLC4_RB_RPTR 0x02c3 717 + #define mmSDMA0_RLC4_RB_RPTR_BASE_IDX 0 718 + #define mmSDMA0_RLC4_RB_RPTR_HI 0x02c4 719 + #define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX 0 720 + #define mmSDMA0_RLC4_RB_WPTR 0x02c5 721 + #define mmSDMA0_RLC4_RB_WPTR_BASE_IDX 0 722 + #define mmSDMA0_RLC4_RB_WPTR_HI 0x02c6 723 + #define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX 0 724 + #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x02c7 725 + #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 726 + #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI 0x02c8 727 + #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 728 + #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO 0x02c9 729 + #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 730 + #define mmSDMA0_RLC4_IB_CNTL 0x02ca 731 + #define mmSDMA0_RLC4_IB_CNTL_BASE_IDX 0 732 + #define mmSDMA0_RLC4_IB_RPTR 0x02cb 733 + #define mmSDMA0_RLC4_IB_RPTR_BASE_IDX 0 734 + #define mmSDMA0_RLC4_IB_OFFSET 0x02cc 735 + #define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX 0 736 + #define mmSDMA0_RLC4_IB_BASE_LO 0x02cd 737 + #define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX 0 738 + #define mmSDMA0_RLC4_IB_BASE_HI 0x02ce 739 + #define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX 0 740 + #define mmSDMA0_RLC4_IB_SIZE 0x02cf 741 + #define mmSDMA0_RLC4_IB_SIZE_BASE_IDX 0 742 + #define mmSDMA0_RLC4_SKIP_CNTL 0x02d0 743 + #define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX 0 744 + #define mmSDMA0_RLC4_CONTEXT_STATUS 0x02d1 745 + #define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX 0 746 + #define mmSDMA0_RLC4_DOORBELL 0x02d2 747 + #define mmSDMA0_RLC4_DOORBELL_BASE_IDX 0 748 + #define mmSDMA0_RLC4_STATUS 0x02e8 749 + #define mmSDMA0_RLC4_STATUS_BASE_IDX 0 750 + #define mmSDMA0_RLC4_DOORBELL_LOG 0x02e9 751 + #define mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX 0 752 + #define mmSDMA0_RLC4_WATERMARK 0x02ea 753 + #define mmSDMA0_RLC4_WATERMARK_BASE_IDX 0 754 + #define mmSDMA0_RLC4_DOORBELL_OFFSET 0x02eb 755 + #define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX 0 756 + #define mmSDMA0_RLC4_CSA_ADDR_LO 0x02ec 757 + #define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX 0 758 + #define mmSDMA0_RLC4_CSA_ADDR_HI 0x02ed 759 + #define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX 0 760 + #define mmSDMA0_RLC4_IB_SUB_REMAIN 0x02ef 761 + #define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX 0 762 + #define mmSDMA0_RLC4_PREEMPT 0x02f0 763 + #define mmSDMA0_RLC4_PREEMPT_BASE_IDX 0 764 + #define mmSDMA0_RLC4_DUMMY_REG 0x02f1 765 + #define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX 0 766 + #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0x02f2 767 + #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 768 + #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0x02f3 769 + #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 770 + #define mmSDMA0_RLC4_RB_AQL_CNTL 0x02f4 771 + #define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX 0 772 + #define mmSDMA0_RLC4_MINOR_PTR_UPDATE 0x02f5 773 + #define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 774 + #define mmSDMA0_RLC4_MIDCMD_DATA0 0x0300 775 + #define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX 0 776 + #define mmSDMA0_RLC4_MIDCMD_DATA1 0x0301 777 + #define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX 0 778 + #define mmSDMA0_RLC4_MIDCMD_DATA2 0x0302 779 + #define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX 0 780 + #define mmSDMA0_RLC4_MIDCMD_DATA3 0x0303 781 + #define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX 0 782 + #define mmSDMA0_RLC4_MIDCMD_DATA4 0x0304 783 + #define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX 0 784 + #define mmSDMA0_RLC4_MIDCMD_DATA5 0x0305 785 + #define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX 0 786 + #define mmSDMA0_RLC4_MIDCMD_DATA6 0x0306 787 + #define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX 0 788 + #define mmSDMA0_RLC4_MIDCMD_DATA7 0x0307 789 + #define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX 0 790 + #define mmSDMA0_RLC4_MIDCMD_DATA8 0x0308 791 + #define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX 0 792 + #define mmSDMA0_RLC4_MIDCMD_CNTL 0x0309 793 + #define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX 0 794 + #define mmSDMA0_RLC5_RB_CNTL 0x0320 795 + #define mmSDMA0_RLC5_RB_CNTL_BASE_IDX 0 796 + #define mmSDMA0_RLC5_RB_BASE 0x0321 797 + #define mmSDMA0_RLC5_RB_BASE_BASE_IDX 0 798 + #define mmSDMA0_RLC5_RB_BASE_HI 0x0322 799 + #define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX 0 800 + #define mmSDMA0_RLC5_RB_RPTR 0x0323 801 + #define mmSDMA0_RLC5_RB_RPTR_BASE_IDX 0 802 + #define mmSDMA0_RLC5_RB_RPTR_HI 0x0324 803 + #define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX 0 804 + #define mmSDMA0_RLC5_RB_WPTR 0x0325 805 + #define mmSDMA0_RLC5_RB_WPTR_BASE_IDX 0 806 + #define mmSDMA0_RLC5_RB_WPTR_HI 0x0326 807 + #define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX 0 808 + #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x0327 809 + #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 810 + #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI 0x0328 811 + #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 812 + #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO 0x0329 813 + #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 814 + #define mmSDMA0_RLC5_IB_CNTL 0x032a 815 + #define mmSDMA0_RLC5_IB_CNTL_BASE_IDX 0 816 + #define mmSDMA0_RLC5_IB_RPTR 0x032b 817 + #define mmSDMA0_RLC5_IB_RPTR_BASE_IDX 0 818 + #define mmSDMA0_RLC5_IB_OFFSET 0x032c 819 + #define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX 0 820 + #define mmSDMA0_RLC5_IB_BASE_LO 0x032d 821 + #define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX 0 822 + #define mmSDMA0_RLC5_IB_BASE_HI 0x032e 823 + #define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX 0 824 + #define mmSDMA0_RLC5_IB_SIZE 0x032f 825 + #define mmSDMA0_RLC5_IB_SIZE_BASE_IDX 0 826 + #define mmSDMA0_RLC5_SKIP_CNTL 0x0330 827 + #define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX 0 828 + #define mmSDMA0_RLC5_CONTEXT_STATUS 0x0331 829 + #define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX 0 830 + #define mmSDMA0_RLC5_DOORBELL 0x0332 831 + #define mmSDMA0_RLC5_DOORBELL_BASE_IDX 0 832 + #define mmSDMA0_RLC5_STATUS 0x0348 833 + #define mmSDMA0_RLC5_STATUS_BASE_IDX 0 834 + #define mmSDMA0_RLC5_DOORBELL_LOG 0x0349 835 + #define mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX 0 836 + #define mmSDMA0_RLC5_WATERMARK 0x034a 837 + #define mmSDMA0_RLC5_WATERMARK_BASE_IDX 0 838 + #define mmSDMA0_RLC5_DOORBELL_OFFSET 0x034b 839 + #define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX 0 840 + #define mmSDMA0_RLC5_CSA_ADDR_LO 0x034c 841 + #define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX 0 842 + #define mmSDMA0_RLC5_CSA_ADDR_HI 0x034d 843 + #define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX 0 844 + #define mmSDMA0_RLC5_IB_SUB_REMAIN 0x034f 845 + #define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX 0 846 + #define mmSDMA0_RLC5_PREEMPT 0x0350 847 + #define mmSDMA0_RLC5_PREEMPT_BASE_IDX 0 848 + #define mmSDMA0_RLC5_DUMMY_REG 0x0351 849 + #define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX 0 850 + #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0x0352 851 + #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 852 + #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0x0353 853 + #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 854 + #define mmSDMA0_RLC5_RB_AQL_CNTL 0x0354 855 + #define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX 0 856 + #define mmSDMA0_RLC5_MINOR_PTR_UPDATE 0x0355 857 + #define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 858 + #define mmSDMA0_RLC5_MIDCMD_DATA0 0x0360 859 + #define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX 0 860 + #define mmSDMA0_RLC5_MIDCMD_DATA1 0x0361 861 + #define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX 0 862 + #define mmSDMA0_RLC5_MIDCMD_DATA2 0x0362 863 + #define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX 0 864 + #define mmSDMA0_RLC5_MIDCMD_DATA3 0x0363 865 + #define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX 0 866 + #define mmSDMA0_RLC5_MIDCMD_DATA4 0x0364 867 + #define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX 0 868 + #define mmSDMA0_RLC5_MIDCMD_DATA5 0x0365 869 + #define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX 0 870 + #define mmSDMA0_RLC5_MIDCMD_DATA6 0x0366 871 + #define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX 0 872 + #define mmSDMA0_RLC5_MIDCMD_DATA7 0x0367 873 + #define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX 0 874 + #define mmSDMA0_RLC5_MIDCMD_DATA8 0x0368 875 + #define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX 0 876 + #define mmSDMA0_RLC5_MIDCMD_CNTL 0x0369 877 + #define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX 0 878 + #define mmSDMA0_RLC6_RB_CNTL 0x0380 879 + #define mmSDMA0_RLC6_RB_CNTL_BASE_IDX 0 880 + #define mmSDMA0_RLC6_RB_BASE 0x0381 881 + #define mmSDMA0_RLC6_RB_BASE_BASE_IDX 0 882 + #define mmSDMA0_RLC6_RB_BASE_HI 0x0382 883 + #define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX 0 884 + #define mmSDMA0_RLC6_RB_RPTR 0x0383 885 + #define mmSDMA0_RLC6_RB_RPTR_BASE_IDX 0 886 + #define mmSDMA0_RLC6_RB_RPTR_HI 0x0384 887 + #define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX 0 888 + #define mmSDMA0_RLC6_RB_WPTR 0x0385 889 + #define mmSDMA0_RLC6_RB_WPTR_BASE_IDX 0 890 + #define mmSDMA0_RLC6_RB_WPTR_HI 0x0386 891 + #define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX 0 892 + #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL 0x0387 893 + #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 894 + #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI 0x0388 895 + #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 896 + #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO 0x0389 897 + #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 898 + #define mmSDMA0_RLC6_IB_CNTL 0x038a 899 + #define mmSDMA0_RLC6_IB_CNTL_BASE_IDX 0 900 + #define mmSDMA0_RLC6_IB_RPTR 0x038b 901 + #define mmSDMA0_RLC6_IB_RPTR_BASE_IDX 0 902 + #define mmSDMA0_RLC6_IB_OFFSET 0x038c 903 + #define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX 0 904 + #define mmSDMA0_RLC6_IB_BASE_LO 0x038d 905 + #define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX 0 906 + #define mmSDMA0_RLC6_IB_BASE_HI 0x038e 907 + #define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX 0 908 + #define mmSDMA0_RLC6_IB_SIZE 0x038f 909 + #define mmSDMA0_RLC6_IB_SIZE_BASE_IDX 0 910 + #define mmSDMA0_RLC6_SKIP_CNTL 0x0390 911 + #define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX 0 912 + #define mmSDMA0_RLC6_CONTEXT_STATUS 0x0391 913 + #define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX 0 914 + #define mmSDMA0_RLC6_DOORBELL 0x0392 915 + #define mmSDMA0_RLC6_DOORBELL_BASE_IDX 0 916 + #define mmSDMA0_RLC6_STATUS 0x03a8 917 + #define mmSDMA0_RLC6_STATUS_BASE_IDX 0 918 + #define mmSDMA0_RLC6_DOORBELL_LOG 0x03a9 919 + #define mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX 0 920 + #define mmSDMA0_RLC6_WATERMARK 0x03aa 921 + #define mmSDMA0_RLC6_WATERMARK_BASE_IDX 0 922 + #define mmSDMA0_RLC6_DOORBELL_OFFSET 0x03ab 923 + #define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX 0 924 + #define mmSDMA0_RLC6_CSA_ADDR_LO 0x03ac 925 + #define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX 0 926 + #define mmSDMA0_RLC6_CSA_ADDR_HI 0x03ad 927 + #define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX 0 928 + #define mmSDMA0_RLC6_IB_SUB_REMAIN 0x03af 929 + #define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX 0 930 + #define mmSDMA0_RLC6_PREEMPT 0x03b0 931 + #define mmSDMA0_RLC6_PREEMPT_BASE_IDX 0 932 + #define mmSDMA0_RLC6_DUMMY_REG 0x03b1 933 + #define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX 0 934 + #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0x03b2 935 + #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 936 + #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0x03b3 937 + #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 938 + #define mmSDMA0_RLC6_RB_AQL_CNTL 0x03b4 939 + #define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX 0 940 + #define mmSDMA0_RLC6_MINOR_PTR_UPDATE 0x03b5 941 + #define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 942 + #define mmSDMA0_RLC6_MIDCMD_DATA0 0x03c0 943 + #define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX 0 944 + #define mmSDMA0_RLC6_MIDCMD_DATA1 0x03c1 945 + #define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX 0 946 + #define mmSDMA0_RLC6_MIDCMD_DATA2 0x03c2 947 + #define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX 0 948 + #define mmSDMA0_RLC6_MIDCMD_DATA3 0x03c3 949 + #define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX 0 950 + #define mmSDMA0_RLC6_MIDCMD_DATA4 0x03c4 951 + #define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX 0 952 + #define mmSDMA0_RLC6_MIDCMD_DATA5 0x03c5 953 + #define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX 0 954 + #define mmSDMA0_RLC6_MIDCMD_DATA6 0x03c6 955 + #define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX 0 956 + #define mmSDMA0_RLC6_MIDCMD_DATA7 0x03c7 957 + #define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX 0 958 + #define mmSDMA0_RLC6_MIDCMD_DATA8 0x03c8 959 + #define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX 0 960 + #define mmSDMA0_RLC6_MIDCMD_CNTL 0x03c9 961 + #define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX 0 962 + #define mmSDMA0_RLC7_RB_CNTL 0x03e0 963 + #define mmSDMA0_RLC7_RB_CNTL_BASE_IDX 0 964 + #define mmSDMA0_RLC7_RB_BASE 0x03e1 965 + #define mmSDMA0_RLC7_RB_BASE_BASE_IDX 0 966 + #define mmSDMA0_RLC7_RB_BASE_HI 0x03e2 967 + #define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX 0 968 + #define mmSDMA0_RLC7_RB_RPTR 0x03e3 969 + #define mmSDMA0_RLC7_RB_RPTR_BASE_IDX 0 970 + #define mmSDMA0_RLC7_RB_RPTR_HI 0x03e4 971 + #define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX 0 972 + #define mmSDMA0_RLC7_RB_WPTR 0x03e5 973 + #define mmSDMA0_RLC7_RB_WPTR_BASE_IDX 0 974 + #define mmSDMA0_RLC7_RB_WPTR_HI 0x03e6 975 + #define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX 0 976 + #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL 0x03e7 977 + #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 978 + #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI 0x03e8 979 + #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 980 + #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO 0x03e9 981 + #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 982 + #define mmSDMA0_RLC7_IB_CNTL 0x03ea 983 + #define mmSDMA0_RLC7_IB_CNTL_BASE_IDX 0 984 + #define mmSDMA0_RLC7_IB_RPTR 0x03eb 985 + #define mmSDMA0_RLC7_IB_RPTR_BASE_IDX 0 986 + #define mmSDMA0_RLC7_IB_OFFSET 0x03ec 987 + #define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX 0 988 + #define mmSDMA0_RLC7_IB_BASE_LO 0x03ed 989 + #define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX 0 990 + #define mmSDMA0_RLC7_IB_BASE_HI 0x03ee 991 + #define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX 0 992 + #define mmSDMA0_RLC7_IB_SIZE 0x03ef 993 + #define mmSDMA0_RLC7_IB_SIZE_BASE_IDX 0 994 + #define mmSDMA0_RLC7_SKIP_CNTL 0x03f0 995 + #define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX 0 996 + #define mmSDMA0_RLC7_CONTEXT_STATUS 0x03f1 997 + #define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX 0 998 + #define mmSDMA0_RLC7_DOORBELL 0x03f2 999 + #define mmSDMA0_RLC7_DOORBELL_BASE_IDX 0 1000 + #define mmSDMA0_RLC7_STATUS 0x0408 1001 + #define mmSDMA0_RLC7_STATUS_BASE_IDX 0 1002 + #define mmSDMA0_RLC7_DOORBELL_LOG 0x0409 1003 + #define mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX 0 1004 + #define mmSDMA0_RLC7_WATERMARK 0x040a 1005 + #define mmSDMA0_RLC7_WATERMARK_BASE_IDX 0 1006 + #define mmSDMA0_RLC7_DOORBELL_OFFSET 0x040b 1007 + #define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX 0 1008 + #define mmSDMA0_RLC7_CSA_ADDR_LO 0x040c 1009 + #define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX 0 1010 + #define mmSDMA0_RLC7_CSA_ADDR_HI 0x040d 1011 + #define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX 0 1012 + #define mmSDMA0_RLC7_IB_SUB_REMAIN 0x040f 1013 + #define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX 0 1014 + #define mmSDMA0_RLC7_PREEMPT 0x0410 1015 + #define mmSDMA0_RLC7_PREEMPT_BASE_IDX 0 1016 + #define mmSDMA0_RLC7_DUMMY_REG 0x0411 1017 + #define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX 0 1018 + #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0x0412 1019 + #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 1020 + #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0x0413 1021 + #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 1022 + #define mmSDMA0_RLC7_RB_AQL_CNTL 0x0414 1023 + #define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX 0 1024 + #define mmSDMA0_RLC7_MINOR_PTR_UPDATE 0x0415 1025 + #define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 1026 + #define mmSDMA0_RLC7_MIDCMD_DATA0 0x0420 1027 + #define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX 0 1028 + #define mmSDMA0_RLC7_MIDCMD_DATA1 0x0421 1029 + #define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX 0 1030 + #define mmSDMA0_RLC7_MIDCMD_DATA2 0x0422 1031 + #define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX 0 1032 + #define mmSDMA0_RLC7_MIDCMD_DATA3 0x0423 1033 + #define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX 0 1034 + #define mmSDMA0_RLC7_MIDCMD_DATA4 0x0424 1035 + #define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX 0 1036 + #define mmSDMA0_RLC7_MIDCMD_DATA5 0x0425 1037 + #define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX 0 1038 + #define mmSDMA0_RLC7_MIDCMD_DATA6 0x0426 1039 + #define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX 0 1040 + #define mmSDMA0_RLC7_MIDCMD_DATA7 0x0427 1041 + #define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX 0 1042 + #define mmSDMA0_RLC7_MIDCMD_DATA8 0x0428 1043 + #define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX 0 1044 + #define mmSDMA0_RLC7_MIDCMD_CNTL 0x0429 1045 + #define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX 0 1046 + 1047 + #endif
+2992
drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h
··· 1 + /* 2 + * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _sdma0_4_2_0_SH_MASK_HEADER 22 + #define _sdma0_4_2_0_SH_MASK_HEADER 23 + 24 + 25 + // addressBlock: sdma0_sdma0dec 26 + //SDMA0_UCODE_ADDR 27 + #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 28 + #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29 + //SDMA0_UCODE_DATA 30 + #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 31 + #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32 + //SDMA0_VM_CNTL 33 + #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 34 + #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 35 + //SDMA0_VM_CTX_LO 36 + #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 37 + #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38 + //SDMA0_VM_CTX_HI 39 + #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 40 + #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41 + //SDMA0_ACTIVE_FCN_ID 42 + #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43 + #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44 + #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45 + #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46 + #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47 + #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48 + //SDMA0_VM_CTX_CNTL 49 + #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 50 + #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 51 + #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52 + #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53 + //SDMA0_VIRT_RESET_REQ 54 + #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 55 + #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 56 + #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57 + #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 58 + //SDMA0_VF_ENABLE 59 + #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 60 + #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 61 + //SDMA0_CONTEXT_REG_TYPE0 62 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 63 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 64 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 65 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 66 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 67 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 68 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 69 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 70 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 71 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 72 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 73 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 74 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 75 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 76 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 77 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 78 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 79 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 80 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 81 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 82 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 83 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 84 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 85 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 86 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 87 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 88 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 89 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 90 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 91 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 92 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 93 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 94 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 95 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 96 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 97 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 98 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 99 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 100 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 101 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 102 + //SDMA0_CONTEXT_REG_TYPE1 103 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 104 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 105 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 106 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 107 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 108 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 109 + #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 110 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 111 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 112 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 113 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 114 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 115 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 116 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 117 + #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 118 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 119 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 120 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 121 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 122 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 123 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 124 + #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 125 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 126 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 127 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 128 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 129 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 130 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 131 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 132 + #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 133 + //SDMA0_CONTEXT_REG_TYPE2 134 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 135 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 136 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 137 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 138 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 139 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 140 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 141 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 142 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 143 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 144 + #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 145 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 146 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 147 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 148 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 149 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 150 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 151 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 152 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 153 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 154 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 155 + #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 156 + //SDMA0_CONTEXT_REG_TYPE3 157 + #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 158 + #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 159 + //SDMA0_PUB_REG_TYPE0 160 + #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 161 + #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 162 + #define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 163 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 164 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 165 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 166 + #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 167 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 168 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 169 + #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 170 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 171 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 172 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 173 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 174 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 175 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 176 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 177 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 178 + #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 179 + #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 180 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 181 + #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 182 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 183 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 184 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 185 + #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 186 + #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 187 + #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 188 + #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 189 + #define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 190 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 191 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 192 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 193 + #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 194 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 195 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 196 + #define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 197 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 198 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 199 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 200 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 201 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 202 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 203 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 204 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 205 + #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 206 + #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 207 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 208 + #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 209 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 210 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 211 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 212 + #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 213 + #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 214 + //SDMA0_PUB_REG_TYPE1 215 + #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 216 + #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 217 + #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 218 + #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 219 + #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 220 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 221 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 222 + #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 223 + #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 224 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 225 + #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 226 + #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 227 + #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 228 + #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 229 + #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 230 + #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 231 + #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 232 + #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 233 + #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 234 + #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 235 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 236 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 237 + #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 238 + #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 239 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 240 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 241 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 242 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 243 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 244 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 245 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 246 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 247 + #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 248 + #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 249 + #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 250 + #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 251 + #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 252 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 253 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 254 + #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 255 + #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 256 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 257 + #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 258 + #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 259 + #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 260 + #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 261 + #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 262 + #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 263 + #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 264 + #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 265 + #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 266 + #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 267 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 268 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 269 + #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 270 + #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 271 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 272 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 273 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 274 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 275 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 276 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 277 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 278 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 279 + //SDMA0_PUB_REG_TYPE2 280 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 281 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 282 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 283 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 284 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 285 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 286 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 287 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 288 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 289 + #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 290 + #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 291 + #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 292 + #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 293 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 294 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 295 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf 296 + #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 297 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 298 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 299 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 300 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 301 + #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 302 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 303 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 304 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 305 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 306 + #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 307 + #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 308 + #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 309 + #define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 310 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 311 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 312 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 313 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 314 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 315 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 316 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 317 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 318 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 319 + #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 320 + #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 321 + #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 322 + #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 323 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 324 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 325 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L 326 + #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 327 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 328 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 329 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 330 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 331 + #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 332 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 333 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 334 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 335 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 336 + #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 337 + #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 338 + #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 339 + #define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 340 + //SDMA0_PUB_REG_TYPE3 341 + #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 342 + #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 343 + #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 344 + #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 345 + #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 346 + #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 347 + //SDMA0_MMHUB_CNTL 348 + #define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 349 + #define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 350 + //SDMA0_CONTEXT_GROUP_BOUNDARY 351 + #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 352 + #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 353 + //SDMA0_POWER_CNTL 354 + #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 355 + #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 356 + #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 357 + #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 358 + #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 359 + #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 360 + #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 361 + #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 362 + #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 363 + #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 364 + #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 365 + #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 366 + #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 367 + #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 368 + #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 369 + #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 370 + #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 371 + #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 372 + #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 373 + #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 374 + //SDMA0_CLK_CTRL 375 + #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 376 + #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 377 + #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 378 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 379 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 380 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 381 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 382 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 383 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 384 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 385 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 386 + #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 387 + #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 388 + #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 389 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 390 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 391 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 392 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 393 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 394 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 395 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 396 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 397 + //SDMA0_CNTL 398 + #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 399 + #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 400 + #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 401 + #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 402 + #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 403 + #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 404 + #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 405 + #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 406 + #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 407 + #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 408 + #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 409 + #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 410 + #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 411 + #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 412 + #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 413 + #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 414 + #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 415 + #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 416 + #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 417 + #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 418 + #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 419 + #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 420 + //SDMA0_CHICKEN_BITS 421 + #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 422 + #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 423 + #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 424 + #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 425 + #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 426 + #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 427 + #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 428 + #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 429 + #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 430 + #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 431 + #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 432 + #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 433 + #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 434 + #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 435 + #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 436 + #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 437 + #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 438 + #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 439 + #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 440 + #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 441 + #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 442 + #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 443 + #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 444 + #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 445 + #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 446 + #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 447 + //SDMA0_GB_ADDR_CONFIG 448 + #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 449 + #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 450 + #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 451 + #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 452 + #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 453 + #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 454 + #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 455 + #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 456 + #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 457 + #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 458 + //SDMA0_GB_ADDR_CONFIG_READ 459 + #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 460 + #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 461 + #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 462 + #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 463 + #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 464 + #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 465 + #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 466 + #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 467 + #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 468 + #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 469 + //SDMA0_RB_RPTR_FETCH_HI 470 + #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 471 + #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 472 + //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 473 + #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 474 + #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 475 + //SDMA0_RB_RPTR_FETCH 476 + #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 477 + #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 478 + //SDMA0_IB_OFFSET_FETCH 479 + #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 480 + #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 481 + //SDMA0_PROGRAM 482 + #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 483 + #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 484 + //SDMA0_STATUS_REG 485 + #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 486 + #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 487 + #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 488 + #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 489 + #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 490 + #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 491 + #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 492 + #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 493 + #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 494 + #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 495 + #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 496 + #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 497 + #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 498 + #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 499 + #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 500 + #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 501 + #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 502 + #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 503 + #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 504 + #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 505 + #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 506 + #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 507 + #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 508 + #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 509 + #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 510 + #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 511 + #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 512 + #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 513 + #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 514 + #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 515 + #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 516 + #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 517 + #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 518 + #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 519 + #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 520 + #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 521 + #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 522 + #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 523 + #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 524 + #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 525 + #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 526 + #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 527 + #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 528 + #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 529 + #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 530 + #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 531 + #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 532 + #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 533 + #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 534 + #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 535 + #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 536 + #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 537 + #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 538 + #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 539 + #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 540 + #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 541 + #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 542 + #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 543 + //SDMA0_STATUS1_REG 544 + #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 545 + #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 546 + #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 547 + #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 548 + #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 549 + #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 550 + #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 551 + #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 552 + #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 553 + #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 554 + #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 555 + #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 556 + #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 557 + #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 558 + #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 559 + #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 560 + #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 561 + #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 562 + #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 563 + #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 564 + #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 565 + #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 566 + #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 567 + #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 568 + #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 569 + #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 570 + #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 571 + #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 572 + //SDMA0_RD_BURST_CNTL 573 + #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 574 + #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 575 + #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 576 + #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 577 + //SDMA0_HBM_PAGE_CONFIG 578 + #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 579 + #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 580 + //SDMA0_UCODE_CHECKSUM 581 + #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 582 + #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 583 + //SDMA0_F32_CNTL 584 + #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 585 + #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 586 + #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 587 + #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 588 + //SDMA0_FREEZE 589 + #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 590 + #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 591 + #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 592 + #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 593 + #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 594 + #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 595 + #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 596 + #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 597 + //SDMA0_PHASE0_QUANTUM 598 + #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 599 + #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 600 + #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 601 + #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 602 + #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 603 + #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 604 + //SDMA0_PHASE1_QUANTUM 605 + #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 606 + #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 607 + #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 608 + #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 609 + #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 610 + #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 611 + //SDMA_POWER_GATING 612 + #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 613 + #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 614 + #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 615 + #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 616 + #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 617 + #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 618 + #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 619 + #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 620 + #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 621 + #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 622 + //SDMA_PGFSM_CONFIG 623 + #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 624 + #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 625 + #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 626 + #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 627 + #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 628 + #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 629 + #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 630 + #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 631 + #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 632 + #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 633 + #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 634 + #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 635 + #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 636 + #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 637 + #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 638 + #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 639 + #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 640 + #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 641 + //SDMA_PGFSM_WRITE 642 + #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 643 + #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 644 + //SDMA_PGFSM_READ 645 + #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 646 + #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 647 + //SDMA0_EDC_CONFIG 648 + #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 649 + #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 650 + #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 651 + #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 652 + //SDMA0_BA_THRESHOLD 653 + #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 654 + #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 655 + #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 656 + #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 657 + //SDMA0_ID 658 + #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 659 + #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 660 + //SDMA0_VERSION 661 + #define SDMA0_VERSION__MINVER__SHIFT 0x0 662 + #define SDMA0_VERSION__MAJVER__SHIFT 0x8 663 + #define SDMA0_VERSION__REV__SHIFT 0x10 664 + #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 665 + #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 666 + #define SDMA0_VERSION__REV_MASK 0x003F0000L 667 + //SDMA0_EDC_COUNTER 668 + #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 669 + #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 670 + #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 671 + #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 672 + #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 673 + #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 674 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 675 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 676 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 677 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 678 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 679 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 680 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 681 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 682 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf 683 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 684 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 685 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 686 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 687 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 688 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 689 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 690 + #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 691 + #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 692 + #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L 693 + #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 694 + #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 695 + #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 696 + #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 697 + #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 698 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 699 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 700 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 701 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 702 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 703 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 704 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 705 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 706 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L 707 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L 708 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L 709 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L 710 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L 711 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L 712 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L 713 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L 714 + #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L 715 + #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L 716 + //SDMA0_EDC_COUNTER_CLEAR 717 + #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 718 + #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 719 + //SDMA0_STATUS2_REG 720 + #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 721 + #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 722 + #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 723 + #define SDMA0_STATUS2_REG__ID_MASK 0x00000003L 724 + #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 725 + #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 726 + //SDMA0_ATOMIC_CNTL 727 + #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 728 + #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 729 + #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 730 + #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 731 + //SDMA0_ATOMIC_PREOP_LO 732 + #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 733 + #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 734 + //SDMA0_ATOMIC_PREOP_HI 735 + #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 736 + #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 737 + //SDMA0_UTCL1_CNTL 738 + #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 739 + #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 740 + #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 741 + #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 742 + #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 743 + #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 744 + #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 745 + #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 746 + #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 747 + #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 748 + #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 749 + #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 750 + //SDMA0_UTCL1_WATERMK 751 + #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 752 + #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 753 + #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 754 + #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 755 + #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL 756 + #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L 757 + #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L 758 + #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L 759 + //SDMA0_UTCL1_RD_STATUS 760 + #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 761 + #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 762 + #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 763 + #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 764 + #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 765 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 766 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 767 + #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 768 + #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 769 + #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 770 + #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 771 + #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 772 + #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 773 + #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 774 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 775 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 776 + #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 777 + #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 778 + #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 779 + #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 780 + #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 781 + #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 782 + #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 783 + #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 784 + #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 785 + #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 786 + #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 787 + #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 788 + #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 789 + #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 790 + #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 791 + #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 792 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 793 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 794 + #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 795 + #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 796 + #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 797 + #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 798 + #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 799 + #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 800 + #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 801 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 802 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 803 + #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 804 + #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 805 + #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 806 + #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 807 + #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 808 + #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 809 + #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 810 + #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 811 + #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 812 + #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 813 + #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 814 + //SDMA0_UTCL1_WR_STATUS 815 + #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 816 + #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 817 + #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 818 + #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 819 + #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 820 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 821 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 822 + #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 823 + #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 824 + #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 825 + #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 826 + #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 827 + #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 828 + #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 829 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 830 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 831 + #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 832 + #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 833 + #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 834 + #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 835 + #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 836 + #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 837 + #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 838 + #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 839 + #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 840 + #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 841 + #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 842 + #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 843 + #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 844 + #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 845 + #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 846 + #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 847 + #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 848 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 849 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 850 + #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 851 + #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 852 + #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 853 + #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 854 + #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 855 + #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 856 + #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 857 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 858 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 859 + #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 860 + #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 861 + #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 862 + #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 863 + #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 864 + #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 865 + #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 866 + #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 867 + #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 868 + #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 869 + #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 870 + #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 871 + //SDMA0_UTCL1_INV0 872 + #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 873 + #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 874 + #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 875 + #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 876 + #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 877 + #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 878 + #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 879 + #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 880 + #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 881 + #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 882 + #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 883 + #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 884 + #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 885 + #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 886 + #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 887 + #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 888 + #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 889 + #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 890 + #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 891 + #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 892 + #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 893 + #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 894 + #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 895 + #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 896 + #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 897 + #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 898 + #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 899 + #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 900 + //SDMA0_UTCL1_INV1 901 + #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 902 + #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 903 + //SDMA0_UTCL1_INV2 904 + #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 905 + #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 906 + //SDMA0_UTCL1_RD_XNACK0 907 + #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 908 + #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 909 + //SDMA0_UTCL1_RD_XNACK1 910 + #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 911 + #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 912 + #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 913 + #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 914 + #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 915 + #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 916 + #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 917 + #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 918 + //SDMA0_UTCL1_WR_XNACK0 919 + #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 920 + #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 921 + //SDMA0_UTCL1_WR_XNACK1 922 + #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 923 + #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 924 + #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 925 + #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 926 + #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 927 + #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 928 + #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 929 + #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 930 + //SDMA0_UTCL1_TIMEOUT 931 + #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 932 + #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 933 + #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 934 + #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 935 + //SDMA0_UTCL1_PAGE 936 + #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 937 + #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 938 + #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 939 + #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 940 + #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 941 + #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 942 + #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 943 + #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 944 + //SDMA0_POWER_CNTL_IDLE 945 + #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 946 + #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 947 + #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 948 + #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 949 + #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 950 + #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 951 + //SDMA0_RELAX_ORDERING_LUT 952 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 953 + #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 954 + #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 955 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 956 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 957 + #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 958 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 959 + #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 960 + #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 961 + #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 962 + #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 963 + #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 964 + #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 965 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 966 + #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 967 + #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 968 + #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 969 + #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 970 + #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 971 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 972 + #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 973 + #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 974 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 975 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 976 + #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 977 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 978 + #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 979 + #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 980 + #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 981 + #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 982 + #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 983 + #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 984 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 985 + #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 986 + #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 987 + #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 988 + #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 989 + #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 990 + //SDMA0_CHICKEN_BITS_2 991 + #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 992 + #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 993 + //SDMA0_STATUS3_REG 994 + #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 995 + #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 996 + #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 997 + #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 998 + #define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 999 + #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 1000 + #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 1001 + #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 1002 + #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 1003 + #define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 1004 + //SDMA0_PHYSICAL_ADDR_LO 1005 + #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 1006 + #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 1007 + #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 1008 + #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 1009 + #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 1010 + #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 1011 + #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 1012 + #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 1013 + //SDMA0_PHYSICAL_ADDR_HI 1014 + #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 1015 + #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 1016 + //SDMA0_PHASE2_QUANTUM 1017 + #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 1018 + #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 1019 + #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 1020 + #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 1021 + #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 1022 + #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 1023 + //SDMA0_ERROR_LOG 1024 + #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 1025 + #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 1026 + #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 1027 + #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 1028 + //SDMA0_PUB_DUMMY_REG0 1029 + #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 1030 + #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 1031 + //SDMA0_PUB_DUMMY_REG1 1032 + #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 1033 + #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 1034 + //SDMA0_PUB_DUMMY_REG2 1035 + #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 1036 + #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 1037 + //SDMA0_PUB_DUMMY_REG3 1038 + #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1039 + #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1040 + //SDMA0_F32_COUNTER 1041 + #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 1042 + #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1043 + //SDMA0_PERFMON_CNTL 1044 + #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1045 + #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1046 + #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1047 + #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1048 + #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1049 + #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1050 + #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1051 + #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1052 + #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1053 + #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1054 + #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1055 + #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1056 + //SDMA0_PERFCOUNTER0_RESULT 1057 + #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1058 + #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1059 + //SDMA0_PERFCOUNTER1_RESULT 1060 + #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1061 + #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1062 + //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 1063 + #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1064 + #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1065 + #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1066 + #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1067 + #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1068 + #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1069 + //SDMA0_CRD_CNTL 1070 + #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1071 + #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1072 + #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1073 + #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1074 + //SDMA0_GPU_IOV_VIOLATION_LOG 1075 + #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1076 + #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1077 + #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1078 + #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1079 + #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1080 + #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1081 + #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1082 + #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1083 + #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1084 + #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1085 + #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1086 + #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1087 + #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1088 + #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1089 + //SDMA0_ULV_CNTL 1090 + #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1091 + #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 1092 + #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 1093 + #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1094 + #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1095 + #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1096 + #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1097 + #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 1098 + #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 1099 + #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1100 + #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1101 + #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1102 + //SDMA0_EA_DBIT_ADDR_DATA 1103 + #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1104 + #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1105 + //SDMA0_EA_DBIT_ADDR_INDEX 1106 + #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1107 + #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1108 + //SDMA0_GFX_RB_CNTL 1109 + #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1110 + #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1111 + #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1112 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1113 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1114 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1115 + #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1116 + #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1117 + #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1118 + #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1119 + #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1120 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1121 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1122 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1123 + #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1124 + #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1125 + //SDMA0_GFX_RB_BASE 1126 + #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1127 + #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1128 + //SDMA0_GFX_RB_BASE_HI 1129 + #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1130 + #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1131 + //SDMA0_GFX_RB_RPTR 1132 + #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1133 + #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1134 + //SDMA0_GFX_RB_RPTR_HI 1135 + #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1136 + #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1137 + //SDMA0_GFX_RB_WPTR 1138 + #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1139 + #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1140 + //SDMA0_GFX_RB_WPTR_HI 1141 + #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1142 + #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1143 + //SDMA0_GFX_RB_WPTR_POLL_CNTL 1144 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1145 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1146 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1147 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1148 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1149 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1150 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1151 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1152 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1153 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1154 + //SDMA0_GFX_RB_RPTR_ADDR_HI 1155 + #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1156 + #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1157 + //SDMA0_GFX_RB_RPTR_ADDR_LO 1158 + #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1159 + #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1160 + #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1161 + #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1162 + //SDMA0_GFX_IB_CNTL 1163 + #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1164 + #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1165 + #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1166 + #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1167 + #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1168 + #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1169 + #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1170 + #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1171 + //SDMA0_GFX_IB_RPTR 1172 + #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1173 + #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1174 + //SDMA0_GFX_IB_OFFSET 1175 + #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1176 + #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1177 + //SDMA0_GFX_IB_BASE_LO 1178 + #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1179 + #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1180 + //SDMA0_GFX_IB_BASE_HI 1181 + #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1182 + #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1183 + //SDMA0_GFX_IB_SIZE 1184 + #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1185 + #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1186 + //SDMA0_GFX_SKIP_CNTL 1187 + #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1188 + #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1189 + //SDMA0_GFX_CONTEXT_STATUS 1190 + #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1191 + #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1192 + #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1193 + #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1194 + #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1195 + #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1196 + #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1197 + #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1198 + #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1199 + #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1200 + #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1201 + #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1202 + #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1203 + #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1204 + #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1205 + #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1206 + //SDMA0_GFX_DOORBELL 1207 + #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1208 + #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1209 + #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1210 + #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1211 + //SDMA0_GFX_CONTEXT_CNTL 1212 + #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1213 + #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1214 + //SDMA0_GFX_STATUS 1215 + #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1216 + #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1217 + #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1218 + #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1219 + //SDMA0_GFX_DOORBELL_LOG 1220 + #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1221 + #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1222 + #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1223 + #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1224 + //SDMA0_GFX_WATERMARK 1225 + #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1226 + #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1227 + #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1228 + #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1229 + //SDMA0_GFX_DOORBELL_OFFSET 1230 + #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1231 + #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1232 + //SDMA0_GFX_CSA_ADDR_LO 1233 + #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1234 + #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1235 + //SDMA0_GFX_CSA_ADDR_HI 1236 + #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1237 + #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1238 + //SDMA0_GFX_IB_SUB_REMAIN 1239 + #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1240 + #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1241 + //SDMA0_GFX_PREEMPT 1242 + #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1243 + #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1244 + //SDMA0_GFX_DUMMY_REG 1245 + #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1246 + #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1247 + //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1248 + #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1249 + #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1250 + //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1251 + #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1252 + #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1253 + //SDMA0_GFX_RB_AQL_CNTL 1254 + #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1255 + #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1256 + #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1257 + #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1258 + #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1259 + #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1260 + //SDMA0_GFX_MINOR_PTR_UPDATE 1261 + #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1262 + #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1263 + //SDMA0_GFX_MIDCMD_DATA0 1264 + #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1265 + #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1266 + //SDMA0_GFX_MIDCMD_DATA1 1267 + #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1268 + #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1269 + //SDMA0_GFX_MIDCMD_DATA2 1270 + #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1271 + #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1272 + //SDMA0_GFX_MIDCMD_DATA3 1273 + #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1274 + #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1275 + //SDMA0_GFX_MIDCMD_DATA4 1276 + #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1277 + #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1278 + //SDMA0_GFX_MIDCMD_DATA5 1279 + #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1280 + #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1281 + //SDMA0_GFX_MIDCMD_DATA6 1282 + #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1283 + #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1284 + //SDMA0_GFX_MIDCMD_DATA7 1285 + #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1286 + #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1287 + //SDMA0_GFX_MIDCMD_DATA8 1288 + #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1289 + #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1290 + //SDMA0_GFX_MIDCMD_CNTL 1291 + #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1292 + #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1293 + #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1294 + #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1295 + #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1296 + #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1297 + #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1298 + #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1299 + //SDMA0_PAGE_RB_CNTL 1300 + #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1301 + #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1302 + #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1303 + #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1304 + #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1305 + #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1306 + #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1307 + #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1308 + #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1309 + #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1310 + #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1311 + #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1312 + #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1313 + #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1314 + #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1315 + #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1316 + //SDMA0_PAGE_RB_BASE 1317 + #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 1318 + #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1319 + //SDMA0_PAGE_RB_BASE_HI 1320 + #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1321 + #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1322 + //SDMA0_PAGE_RB_RPTR 1323 + #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1324 + #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1325 + //SDMA0_PAGE_RB_RPTR_HI 1326 + #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1327 + #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1328 + //SDMA0_PAGE_RB_WPTR 1329 + #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1330 + #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1331 + //SDMA0_PAGE_RB_WPTR_HI 1332 + #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1333 + #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1334 + //SDMA0_PAGE_RB_WPTR_POLL_CNTL 1335 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1336 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1337 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1338 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1339 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1340 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1341 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1342 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1343 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1344 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1345 + //SDMA0_PAGE_RB_RPTR_ADDR_HI 1346 + #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1347 + #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1348 + //SDMA0_PAGE_RB_RPTR_ADDR_LO 1349 + #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1350 + #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1351 + #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1352 + #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1353 + //SDMA0_PAGE_IB_CNTL 1354 + #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1355 + #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1356 + #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1357 + #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1358 + #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1359 + #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1360 + #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1361 + #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1362 + //SDMA0_PAGE_IB_RPTR 1363 + #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1364 + #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1365 + //SDMA0_PAGE_IB_OFFSET 1366 + #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1367 + #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1368 + //SDMA0_PAGE_IB_BASE_LO 1369 + #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1370 + #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1371 + //SDMA0_PAGE_IB_BASE_HI 1372 + #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1373 + #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1374 + //SDMA0_PAGE_IB_SIZE 1375 + #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1376 + #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1377 + //SDMA0_PAGE_SKIP_CNTL 1378 + #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1379 + #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1380 + //SDMA0_PAGE_CONTEXT_STATUS 1381 + #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1382 + #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1383 + #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1384 + #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1385 + #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1386 + #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1387 + #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1388 + #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1389 + #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1390 + #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1391 + #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1392 + #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1393 + #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1394 + #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1395 + #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1396 + #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1397 + //SDMA0_PAGE_DOORBELL 1398 + #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1399 + #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1400 + #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1401 + #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1402 + //SDMA0_PAGE_STATUS 1403 + #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1404 + #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1405 + #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1406 + #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1407 + //SDMA0_PAGE_DOORBELL_LOG 1408 + #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1409 + #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1410 + #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1411 + #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1412 + //SDMA0_PAGE_WATERMARK 1413 + #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1414 + #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1415 + #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1416 + #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1417 + //SDMA0_PAGE_DOORBELL_OFFSET 1418 + #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1419 + #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1420 + //SDMA0_PAGE_CSA_ADDR_LO 1421 + #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1422 + #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1423 + //SDMA0_PAGE_CSA_ADDR_HI 1424 + #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1425 + #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1426 + //SDMA0_PAGE_IB_SUB_REMAIN 1427 + #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1428 + #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1429 + //SDMA0_PAGE_PREEMPT 1430 + #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1431 + #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1432 + //SDMA0_PAGE_DUMMY_REG 1433 + #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1434 + #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1435 + //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 1436 + #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1437 + #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1438 + //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 1439 + #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1440 + #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1441 + //SDMA0_PAGE_RB_AQL_CNTL 1442 + #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1443 + #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1444 + #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1445 + #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1446 + #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1447 + #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1448 + //SDMA0_PAGE_MINOR_PTR_UPDATE 1449 + #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1450 + #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1451 + //SDMA0_PAGE_MIDCMD_DATA0 1452 + #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1453 + #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1454 + //SDMA0_PAGE_MIDCMD_DATA1 1455 + #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1456 + #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1457 + //SDMA0_PAGE_MIDCMD_DATA2 1458 + #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1459 + #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1460 + //SDMA0_PAGE_MIDCMD_DATA3 1461 + #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1462 + #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1463 + //SDMA0_PAGE_MIDCMD_DATA4 1464 + #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1465 + #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1466 + //SDMA0_PAGE_MIDCMD_DATA5 1467 + #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1468 + #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1469 + //SDMA0_PAGE_MIDCMD_DATA6 1470 + #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1471 + #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1472 + //SDMA0_PAGE_MIDCMD_DATA7 1473 + #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1474 + #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1475 + //SDMA0_PAGE_MIDCMD_DATA8 1476 + #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1477 + #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1478 + //SDMA0_PAGE_MIDCMD_CNTL 1479 + #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1480 + #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1481 + #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1482 + #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1483 + #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1484 + #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1485 + #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1486 + #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1487 + //SDMA0_RLC0_RB_CNTL 1488 + #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1489 + #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1490 + #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1491 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1492 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1493 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1494 + #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1495 + #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1496 + #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1497 + #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1498 + #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1499 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1500 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1501 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1502 + #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1503 + #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1504 + //SDMA0_RLC0_RB_BASE 1505 + #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1506 + #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1507 + //SDMA0_RLC0_RB_BASE_HI 1508 + #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1509 + #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1510 + //SDMA0_RLC0_RB_RPTR 1511 + #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1512 + #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1513 + //SDMA0_RLC0_RB_RPTR_HI 1514 + #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1515 + #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1516 + //SDMA0_RLC0_RB_WPTR 1517 + #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1518 + #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1519 + //SDMA0_RLC0_RB_WPTR_HI 1520 + #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1521 + #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1522 + //SDMA0_RLC0_RB_WPTR_POLL_CNTL 1523 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1524 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1525 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1526 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1527 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1528 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1529 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1530 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1531 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1532 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1533 + //SDMA0_RLC0_RB_RPTR_ADDR_HI 1534 + #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1535 + #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1536 + //SDMA0_RLC0_RB_RPTR_ADDR_LO 1537 + #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1538 + #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1539 + #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1540 + #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1541 + //SDMA0_RLC0_IB_CNTL 1542 + #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1543 + #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1544 + #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1545 + #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1546 + #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1547 + #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1548 + #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1549 + #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1550 + //SDMA0_RLC0_IB_RPTR 1551 + #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1552 + #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1553 + //SDMA0_RLC0_IB_OFFSET 1554 + #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1555 + #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1556 + //SDMA0_RLC0_IB_BASE_LO 1557 + #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1558 + #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1559 + //SDMA0_RLC0_IB_BASE_HI 1560 + #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1561 + #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1562 + //SDMA0_RLC0_IB_SIZE 1563 + #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1564 + #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1565 + //SDMA0_RLC0_SKIP_CNTL 1566 + #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1567 + #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1568 + //SDMA0_RLC0_CONTEXT_STATUS 1569 + #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1570 + #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1571 + #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1572 + #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1573 + #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1574 + #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1575 + #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1576 + #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1577 + #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1578 + #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1579 + #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1580 + #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1581 + #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1582 + #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1583 + #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1584 + #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1585 + //SDMA0_RLC0_DOORBELL 1586 + #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1587 + #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1588 + #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1589 + #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1590 + //SDMA0_RLC0_STATUS 1591 + #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1592 + #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1593 + #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1594 + #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1595 + //SDMA0_RLC0_DOORBELL_LOG 1596 + #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1597 + #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1598 + #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1599 + #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1600 + //SDMA0_RLC0_WATERMARK 1601 + #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1602 + #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1603 + #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1604 + #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1605 + //SDMA0_RLC0_DOORBELL_OFFSET 1606 + #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1607 + #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1608 + //SDMA0_RLC0_CSA_ADDR_LO 1609 + #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1610 + #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1611 + //SDMA0_RLC0_CSA_ADDR_HI 1612 + #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1613 + #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1614 + //SDMA0_RLC0_IB_SUB_REMAIN 1615 + #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1616 + #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1617 + //SDMA0_RLC0_PREEMPT 1618 + #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1619 + #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1620 + //SDMA0_RLC0_DUMMY_REG 1621 + #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1622 + #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1623 + //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1624 + #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1625 + #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1626 + //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1627 + #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1628 + #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1629 + //SDMA0_RLC0_RB_AQL_CNTL 1630 + #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1631 + #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1632 + #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1633 + #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1634 + #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1635 + #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1636 + //SDMA0_RLC0_MINOR_PTR_UPDATE 1637 + #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1638 + #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1639 + //SDMA0_RLC0_MIDCMD_DATA0 1640 + #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1641 + #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1642 + //SDMA0_RLC0_MIDCMD_DATA1 1643 + #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1644 + #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1645 + //SDMA0_RLC0_MIDCMD_DATA2 1646 + #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1647 + #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1648 + //SDMA0_RLC0_MIDCMD_DATA3 1649 + #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1650 + #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1651 + //SDMA0_RLC0_MIDCMD_DATA4 1652 + #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1653 + #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1654 + //SDMA0_RLC0_MIDCMD_DATA5 1655 + #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1656 + #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1657 + //SDMA0_RLC0_MIDCMD_DATA6 1658 + #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1659 + #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1660 + //SDMA0_RLC0_MIDCMD_DATA7 1661 + #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1662 + #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1663 + //SDMA0_RLC0_MIDCMD_DATA8 1664 + #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1665 + #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1666 + //SDMA0_RLC0_MIDCMD_CNTL 1667 + #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1668 + #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1669 + #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1670 + #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1671 + #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1672 + #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1673 + #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1674 + #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1675 + //SDMA0_RLC1_RB_CNTL 1676 + #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1677 + #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1678 + #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1679 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1680 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1681 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1682 + #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1683 + #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1684 + #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1685 + #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1686 + #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1687 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1688 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1689 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1690 + #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1691 + #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1692 + //SDMA0_RLC1_RB_BASE 1693 + #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1694 + #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1695 + //SDMA0_RLC1_RB_BASE_HI 1696 + #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1697 + #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1698 + //SDMA0_RLC1_RB_RPTR 1699 + #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1700 + #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1701 + //SDMA0_RLC1_RB_RPTR_HI 1702 + #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1703 + #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1704 + //SDMA0_RLC1_RB_WPTR 1705 + #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1706 + #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1707 + //SDMA0_RLC1_RB_WPTR_HI 1708 + #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1709 + #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1710 + //SDMA0_RLC1_RB_WPTR_POLL_CNTL 1711 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1712 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1713 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1714 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1715 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1716 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1717 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1718 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1719 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1720 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1721 + //SDMA0_RLC1_RB_RPTR_ADDR_HI 1722 + #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1723 + #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1724 + //SDMA0_RLC1_RB_RPTR_ADDR_LO 1725 + #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1726 + #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1727 + #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1728 + #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1729 + //SDMA0_RLC1_IB_CNTL 1730 + #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1731 + #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1732 + #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1733 + #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1734 + #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1735 + #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1736 + #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1737 + #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1738 + //SDMA0_RLC1_IB_RPTR 1739 + #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1740 + #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1741 + //SDMA0_RLC1_IB_OFFSET 1742 + #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1743 + #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1744 + //SDMA0_RLC1_IB_BASE_LO 1745 + #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1746 + #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1747 + //SDMA0_RLC1_IB_BASE_HI 1748 + #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1749 + #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1750 + //SDMA0_RLC1_IB_SIZE 1751 + #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1752 + #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1753 + //SDMA0_RLC1_SKIP_CNTL 1754 + #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1755 + #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1756 + //SDMA0_RLC1_CONTEXT_STATUS 1757 + #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1758 + #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1759 + #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1760 + #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1761 + #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1762 + #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1763 + #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1764 + #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1765 + #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1766 + #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1767 + #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1768 + #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1769 + #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1770 + #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1771 + #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1772 + #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1773 + //SDMA0_RLC1_DOORBELL 1774 + #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1775 + #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1776 + #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1777 + #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1778 + //SDMA0_RLC1_STATUS 1779 + #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1780 + #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1781 + #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1782 + #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1783 + //SDMA0_RLC1_DOORBELL_LOG 1784 + #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1785 + #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1786 + #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1787 + #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1788 + //SDMA0_RLC1_WATERMARK 1789 + #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1790 + #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1791 + #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1792 + #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1793 + //SDMA0_RLC1_DOORBELL_OFFSET 1794 + #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1795 + #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1796 + //SDMA0_RLC1_CSA_ADDR_LO 1797 + #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1798 + #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1799 + //SDMA0_RLC1_CSA_ADDR_HI 1800 + #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1801 + #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1802 + //SDMA0_RLC1_IB_SUB_REMAIN 1803 + #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1804 + #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1805 + //SDMA0_RLC1_PREEMPT 1806 + #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1807 + #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1808 + //SDMA0_RLC1_DUMMY_REG 1809 + #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1810 + #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1811 + //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1812 + #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1813 + #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1814 + //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1815 + #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1816 + #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1817 + //SDMA0_RLC1_RB_AQL_CNTL 1818 + #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1819 + #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1820 + #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1821 + #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1822 + #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1823 + #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1824 + //SDMA0_RLC1_MINOR_PTR_UPDATE 1825 + #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1826 + #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1827 + //SDMA0_RLC1_MIDCMD_DATA0 1828 + #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1829 + #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1830 + //SDMA0_RLC1_MIDCMD_DATA1 1831 + #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1832 + #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1833 + //SDMA0_RLC1_MIDCMD_DATA2 1834 + #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1835 + #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1836 + //SDMA0_RLC1_MIDCMD_DATA3 1837 + #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1838 + #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1839 + //SDMA0_RLC1_MIDCMD_DATA4 1840 + #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1841 + #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1842 + //SDMA0_RLC1_MIDCMD_DATA5 1843 + #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1844 + #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1845 + //SDMA0_RLC1_MIDCMD_DATA6 1846 + #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1847 + #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1848 + //SDMA0_RLC1_MIDCMD_DATA7 1849 + #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1850 + #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1851 + //SDMA0_RLC1_MIDCMD_DATA8 1852 + #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1853 + #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1854 + //SDMA0_RLC1_MIDCMD_CNTL 1855 + #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1856 + #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1857 + #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1858 + #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1859 + #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1860 + #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1861 + #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1862 + #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1863 + //SDMA0_RLC2_RB_CNTL 1864 + #define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 1865 + #define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 1866 + #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1867 + #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1868 + #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1869 + #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1870 + #define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 1871 + #define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 1872 + #define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1873 + #define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1874 + #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1875 + #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1876 + #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1877 + #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1878 + #define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 1879 + #define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 1880 + //SDMA0_RLC2_RB_BASE 1881 + #define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 1882 + #define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1883 + //SDMA0_RLC2_RB_BASE_HI 1884 + #define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 1885 + #define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1886 + //SDMA0_RLC2_RB_RPTR 1887 + #define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 1888 + #define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1889 + //SDMA0_RLC2_RB_RPTR_HI 1890 + #define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 1891 + #define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1892 + //SDMA0_RLC2_RB_WPTR 1893 + #define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 1894 + #define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1895 + //SDMA0_RLC2_RB_WPTR_HI 1896 + #define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 1897 + #define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1898 + //SDMA0_RLC2_RB_WPTR_POLL_CNTL 1899 + #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1900 + #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1901 + #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1902 + #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1903 + #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1904 + #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1905 + #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1906 + #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1907 + #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1908 + #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1909 + //SDMA0_RLC2_RB_RPTR_ADDR_HI 1910 + #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1911 + #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1912 + //SDMA0_RLC2_RB_RPTR_ADDR_LO 1913 + #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1914 + #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1915 + #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1916 + #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1917 + //SDMA0_RLC2_IB_CNTL 1918 + #define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 1919 + #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1920 + #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1921 + #define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 1922 + #define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1923 + #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1924 + #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1925 + #define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1926 + //SDMA0_RLC2_IB_RPTR 1927 + #define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 1928 + #define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1929 + //SDMA0_RLC2_IB_OFFSET 1930 + #define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 1931 + #define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1932 + //SDMA0_RLC2_IB_BASE_LO 1933 + #define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 1934 + #define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1935 + //SDMA0_RLC2_IB_BASE_HI 1936 + #define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 1937 + #define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1938 + //SDMA0_RLC2_IB_SIZE 1939 + #define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 1940 + #define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 1941 + //SDMA0_RLC2_SKIP_CNTL 1942 + #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1943 + #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1944 + //SDMA0_RLC2_CONTEXT_STATUS 1945 + #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1946 + #define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 1947 + #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1948 + #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1949 + #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1950 + #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1951 + #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1952 + #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1953 + #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1954 + #define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1955 + #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1956 + #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1957 + #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1958 + #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1959 + #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1960 + #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1961 + //SDMA0_RLC2_DOORBELL 1962 + #define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 1963 + #define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 1964 + #define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 1965 + #define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 1966 + //SDMA0_RLC2_STATUS 1967 + #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1968 + #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1969 + #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1970 + #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1971 + //SDMA0_RLC2_DOORBELL_LOG 1972 + #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1973 + #define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 1974 + #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1975 + #define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1976 + //SDMA0_RLC2_WATERMARK 1977 + #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1978 + #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1979 + #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1980 + #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1981 + //SDMA0_RLC2_DOORBELL_OFFSET 1982 + #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1983 + #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1984 + //SDMA0_RLC2_CSA_ADDR_LO 1985 + #define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 1986 + #define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1987 + //SDMA0_RLC2_CSA_ADDR_HI 1988 + #define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 1989 + #define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1990 + //SDMA0_RLC2_IB_SUB_REMAIN 1991 + #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1992 + #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1993 + //SDMA0_RLC2_PREEMPT 1994 + #define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 1995 + #define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1996 + //SDMA0_RLC2_DUMMY_REG 1997 + #define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 1998 + #define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1999 + //SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 2000 + #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2001 + #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2002 + //SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 2003 + #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2004 + #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2005 + //SDMA0_RLC2_RB_AQL_CNTL 2006 + #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2007 + #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2008 + #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2009 + #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2010 + #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2011 + #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2012 + //SDMA0_RLC2_MINOR_PTR_UPDATE 2013 + #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2014 + #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2015 + //SDMA0_RLC2_MIDCMD_DATA0 2016 + #define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 2017 + #define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2018 + //SDMA0_RLC2_MIDCMD_DATA1 2019 + #define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 2020 + #define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2021 + //SDMA0_RLC2_MIDCMD_DATA2 2022 + #define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 2023 + #define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2024 + //SDMA0_RLC2_MIDCMD_DATA3 2025 + #define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 2026 + #define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2027 + //SDMA0_RLC2_MIDCMD_DATA4 2028 + #define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 2029 + #define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2030 + //SDMA0_RLC2_MIDCMD_DATA5 2031 + #define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 2032 + #define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2033 + //SDMA0_RLC2_MIDCMD_DATA6 2034 + #define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 2035 + #define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2036 + //SDMA0_RLC2_MIDCMD_DATA7 2037 + #define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 2038 + #define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2039 + //SDMA0_RLC2_MIDCMD_DATA8 2040 + #define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 2041 + #define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2042 + //SDMA0_RLC2_MIDCMD_CNTL 2043 + #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2044 + #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2045 + #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2046 + #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2047 + #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2048 + #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2049 + #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2050 + #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2051 + //SDMA0_RLC3_RB_CNTL 2052 + #define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 2053 + #define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 2054 + #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2055 + #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2056 + #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2057 + #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2058 + #define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 2059 + #define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 2060 + #define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2061 + #define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2062 + #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2063 + #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2064 + #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2065 + #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2066 + #define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 2067 + #define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 2068 + //SDMA0_RLC3_RB_BASE 2069 + #define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 2070 + #define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2071 + //SDMA0_RLC3_RB_BASE_HI 2072 + #define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 2073 + #define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2074 + //SDMA0_RLC3_RB_RPTR 2075 + #define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 2076 + #define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2077 + //SDMA0_RLC3_RB_RPTR_HI 2078 + #define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 2079 + #define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2080 + //SDMA0_RLC3_RB_WPTR 2081 + #define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 2082 + #define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2083 + //SDMA0_RLC3_RB_WPTR_HI 2084 + #define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 2085 + #define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2086 + //SDMA0_RLC3_RB_WPTR_POLL_CNTL 2087 + #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2088 + #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2089 + #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2090 + #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2091 + #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2092 + #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2093 + #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2094 + #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2095 + #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2096 + #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2097 + //SDMA0_RLC3_RB_RPTR_ADDR_HI 2098 + #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2099 + #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2100 + //SDMA0_RLC3_RB_RPTR_ADDR_LO 2101 + #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2102 + #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2103 + #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2104 + #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2105 + //SDMA0_RLC3_IB_CNTL 2106 + #define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 2107 + #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2108 + #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2109 + #define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 2110 + #define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2111 + #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2112 + #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2113 + #define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2114 + //SDMA0_RLC3_IB_RPTR 2115 + #define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 2116 + #define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2117 + //SDMA0_RLC3_IB_OFFSET 2118 + #define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 2119 + #define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2120 + //SDMA0_RLC3_IB_BASE_LO 2121 + #define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 2122 + #define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2123 + //SDMA0_RLC3_IB_BASE_HI 2124 + #define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 2125 + #define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2126 + //SDMA0_RLC3_IB_SIZE 2127 + #define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 2128 + #define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 2129 + //SDMA0_RLC3_SKIP_CNTL 2130 + #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2131 + #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2132 + //SDMA0_RLC3_CONTEXT_STATUS 2133 + #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2134 + #define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 2135 + #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2136 + #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2137 + #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2138 + #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2139 + #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2140 + #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2141 + #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2142 + #define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2143 + #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2144 + #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2145 + #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2146 + #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2147 + #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2148 + #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2149 + //SDMA0_RLC3_DOORBELL 2150 + #define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 2151 + #define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 2152 + #define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 2153 + #define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 2154 + //SDMA0_RLC3_STATUS 2155 + #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2156 + #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2157 + #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2158 + #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2159 + //SDMA0_RLC3_DOORBELL_LOG 2160 + #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2161 + #define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 2162 + #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2163 + #define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2164 + //SDMA0_RLC3_WATERMARK 2165 + #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2166 + #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2167 + #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2168 + #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2169 + //SDMA0_RLC3_DOORBELL_OFFSET 2170 + #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2171 + #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2172 + //SDMA0_RLC3_CSA_ADDR_LO 2173 + #define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 2174 + #define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2175 + //SDMA0_RLC3_CSA_ADDR_HI 2176 + #define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 2177 + #define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2178 + //SDMA0_RLC3_IB_SUB_REMAIN 2179 + #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2180 + #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2181 + //SDMA0_RLC3_PREEMPT 2182 + #define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 2183 + #define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2184 + //SDMA0_RLC3_DUMMY_REG 2185 + #define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 2186 + #define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2187 + //SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 2188 + #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2189 + #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2190 + //SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 2191 + #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2192 + #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2193 + //SDMA0_RLC3_RB_AQL_CNTL 2194 + #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2195 + #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2196 + #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2197 + #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2198 + #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2199 + #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2200 + //SDMA0_RLC3_MINOR_PTR_UPDATE 2201 + #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2202 + #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2203 + //SDMA0_RLC3_MIDCMD_DATA0 2204 + #define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 2205 + #define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2206 + //SDMA0_RLC3_MIDCMD_DATA1 2207 + #define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 2208 + #define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2209 + //SDMA0_RLC3_MIDCMD_DATA2 2210 + #define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 2211 + #define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2212 + //SDMA0_RLC3_MIDCMD_DATA3 2213 + #define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 2214 + #define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2215 + //SDMA0_RLC3_MIDCMD_DATA4 2216 + #define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 2217 + #define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2218 + //SDMA0_RLC3_MIDCMD_DATA5 2219 + #define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 2220 + #define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2221 + //SDMA0_RLC3_MIDCMD_DATA6 2222 + #define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 2223 + #define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2224 + //SDMA0_RLC3_MIDCMD_DATA7 2225 + #define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 2226 + #define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2227 + //SDMA0_RLC3_MIDCMD_DATA8 2228 + #define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 2229 + #define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2230 + //SDMA0_RLC3_MIDCMD_CNTL 2231 + #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2232 + #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2233 + #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2234 + #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2235 + #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2236 + #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2237 + #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2238 + #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2239 + //SDMA0_RLC4_RB_CNTL 2240 + #define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 2241 + #define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 2242 + #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2243 + #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2244 + #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2245 + #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2246 + #define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 2247 + #define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 2248 + #define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2249 + #define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2250 + #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2251 + #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2252 + #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2253 + #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2254 + #define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 2255 + #define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 2256 + //SDMA0_RLC4_RB_BASE 2257 + #define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 2258 + #define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2259 + //SDMA0_RLC4_RB_BASE_HI 2260 + #define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 2261 + #define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2262 + //SDMA0_RLC4_RB_RPTR 2263 + #define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 2264 + #define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2265 + //SDMA0_RLC4_RB_RPTR_HI 2266 + #define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 2267 + #define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2268 + //SDMA0_RLC4_RB_WPTR 2269 + #define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 2270 + #define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2271 + //SDMA0_RLC4_RB_WPTR_HI 2272 + #define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 2273 + #define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2274 + //SDMA0_RLC4_RB_WPTR_POLL_CNTL 2275 + #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2276 + #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2277 + #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2278 + #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2279 + #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2280 + #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2281 + #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2282 + #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2283 + #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2284 + #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2285 + //SDMA0_RLC4_RB_RPTR_ADDR_HI 2286 + #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2287 + #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2288 + //SDMA0_RLC4_RB_RPTR_ADDR_LO 2289 + #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2290 + #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2291 + #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2292 + #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2293 + //SDMA0_RLC4_IB_CNTL 2294 + #define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 2295 + #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2296 + #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2297 + #define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 2298 + #define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2299 + #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2300 + #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2301 + #define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2302 + //SDMA0_RLC4_IB_RPTR 2303 + #define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 2304 + #define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2305 + //SDMA0_RLC4_IB_OFFSET 2306 + #define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 2307 + #define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2308 + //SDMA0_RLC4_IB_BASE_LO 2309 + #define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 2310 + #define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2311 + //SDMA0_RLC4_IB_BASE_HI 2312 + #define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 2313 + #define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2314 + //SDMA0_RLC4_IB_SIZE 2315 + #define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 2316 + #define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 2317 + //SDMA0_RLC4_SKIP_CNTL 2318 + #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2319 + #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2320 + //SDMA0_RLC4_CONTEXT_STATUS 2321 + #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2322 + #define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 2323 + #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2324 + #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2325 + #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2326 + #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2327 + #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2328 + #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2329 + #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2330 + #define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2331 + #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2332 + #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2333 + #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2334 + #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2335 + #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2336 + #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2337 + //SDMA0_RLC4_DOORBELL 2338 + #define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 2339 + #define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 2340 + #define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 2341 + #define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 2342 + //SDMA0_RLC4_STATUS 2343 + #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2344 + #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2345 + #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2346 + #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2347 + //SDMA0_RLC4_DOORBELL_LOG 2348 + #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2349 + #define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 2350 + #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2351 + #define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2352 + //SDMA0_RLC4_WATERMARK 2353 + #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2354 + #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2355 + #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2356 + #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2357 + //SDMA0_RLC4_DOORBELL_OFFSET 2358 + #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2359 + #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2360 + //SDMA0_RLC4_CSA_ADDR_LO 2361 + #define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 2362 + #define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2363 + //SDMA0_RLC4_CSA_ADDR_HI 2364 + #define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 2365 + #define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2366 + //SDMA0_RLC4_IB_SUB_REMAIN 2367 + #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2368 + #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2369 + //SDMA0_RLC4_PREEMPT 2370 + #define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 2371 + #define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2372 + //SDMA0_RLC4_DUMMY_REG 2373 + #define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 2374 + #define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2375 + //SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 2376 + #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2377 + #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2378 + //SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 2379 + #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2380 + #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2381 + //SDMA0_RLC4_RB_AQL_CNTL 2382 + #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2383 + #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2384 + #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2385 + #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2386 + #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2387 + #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2388 + //SDMA0_RLC4_MINOR_PTR_UPDATE 2389 + #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2390 + #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2391 + //SDMA0_RLC4_MIDCMD_DATA0 2392 + #define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 2393 + #define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2394 + //SDMA0_RLC4_MIDCMD_DATA1 2395 + #define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 2396 + #define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2397 + //SDMA0_RLC4_MIDCMD_DATA2 2398 + #define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 2399 + #define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2400 + //SDMA0_RLC4_MIDCMD_DATA3 2401 + #define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 2402 + #define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2403 + //SDMA0_RLC4_MIDCMD_DATA4 2404 + #define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 2405 + #define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2406 + //SDMA0_RLC4_MIDCMD_DATA5 2407 + #define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 2408 + #define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2409 + //SDMA0_RLC4_MIDCMD_DATA6 2410 + #define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 2411 + #define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2412 + //SDMA0_RLC4_MIDCMD_DATA7 2413 + #define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 2414 + #define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2415 + //SDMA0_RLC4_MIDCMD_DATA8 2416 + #define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 2417 + #define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2418 + //SDMA0_RLC4_MIDCMD_CNTL 2419 + #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2420 + #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2421 + #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2422 + #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2423 + #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2424 + #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2425 + #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2426 + #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2427 + //SDMA0_RLC5_RB_CNTL 2428 + #define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 2429 + #define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 2430 + #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2431 + #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2432 + #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2433 + #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2434 + #define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 2435 + #define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 2436 + #define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2437 + #define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2438 + #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2439 + #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2440 + #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2441 + #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2442 + #define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 2443 + #define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 2444 + //SDMA0_RLC5_RB_BASE 2445 + #define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 2446 + #define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2447 + //SDMA0_RLC5_RB_BASE_HI 2448 + #define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 2449 + #define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2450 + //SDMA0_RLC5_RB_RPTR 2451 + #define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 2452 + #define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2453 + //SDMA0_RLC5_RB_RPTR_HI 2454 + #define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 2455 + #define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2456 + //SDMA0_RLC5_RB_WPTR 2457 + #define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 2458 + #define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2459 + //SDMA0_RLC5_RB_WPTR_HI 2460 + #define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 2461 + #define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2462 + //SDMA0_RLC5_RB_WPTR_POLL_CNTL 2463 + #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2464 + #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2465 + #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2466 + #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2467 + #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2468 + #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2469 + #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2470 + #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2471 + #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2472 + #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2473 + //SDMA0_RLC5_RB_RPTR_ADDR_HI 2474 + #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2475 + #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2476 + //SDMA0_RLC5_RB_RPTR_ADDR_LO 2477 + #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2478 + #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2479 + #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2480 + #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2481 + //SDMA0_RLC5_IB_CNTL 2482 + #define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 2483 + #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2484 + #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2485 + #define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 2486 + #define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2487 + #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2488 + #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2489 + #define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2490 + //SDMA0_RLC5_IB_RPTR 2491 + #define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 2492 + #define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2493 + //SDMA0_RLC5_IB_OFFSET 2494 + #define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 2495 + #define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2496 + //SDMA0_RLC5_IB_BASE_LO 2497 + #define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 2498 + #define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2499 + //SDMA0_RLC5_IB_BASE_HI 2500 + #define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 2501 + #define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2502 + //SDMA0_RLC5_IB_SIZE 2503 + #define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 2504 + #define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 2505 + //SDMA0_RLC5_SKIP_CNTL 2506 + #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2507 + #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2508 + //SDMA0_RLC5_CONTEXT_STATUS 2509 + #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2510 + #define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 2511 + #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2512 + #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2513 + #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2514 + #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2515 + #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2516 + #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2517 + #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2518 + #define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2519 + #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2520 + #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2521 + #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2522 + #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2523 + #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2524 + #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2525 + //SDMA0_RLC5_DOORBELL 2526 + #define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 2527 + #define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 2528 + #define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 2529 + #define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 2530 + //SDMA0_RLC5_STATUS 2531 + #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2532 + #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2533 + #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2534 + #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2535 + //SDMA0_RLC5_DOORBELL_LOG 2536 + #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2537 + #define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 2538 + #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2539 + #define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2540 + //SDMA0_RLC5_WATERMARK 2541 + #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2542 + #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2543 + #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2544 + #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2545 + //SDMA0_RLC5_DOORBELL_OFFSET 2546 + #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2547 + #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2548 + //SDMA0_RLC5_CSA_ADDR_LO 2549 + #define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 2550 + #define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2551 + //SDMA0_RLC5_CSA_ADDR_HI 2552 + #define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 2553 + #define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2554 + //SDMA0_RLC5_IB_SUB_REMAIN 2555 + #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2556 + #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2557 + //SDMA0_RLC5_PREEMPT 2558 + #define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 2559 + #define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2560 + //SDMA0_RLC5_DUMMY_REG 2561 + #define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 2562 + #define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2563 + //SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 2564 + #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2565 + #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2566 + //SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 2567 + #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2568 + #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2569 + //SDMA0_RLC5_RB_AQL_CNTL 2570 + #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2571 + #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2572 + #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2573 + #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2574 + #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2575 + #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2576 + //SDMA0_RLC5_MINOR_PTR_UPDATE 2577 + #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2578 + #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2579 + //SDMA0_RLC5_MIDCMD_DATA0 2580 + #define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 2581 + #define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2582 + //SDMA0_RLC5_MIDCMD_DATA1 2583 + #define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 2584 + #define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2585 + //SDMA0_RLC5_MIDCMD_DATA2 2586 + #define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 2587 + #define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2588 + //SDMA0_RLC5_MIDCMD_DATA3 2589 + #define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 2590 + #define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2591 + //SDMA0_RLC5_MIDCMD_DATA4 2592 + #define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 2593 + #define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2594 + //SDMA0_RLC5_MIDCMD_DATA5 2595 + #define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 2596 + #define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2597 + //SDMA0_RLC5_MIDCMD_DATA6 2598 + #define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 2599 + #define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2600 + //SDMA0_RLC5_MIDCMD_DATA7 2601 + #define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 2602 + #define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2603 + //SDMA0_RLC5_MIDCMD_DATA8 2604 + #define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 2605 + #define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2606 + //SDMA0_RLC5_MIDCMD_CNTL 2607 + #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2608 + #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2609 + #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2610 + #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2611 + #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2612 + #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2613 + #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2614 + #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2615 + //SDMA0_RLC6_RB_CNTL 2616 + #define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 2617 + #define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 2618 + #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2619 + #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2620 + #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2621 + #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2622 + #define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 2623 + #define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 2624 + #define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2625 + #define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2626 + #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2627 + #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2628 + #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2629 + #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2630 + #define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 2631 + #define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 2632 + //SDMA0_RLC6_RB_BASE 2633 + #define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 2634 + #define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2635 + //SDMA0_RLC6_RB_BASE_HI 2636 + #define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 2637 + #define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2638 + //SDMA0_RLC6_RB_RPTR 2639 + #define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 2640 + #define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2641 + //SDMA0_RLC6_RB_RPTR_HI 2642 + #define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 2643 + #define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2644 + //SDMA0_RLC6_RB_WPTR 2645 + #define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 2646 + #define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2647 + //SDMA0_RLC6_RB_WPTR_HI 2648 + #define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 2649 + #define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2650 + //SDMA0_RLC6_RB_WPTR_POLL_CNTL 2651 + #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2652 + #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2653 + #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2654 + #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2655 + #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2656 + #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2657 + #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2658 + #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2659 + #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2660 + #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2661 + //SDMA0_RLC6_RB_RPTR_ADDR_HI 2662 + #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2663 + #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2664 + //SDMA0_RLC6_RB_RPTR_ADDR_LO 2665 + #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2666 + #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2667 + #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2668 + #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2669 + //SDMA0_RLC6_IB_CNTL 2670 + #define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 2671 + #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2672 + #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2673 + #define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 2674 + #define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2675 + #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2676 + #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2677 + #define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2678 + //SDMA0_RLC6_IB_RPTR 2679 + #define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 2680 + #define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2681 + //SDMA0_RLC6_IB_OFFSET 2682 + #define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 2683 + #define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2684 + //SDMA0_RLC6_IB_BASE_LO 2685 + #define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 2686 + #define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2687 + //SDMA0_RLC6_IB_BASE_HI 2688 + #define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 2689 + #define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2690 + //SDMA0_RLC6_IB_SIZE 2691 + #define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 2692 + #define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 2693 + //SDMA0_RLC6_SKIP_CNTL 2694 + #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2695 + #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2696 + //SDMA0_RLC6_CONTEXT_STATUS 2697 + #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2698 + #define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2699 + #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2700 + #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2701 + #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2702 + #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2703 + #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2704 + #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2705 + #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2706 + #define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2707 + #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2708 + #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2709 + #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2710 + #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2711 + #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2712 + #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2713 + //SDMA0_RLC6_DOORBELL 2714 + #define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 2715 + #define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 2716 + #define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 2717 + #define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 2718 + //SDMA0_RLC6_STATUS 2719 + #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2720 + #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2721 + #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2722 + #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2723 + //SDMA0_RLC6_DOORBELL_LOG 2724 + #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2725 + #define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 2726 + #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2727 + #define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2728 + //SDMA0_RLC6_WATERMARK 2729 + #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2730 + #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2731 + #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2732 + #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2733 + //SDMA0_RLC6_DOORBELL_OFFSET 2734 + #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2735 + #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2736 + //SDMA0_RLC6_CSA_ADDR_LO 2737 + #define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 2738 + #define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2739 + //SDMA0_RLC6_CSA_ADDR_HI 2740 + #define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 2741 + #define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2742 + //SDMA0_RLC6_IB_SUB_REMAIN 2743 + #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2744 + #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2745 + //SDMA0_RLC6_PREEMPT 2746 + #define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 2747 + #define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2748 + //SDMA0_RLC6_DUMMY_REG 2749 + #define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 2750 + #define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2751 + //SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 2752 + #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2753 + #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2754 + //SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 2755 + #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2756 + #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2757 + //SDMA0_RLC6_RB_AQL_CNTL 2758 + #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2759 + #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2760 + #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2761 + #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2762 + #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2763 + #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2764 + //SDMA0_RLC6_MINOR_PTR_UPDATE 2765 + #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2766 + #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2767 + //SDMA0_RLC6_MIDCMD_DATA0 2768 + #define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 2769 + #define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2770 + //SDMA0_RLC6_MIDCMD_DATA1 2771 + #define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 2772 + #define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2773 + //SDMA0_RLC6_MIDCMD_DATA2 2774 + #define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 2775 + #define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2776 + //SDMA0_RLC6_MIDCMD_DATA3 2777 + #define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 2778 + #define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2779 + //SDMA0_RLC6_MIDCMD_DATA4 2780 + #define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 2781 + #define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2782 + //SDMA0_RLC6_MIDCMD_DATA5 2783 + #define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 2784 + #define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2785 + //SDMA0_RLC6_MIDCMD_DATA6 2786 + #define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 2787 + #define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2788 + //SDMA0_RLC6_MIDCMD_DATA7 2789 + #define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 2790 + #define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2791 + //SDMA0_RLC6_MIDCMD_DATA8 2792 + #define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 2793 + #define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2794 + //SDMA0_RLC6_MIDCMD_CNTL 2795 + #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2796 + #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2797 + #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2798 + #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2799 + #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2800 + #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2801 + #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2802 + #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2803 + //SDMA0_RLC7_RB_CNTL 2804 + #define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 2805 + #define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 2806 + #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2807 + #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2808 + #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2809 + #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2810 + #define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 2811 + #define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 2812 + #define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2813 + #define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2814 + #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2815 + #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2816 + #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2817 + #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2818 + #define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 2819 + #define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 2820 + //SDMA0_RLC7_RB_BASE 2821 + #define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 2822 + #define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2823 + //SDMA0_RLC7_RB_BASE_HI 2824 + #define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 2825 + #define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2826 + //SDMA0_RLC7_RB_RPTR 2827 + #define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 2828 + #define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2829 + //SDMA0_RLC7_RB_RPTR_HI 2830 + #define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 2831 + #define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2832 + //SDMA0_RLC7_RB_WPTR 2833 + #define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 2834 + #define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2835 + //SDMA0_RLC7_RB_WPTR_HI 2836 + #define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 2837 + #define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2838 + //SDMA0_RLC7_RB_WPTR_POLL_CNTL 2839 + #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2840 + #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2841 + #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2842 + #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2843 + #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2844 + #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2845 + #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2846 + #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2847 + #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2848 + #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2849 + //SDMA0_RLC7_RB_RPTR_ADDR_HI 2850 + #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2851 + #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2852 + //SDMA0_RLC7_RB_RPTR_ADDR_LO 2853 + #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2854 + #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2855 + #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2856 + #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2857 + //SDMA0_RLC7_IB_CNTL 2858 + #define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 2859 + #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2860 + #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2861 + #define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 2862 + #define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2863 + #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2864 + #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2865 + #define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2866 + //SDMA0_RLC7_IB_RPTR 2867 + #define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 2868 + #define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2869 + //SDMA0_RLC7_IB_OFFSET 2870 + #define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 2871 + #define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2872 + //SDMA0_RLC7_IB_BASE_LO 2873 + #define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 2874 + #define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2875 + //SDMA0_RLC7_IB_BASE_HI 2876 + #define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 2877 + #define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2878 + //SDMA0_RLC7_IB_SIZE 2879 + #define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 2880 + #define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 2881 + //SDMA0_RLC7_SKIP_CNTL 2882 + #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2883 + #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2884 + //SDMA0_RLC7_CONTEXT_STATUS 2885 + #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2886 + #define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 2887 + #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2888 + #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2889 + #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2890 + #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2891 + #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2892 + #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2893 + #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2894 + #define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2895 + #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2896 + #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2897 + #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2898 + #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2899 + #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2900 + #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2901 + //SDMA0_RLC7_DOORBELL 2902 + #define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 2903 + #define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 2904 + #define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 2905 + #define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 2906 + //SDMA0_RLC7_STATUS 2907 + #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2908 + #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2909 + #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2910 + #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2911 + //SDMA0_RLC7_DOORBELL_LOG 2912 + #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2913 + #define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 2914 + #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2915 + #define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2916 + //SDMA0_RLC7_WATERMARK 2917 + #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2918 + #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2919 + #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2920 + #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2921 + //SDMA0_RLC7_DOORBELL_OFFSET 2922 + #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2923 + #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2924 + //SDMA0_RLC7_CSA_ADDR_LO 2925 + #define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 2926 + #define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2927 + //SDMA0_RLC7_CSA_ADDR_HI 2928 + #define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 2929 + #define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2930 + //SDMA0_RLC7_IB_SUB_REMAIN 2931 + #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2932 + #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2933 + //SDMA0_RLC7_PREEMPT 2934 + #define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 2935 + #define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2936 + //SDMA0_RLC7_DUMMY_REG 2937 + #define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 2938 + #define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2939 + //SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 2940 + #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2941 + #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2942 + //SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 2943 + #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2944 + #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2945 + //SDMA0_RLC7_RB_AQL_CNTL 2946 + #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2947 + #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2948 + #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2949 + #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2950 + #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2951 + #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2952 + //SDMA0_RLC7_MINOR_PTR_UPDATE 2953 + #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2954 + #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2955 + //SDMA0_RLC7_MIDCMD_DATA0 2956 + #define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 2957 + #define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2958 + //SDMA0_RLC7_MIDCMD_DATA1 2959 + #define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 2960 + #define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2961 + //SDMA0_RLC7_MIDCMD_DATA2 2962 + #define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 2963 + #define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2964 + //SDMA0_RLC7_MIDCMD_DATA3 2965 + #define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 2966 + #define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2967 + //SDMA0_RLC7_MIDCMD_DATA4 2968 + #define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 2969 + #define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2970 + //SDMA0_RLC7_MIDCMD_DATA5 2971 + #define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 2972 + #define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2973 + //SDMA0_RLC7_MIDCMD_DATA6 2974 + #define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 2975 + #define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2976 + //SDMA0_RLC7_MIDCMD_DATA7 2977 + #define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 2978 + #define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2979 + //SDMA0_RLC7_MIDCMD_DATA8 2980 + #define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 2981 + #define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2982 + //SDMA0_RLC7_MIDCMD_CNTL 2983 + #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2984 + #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2985 + #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2986 + #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2987 + #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2988 + #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2989 + #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2990 + #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2991 + 2992 + #endif
+1039
drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h
··· 1 + /* 2 + * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _sdma1_4_2_0_OFFSET_HEADER 22 + #define _sdma1_4_2_0_OFFSET_HEADER 23 + 24 + 25 + 26 + // addressBlock: sdma1_sdma1dec 27 + // base address: 0x6180 28 + #define mmSDMA1_UCODE_ADDR 0x0000 29 + #define mmSDMA1_UCODE_ADDR_BASE_IDX 0 30 + #define mmSDMA1_UCODE_DATA 0x0001 31 + #define mmSDMA1_UCODE_DATA_BASE_IDX 0 32 + #define mmSDMA1_VM_CNTL 0x0004 33 + #define mmSDMA1_VM_CNTL_BASE_IDX 0 34 + #define mmSDMA1_VM_CTX_LO 0x0005 35 + #define mmSDMA1_VM_CTX_LO_BASE_IDX 0 36 + #define mmSDMA1_VM_CTX_HI 0x0006 37 + #define mmSDMA1_VM_CTX_HI_BASE_IDX 0 38 + #define mmSDMA1_ACTIVE_FCN_ID 0x0007 39 + #define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0 40 + #define mmSDMA1_VM_CTX_CNTL 0x0008 41 + #define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0 42 + #define mmSDMA1_VIRT_RESET_REQ 0x0009 43 + #define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0 44 + #define mmSDMA1_VF_ENABLE 0x000a 45 + #define mmSDMA1_VF_ENABLE_BASE_IDX 0 46 + #define mmSDMA1_CONTEXT_REG_TYPE0 0x000b 47 + #define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0 48 + #define mmSDMA1_CONTEXT_REG_TYPE1 0x000c 49 + #define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0 50 + #define mmSDMA1_CONTEXT_REG_TYPE2 0x000d 51 + #define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0 52 + #define mmSDMA1_CONTEXT_REG_TYPE3 0x000e 53 + #define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0 54 + #define mmSDMA1_PUB_REG_TYPE0 0x000f 55 + #define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0 56 + #define mmSDMA1_PUB_REG_TYPE1 0x0010 57 + #define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0 58 + #define mmSDMA1_PUB_REG_TYPE2 0x0011 59 + #define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0 60 + #define mmSDMA1_PUB_REG_TYPE3 0x0012 61 + #define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0 62 + #define mmSDMA1_MMHUB_CNTL 0x0013 63 + #define mmSDMA1_MMHUB_CNTL_BASE_IDX 0 64 + #define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019 65 + #define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 66 + #define mmSDMA1_POWER_CNTL 0x001a 67 + #define mmSDMA1_POWER_CNTL_BASE_IDX 0 68 + #define mmSDMA1_CLK_CTRL 0x001b 69 + #define mmSDMA1_CLK_CTRL_BASE_IDX 0 70 + #define mmSDMA1_CNTL 0x001c 71 + #define mmSDMA1_CNTL_BASE_IDX 0 72 + #define mmSDMA1_CHICKEN_BITS 0x001d 73 + #define mmSDMA1_CHICKEN_BITS_BASE_IDX 0 74 + #define mmSDMA1_GB_ADDR_CONFIG 0x001e 75 + #define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 76 + #define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f 77 + #define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 78 + #define mmSDMA1_RB_RPTR_FETCH_HI 0x0020 79 + #define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 80 + #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 81 + #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 82 + #define mmSDMA1_RB_RPTR_FETCH 0x0022 83 + #define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0 84 + #define mmSDMA1_IB_OFFSET_FETCH 0x0023 85 + #define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 86 + #define mmSDMA1_PROGRAM 0x0024 87 + #define mmSDMA1_PROGRAM_BASE_IDX 0 88 + #define mmSDMA1_STATUS_REG 0x0025 89 + #define mmSDMA1_STATUS_REG_BASE_IDX 0 90 + #define mmSDMA1_STATUS1_REG 0x0026 91 + #define mmSDMA1_STATUS1_REG_BASE_IDX 0 92 + #define mmSDMA1_RD_BURST_CNTL 0x0027 93 + #define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0 94 + #define mmSDMA1_HBM_PAGE_CONFIG 0x0028 95 + #define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 96 + #define mmSDMA1_UCODE_CHECKSUM 0x0029 97 + #define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0 98 + #define mmSDMA1_F32_CNTL 0x002a 99 + #define mmSDMA1_F32_CNTL_BASE_IDX 0 100 + #define mmSDMA1_FREEZE 0x002b 101 + #define mmSDMA1_FREEZE_BASE_IDX 0 102 + #define mmSDMA1_PHASE0_QUANTUM 0x002c 103 + #define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0 104 + #define mmSDMA1_PHASE1_QUANTUM 0x002d 105 + #define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0 106 + #define mmSDMA1_EDC_CONFIG 0x0032 107 + #define mmSDMA1_EDC_CONFIG_BASE_IDX 0 108 + #define mmSDMA1_BA_THRESHOLD 0x0033 109 + #define mmSDMA1_BA_THRESHOLD_BASE_IDX 0 110 + #define mmSDMA1_ID 0x0034 111 + #define mmSDMA1_ID_BASE_IDX 0 112 + #define mmSDMA1_VERSION 0x0035 113 + #define mmSDMA1_VERSION_BASE_IDX 0 114 + #define mmSDMA1_EDC_COUNTER 0x0036 115 + #define mmSDMA1_EDC_COUNTER_BASE_IDX 0 116 + #define mmSDMA1_EDC_COUNTER_CLEAR 0x0037 117 + #define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 118 + #define mmSDMA1_STATUS2_REG 0x0038 119 + #define mmSDMA1_STATUS2_REG_BASE_IDX 0 120 + #define mmSDMA1_ATOMIC_CNTL 0x0039 121 + #define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0 122 + #define mmSDMA1_ATOMIC_PREOP_LO 0x003a 123 + #define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 124 + #define mmSDMA1_ATOMIC_PREOP_HI 0x003b 125 + #define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 126 + #define mmSDMA1_UTCL1_CNTL 0x003c 127 + #define mmSDMA1_UTCL1_CNTL_BASE_IDX 0 128 + #define mmSDMA1_UTCL1_WATERMK 0x003d 129 + #define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0 130 + #define mmSDMA1_UTCL1_RD_STATUS 0x003e 131 + #define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 132 + #define mmSDMA1_UTCL1_WR_STATUS 0x003f 133 + #define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 134 + #define mmSDMA1_UTCL1_INV0 0x0040 135 + #define mmSDMA1_UTCL1_INV0_BASE_IDX 0 136 + #define mmSDMA1_UTCL1_INV1 0x0041 137 + #define mmSDMA1_UTCL1_INV1_BASE_IDX 0 138 + #define mmSDMA1_UTCL1_INV2 0x0042 139 + #define mmSDMA1_UTCL1_INV2_BASE_IDX 0 140 + #define mmSDMA1_UTCL1_RD_XNACK0 0x0043 141 + #define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 142 + #define mmSDMA1_UTCL1_RD_XNACK1 0x0044 143 + #define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 144 + #define mmSDMA1_UTCL1_WR_XNACK0 0x0045 145 + #define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 146 + #define mmSDMA1_UTCL1_WR_XNACK1 0x0046 147 + #define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 148 + #define mmSDMA1_UTCL1_TIMEOUT 0x0047 149 + #define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 150 + #define mmSDMA1_UTCL1_PAGE 0x0048 151 + #define mmSDMA1_UTCL1_PAGE_BASE_IDX 0 152 + #define mmSDMA1_POWER_CNTL_IDLE 0x0049 153 + #define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0 154 + #define mmSDMA1_RELAX_ORDERING_LUT 0x004a 155 + #define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 156 + #define mmSDMA1_CHICKEN_BITS_2 0x004b 157 + #define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0 158 + #define mmSDMA1_STATUS3_REG 0x004c 159 + #define mmSDMA1_STATUS3_REG_BASE_IDX 0 160 + #define mmSDMA1_PHYSICAL_ADDR_LO 0x004d 161 + #define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 162 + #define mmSDMA1_PHYSICAL_ADDR_HI 0x004e 163 + #define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 164 + #define mmSDMA1_PHASE2_QUANTUM 0x004f 165 + #define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0 166 + #define mmSDMA1_ERROR_LOG 0x0050 167 + #define mmSDMA1_ERROR_LOG_BASE_IDX 0 168 + #define mmSDMA1_PUB_DUMMY_REG0 0x0051 169 + #define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 170 + #define mmSDMA1_PUB_DUMMY_REG1 0x0052 171 + #define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 172 + #define mmSDMA1_PUB_DUMMY_REG2 0x0053 173 + #define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 174 + #define mmSDMA1_PUB_DUMMY_REG3 0x0054 175 + #define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 176 + #define mmSDMA1_F32_COUNTER 0x0055 177 + #define mmSDMA1_F32_COUNTER_BASE_IDX 0 178 + #define mmSDMA1_PERFMON_CNTL 0x0057 179 + #define mmSDMA1_PERFMON_CNTL_BASE_IDX 0 180 + #define mmSDMA1_PERFCOUNTER0_RESULT 0x0058 181 + #define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0 182 + #define mmSDMA1_PERFCOUNTER1_RESULT 0x0059 183 + #define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0 184 + #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a 185 + #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 186 + #define mmSDMA1_CRD_CNTL 0x005b 187 + #define mmSDMA1_CRD_CNTL_BASE_IDX 0 188 + #define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d 189 + #define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 190 + #define mmSDMA1_ULV_CNTL 0x005e 191 + #define mmSDMA1_ULV_CNTL_BASE_IDX 0 192 + #define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060 193 + #define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 194 + #define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061 195 + #define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 196 + #define mmSDMA1_GFX_RB_CNTL 0x0080 197 + #define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0 198 + #define mmSDMA1_GFX_RB_BASE 0x0081 199 + #define mmSDMA1_GFX_RB_BASE_BASE_IDX 0 200 + #define mmSDMA1_GFX_RB_BASE_HI 0x0082 201 + #define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 202 + #define mmSDMA1_GFX_RB_RPTR 0x0083 203 + #define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0 204 + #define mmSDMA1_GFX_RB_RPTR_HI 0x0084 205 + #define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 206 + #define mmSDMA1_GFX_RB_WPTR 0x0085 207 + #define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0 208 + #define mmSDMA1_GFX_RB_WPTR_HI 0x0086 209 + #define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 210 + #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087 211 + #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 212 + #define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088 213 + #define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 214 + #define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089 215 + #define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 216 + #define mmSDMA1_GFX_IB_CNTL 0x008a 217 + #define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0 218 + #define mmSDMA1_GFX_IB_RPTR 0x008b 219 + #define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0 220 + #define mmSDMA1_GFX_IB_OFFSET 0x008c 221 + #define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0 222 + #define mmSDMA1_GFX_IB_BASE_LO 0x008d 223 + #define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 224 + #define mmSDMA1_GFX_IB_BASE_HI 0x008e 225 + #define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 226 + #define mmSDMA1_GFX_IB_SIZE 0x008f 227 + #define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0 228 + #define mmSDMA1_GFX_SKIP_CNTL 0x0090 229 + #define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 230 + #define mmSDMA1_GFX_CONTEXT_STATUS 0x0091 231 + #define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 232 + #define mmSDMA1_GFX_DOORBELL 0x0092 233 + #define mmSDMA1_GFX_DOORBELL_BASE_IDX 0 234 + #define mmSDMA1_GFX_CONTEXT_CNTL 0x0093 235 + #define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 236 + #define mmSDMA1_GFX_STATUS 0x00a8 237 + #define mmSDMA1_GFX_STATUS_BASE_IDX 0 238 + #define mmSDMA1_GFX_DOORBELL_LOG 0x00a9 239 + #define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 240 + #define mmSDMA1_GFX_WATERMARK 0x00aa 241 + #define mmSDMA1_GFX_WATERMARK_BASE_IDX 0 242 + #define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab 243 + #define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 244 + #define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac 245 + #define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 246 + #define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad 247 + #define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 248 + #define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af 249 + #define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 250 + #define mmSDMA1_GFX_PREEMPT 0x00b0 251 + #define mmSDMA1_GFX_PREEMPT_BASE_IDX 0 252 + #define mmSDMA1_GFX_DUMMY_REG 0x00b1 253 + #define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0 254 + #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 255 + #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 256 + #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 257 + #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 258 + #define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4 259 + #define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 260 + #define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5 261 + #define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 262 + #define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0 263 + #define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 264 + #define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1 265 + #define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 266 + #define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2 267 + #define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 268 + #define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3 269 + #define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 270 + #define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4 271 + #define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 272 + #define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5 273 + #define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 274 + #define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6 275 + #define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 276 + #define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7 277 + #define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 278 + #define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8 279 + #define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 280 + #define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9 281 + #define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 282 + #define mmSDMA1_PAGE_RB_CNTL 0x00e0 283 + #define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0 284 + #define mmSDMA1_PAGE_RB_BASE 0x00e1 285 + #define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0 286 + #define mmSDMA1_PAGE_RB_BASE_HI 0x00e2 287 + #define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 288 + #define mmSDMA1_PAGE_RB_RPTR 0x00e3 289 + #define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0 290 + #define mmSDMA1_PAGE_RB_RPTR_HI 0x00e4 291 + #define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 292 + #define mmSDMA1_PAGE_RB_WPTR 0x00e5 293 + #define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0 294 + #define mmSDMA1_PAGE_RB_WPTR_HI 0x00e6 295 + #define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 296 + #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7 297 + #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 298 + #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e8 299 + #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 300 + #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e9 301 + #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 302 + #define mmSDMA1_PAGE_IB_CNTL 0x00ea 303 + #define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0 304 + #define mmSDMA1_PAGE_IB_RPTR 0x00eb 305 + #define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0 306 + #define mmSDMA1_PAGE_IB_OFFSET 0x00ec 307 + #define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 308 + #define mmSDMA1_PAGE_IB_BASE_LO 0x00ed 309 + #define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 310 + #define mmSDMA1_PAGE_IB_BASE_HI 0x00ee 311 + #define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 312 + #define mmSDMA1_PAGE_IB_SIZE 0x00ef 313 + #define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0 314 + #define mmSDMA1_PAGE_SKIP_CNTL 0x00f0 315 + #define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 316 + #define mmSDMA1_PAGE_CONTEXT_STATUS 0x00f1 317 + #define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 318 + #define mmSDMA1_PAGE_DOORBELL 0x00f2 319 + #define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0 320 + #define mmSDMA1_PAGE_STATUS 0x0108 321 + #define mmSDMA1_PAGE_STATUS_BASE_IDX 0 322 + #define mmSDMA1_PAGE_DOORBELL_LOG 0x0109 323 + #define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 324 + #define mmSDMA1_PAGE_WATERMARK 0x010a 325 + #define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0 326 + #define mmSDMA1_PAGE_DOORBELL_OFFSET 0x010b 327 + #define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 328 + #define mmSDMA1_PAGE_CSA_ADDR_LO 0x010c 329 + #define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 330 + #define mmSDMA1_PAGE_CSA_ADDR_HI 0x010d 331 + #define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 332 + #define mmSDMA1_PAGE_IB_SUB_REMAIN 0x010f 333 + #define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 334 + #define mmSDMA1_PAGE_PREEMPT 0x0110 335 + #define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0 336 + #define mmSDMA1_PAGE_DUMMY_REG 0x0111 337 + #define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 338 + #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 339 + #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 340 + #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 341 + #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 342 + #define mmSDMA1_PAGE_RB_AQL_CNTL 0x0114 343 + #define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 344 + #define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0115 345 + #define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 346 + #define mmSDMA1_PAGE_MIDCMD_DATA0 0x0120 347 + #define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 348 + #define mmSDMA1_PAGE_MIDCMD_DATA1 0x0121 349 + #define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 350 + #define mmSDMA1_PAGE_MIDCMD_DATA2 0x0122 351 + #define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 352 + #define mmSDMA1_PAGE_MIDCMD_DATA3 0x0123 353 + #define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 354 + #define mmSDMA1_PAGE_MIDCMD_DATA4 0x0124 355 + #define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 356 + #define mmSDMA1_PAGE_MIDCMD_DATA5 0x0125 357 + #define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 358 + #define mmSDMA1_PAGE_MIDCMD_DATA6 0x0126 359 + #define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 360 + #define mmSDMA1_PAGE_MIDCMD_DATA7 0x0127 361 + #define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 362 + #define mmSDMA1_PAGE_MIDCMD_DATA8 0x0128 363 + #define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 364 + #define mmSDMA1_PAGE_MIDCMD_CNTL 0x0129 365 + #define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 366 + #define mmSDMA1_RLC0_RB_CNTL 0x0140 367 + #define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0 368 + #define mmSDMA1_RLC0_RB_BASE 0x0141 369 + #define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0 370 + #define mmSDMA1_RLC0_RB_BASE_HI 0x0142 371 + #define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 372 + #define mmSDMA1_RLC0_RB_RPTR 0x0143 373 + #define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0 374 + #define mmSDMA1_RLC0_RB_RPTR_HI 0x0144 375 + #define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 376 + #define mmSDMA1_RLC0_RB_WPTR 0x0145 377 + #define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0 378 + #define mmSDMA1_RLC0_RB_WPTR_HI 0x0146 379 + #define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 380 + #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147 381 + #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 382 + #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0148 383 + #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 384 + #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0149 385 + #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 386 + #define mmSDMA1_RLC0_IB_CNTL 0x014a 387 + #define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0 388 + #define mmSDMA1_RLC0_IB_RPTR 0x014b 389 + #define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0 390 + #define mmSDMA1_RLC0_IB_OFFSET 0x014c 391 + #define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 392 + #define mmSDMA1_RLC0_IB_BASE_LO 0x014d 393 + #define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 394 + #define mmSDMA1_RLC0_IB_BASE_HI 0x014e 395 + #define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 396 + #define mmSDMA1_RLC0_IB_SIZE 0x014f 397 + #define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0 398 + #define mmSDMA1_RLC0_SKIP_CNTL 0x0150 399 + #define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 400 + #define mmSDMA1_RLC0_CONTEXT_STATUS 0x0151 401 + #define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 402 + #define mmSDMA1_RLC0_DOORBELL 0x0152 403 + #define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0 404 + #define mmSDMA1_RLC0_STATUS 0x0168 405 + #define mmSDMA1_RLC0_STATUS_BASE_IDX 0 406 + #define mmSDMA1_RLC0_DOORBELL_LOG 0x0169 407 + #define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 408 + #define mmSDMA1_RLC0_WATERMARK 0x016a 409 + #define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0 410 + #define mmSDMA1_RLC0_DOORBELL_OFFSET 0x016b 411 + #define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 412 + #define mmSDMA1_RLC0_CSA_ADDR_LO 0x016c 413 + #define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 414 + #define mmSDMA1_RLC0_CSA_ADDR_HI 0x016d 415 + #define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 416 + #define mmSDMA1_RLC0_IB_SUB_REMAIN 0x016f 417 + #define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 418 + #define mmSDMA1_RLC0_PREEMPT 0x0170 419 + #define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0 420 + #define mmSDMA1_RLC0_DUMMY_REG 0x0171 421 + #define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 422 + #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 423 + #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 424 + #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 425 + #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 426 + #define mmSDMA1_RLC0_RB_AQL_CNTL 0x0174 427 + #define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 428 + #define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0175 429 + #define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 430 + #define mmSDMA1_RLC0_MIDCMD_DATA0 0x0180 431 + #define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 432 + #define mmSDMA1_RLC0_MIDCMD_DATA1 0x0181 433 + #define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 434 + #define mmSDMA1_RLC0_MIDCMD_DATA2 0x0182 435 + #define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 436 + #define mmSDMA1_RLC0_MIDCMD_DATA3 0x0183 437 + #define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 438 + #define mmSDMA1_RLC0_MIDCMD_DATA4 0x0184 439 + #define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 440 + #define mmSDMA1_RLC0_MIDCMD_DATA5 0x0185 441 + #define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 442 + #define mmSDMA1_RLC0_MIDCMD_DATA6 0x0186 443 + #define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 444 + #define mmSDMA1_RLC0_MIDCMD_DATA7 0x0187 445 + #define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 446 + #define mmSDMA1_RLC0_MIDCMD_DATA8 0x0188 447 + #define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 448 + #define mmSDMA1_RLC0_MIDCMD_CNTL 0x0189 449 + #define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 450 + #define mmSDMA1_RLC1_RB_CNTL 0x01a0 451 + #define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0 452 + #define mmSDMA1_RLC1_RB_BASE 0x01a1 453 + #define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0 454 + #define mmSDMA1_RLC1_RB_BASE_HI 0x01a2 455 + #define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 456 + #define mmSDMA1_RLC1_RB_RPTR 0x01a3 457 + #define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0 458 + #define mmSDMA1_RLC1_RB_RPTR_HI 0x01a4 459 + #define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 460 + #define mmSDMA1_RLC1_RB_WPTR 0x01a5 461 + #define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0 462 + #define mmSDMA1_RLC1_RB_WPTR_HI 0x01a6 463 + #define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 464 + #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7 465 + #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 466 + #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8 467 + #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 468 + #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x01a9 469 + #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 470 + #define mmSDMA1_RLC1_IB_CNTL 0x01aa 471 + #define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0 472 + #define mmSDMA1_RLC1_IB_RPTR 0x01ab 473 + #define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0 474 + #define mmSDMA1_RLC1_IB_OFFSET 0x01ac 475 + #define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 476 + #define mmSDMA1_RLC1_IB_BASE_LO 0x01ad 477 + #define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 478 + #define mmSDMA1_RLC1_IB_BASE_HI 0x01ae 479 + #define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 480 + #define mmSDMA1_RLC1_IB_SIZE 0x01af 481 + #define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0 482 + #define mmSDMA1_RLC1_SKIP_CNTL 0x01b0 483 + #define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 484 + #define mmSDMA1_RLC1_CONTEXT_STATUS 0x01b1 485 + #define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 486 + #define mmSDMA1_RLC1_DOORBELL 0x01b2 487 + #define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0 488 + #define mmSDMA1_RLC1_STATUS 0x01c8 489 + #define mmSDMA1_RLC1_STATUS_BASE_IDX 0 490 + #define mmSDMA1_RLC1_DOORBELL_LOG 0x01c9 491 + #define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 492 + #define mmSDMA1_RLC1_WATERMARK 0x01ca 493 + #define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0 494 + #define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01cb 495 + #define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 496 + #define mmSDMA1_RLC1_CSA_ADDR_LO 0x01cc 497 + #define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 498 + #define mmSDMA1_RLC1_CSA_ADDR_HI 0x01cd 499 + #define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 500 + #define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01cf 501 + #define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 502 + #define mmSDMA1_RLC1_PREEMPT 0x01d0 503 + #define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0 504 + #define mmSDMA1_RLC1_DUMMY_REG 0x01d1 505 + #define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 506 + #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 507 + #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 508 + #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 509 + #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 510 + #define mmSDMA1_RLC1_RB_AQL_CNTL 0x01d4 511 + #define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 512 + #define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01d5 513 + #define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 514 + #define mmSDMA1_RLC1_MIDCMD_DATA0 0x01e0 515 + #define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 516 + #define mmSDMA1_RLC1_MIDCMD_DATA1 0x01e1 517 + #define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 518 + #define mmSDMA1_RLC1_MIDCMD_DATA2 0x01e2 519 + #define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 520 + #define mmSDMA1_RLC1_MIDCMD_DATA3 0x01e3 521 + #define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 522 + #define mmSDMA1_RLC1_MIDCMD_DATA4 0x01e4 523 + #define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 524 + #define mmSDMA1_RLC1_MIDCMD_DATA5 0x01e5 525 + #define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 526 + #define mmSDMA1_RLC1_MIDCMD_DATA6 0x01e6 527 + #define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 528 + #define mmSDMA1_RLC1_MIDCMD_DATA7 0x01e7 529 + #define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 530 + #define mmSDMA1_RLC1_MIDCMD_DATA8 0x01e8 531 + #define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 532 + #define mmSDMA1_RLC1_MIDCMD_CNTL 0x01e9 533 + #define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 534 + #define mmSDMA1_RLC2_RB_CNTL 0x0200 535 + #define mmSDMA1_RLC2_RB_CNTL_BASE_IDX 0 536 + #define mmSDMA1_RLC2_RB_BASE 0x0201 537 + #define mmSDMA1_RLC2_RB_BASE_BASE_IDX 0 538 + #define mmSDMA1_RLC2_RB_BASE_HI 0x0202 539 + #define mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX 0 540 + #define mmSDMA1_RLC2_RB_RPTR 0x0203 541 + #define mmSDMA1_RLC2_RB_RPTR_BASE_IDX 0 542 + #define mmSDMA1_RLC2_RB_RPTR_HI 0x0204 543 + #define mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX 0 544 + #define mmSDMA1_RLC2_RB_WPTR 0x0205 545 + #define mmSDMA1_RLC2_RB_WPTR_BASE_IDX 0 546 + #define mmSDMA1_RLC2_RB_WPTR_HI 0x0206 547 + #define mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX 0 548 + #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL 0x0207 549 + #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 550 + #define mmSDMA1_RLC2_RB_RPTR_ADDR_HI 0x0208 551 + #define mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 552 + #define mmSDMA1_RLC2_RB_RPTR_ADDR_LO 0x0209 553 + #define mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 554 + #define mmSDMA1_RLC2_IB_CNTL 0x020a 555 + #define mmSDMA1_RLC2_IB_CNTL_BASE_IDX 0 556 + #define mmSDMA1_RLC2_IB_RPTR 0x020b 557 + #define mmSDMA1_RLC2_IB_RPTR_BASE_IDX 0 558 + #define mmSDMA1_RLC2_IB_OFFSET 0x020c 559 + #define mmSDMA1_RLC2_IB_OFFSET_BASE_IDX 0 560 + #define mmSDMA1_RLC2_IB_BASE_LO 0x020d 561 + #define mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX 0 562 + #define mmSDMA1_RLC2_IB_BASE_HI 0x020e 563 + #define mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX 0 564 + #define mmSDMA1_RLC2_IB_SIZE 0x020f 565 + #define mmSDMA1_RLC2_IB_SIZE_BASE_IDX 0 566 + #define mmSDMA1_RLC2_SKIP_CNTL 0x0210 567 + #define mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX 0 568 + #define mmSDMA1_RLC2_CONTEXT_STATUS 0x0211 569 + #define mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX 0 570 + #define mmSDMA1_RLC2_DOORBELL 0x0212 571 + #define mmSDMA1_RLC2_DOORBELL_BASE_IDX 0 572 + #define mmSDMA1_RLC2_STATUS 0x0228 573 + #define mmSDMA1_RLC2_STATUS_BASE_IDX 0 574 + #define mmSDMA1_RLC2_DOORBELL_LOG 0x0229 575 + #define mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX 0 576 + #define mmSDMA1_RLC2_WATERMARK 0x022a 577 + #define mmSDMA1_RLC2_WATERMARK_BASE_IDX 0 578 + #define mmSDMA1_RLC2_DOORBELL_OFFSET 0x022b 579 + #define mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX 0 580 + #define mmSDMA1_RLC2_CSA_ADDR_LO 0x022c 581 + #define mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX 0 582 + #define mmSDMA1_RLC2_CSA_ADDR_HI 0x022d 583 + #define mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX 0 584 + #define mmSDMA1_RLC2_IB_SUB_REMAIN 0x022f 585 + #define mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX 0 586 + #define mmSDMA1_RLC2_PREEMPT 0x0230 587 + #define mmSDMA1_RLC2_PREEMPT_BASE_IDX 0 588 + #define mmSDMA1_RLC2_DUMMY_REG 0x0231 589 + #define mmSDMA1_RLC2_DUMMY_REG_BASE_IDX 0 590 + #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 0x0232 591 + #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 592 + #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 0x0233 593 + #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 594 + #define mmSDMA1_RLC2_RB_AQL_CNTL 0x0234 595 + #define mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX 0 596 + #define mmSDMA1_RLC2_MINOR_PTR_UPDATE 0x0235 597 + #define mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 598 + #define mmSDMA1_RLC2_MIDCMD_DATA0 0x0240 599 + #define mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX 0 600 + #define mmSDMA1_RLC2_MIDCMD_DATA1 0x0241 601 + #define mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX 0 602 + #define mmSDMA1_RLC2_MIDCMD_DATA2 0x0242 603 + #define mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX 0 604 + #define mmSDMA1_RLC2_MIDCMD_DATA3 0x0243 605 + #define mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX 0 606 + #define mmSDMA1_RLC2_MIDCMD_DATA4 0x0244 607 + #define mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX 0 608 + #define mmSDMA1_RLC2_MIDCMD_DATA5 0x0245 609 + #define mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX 0 610 + #define mmSDMA1_RLC2_MIDCMD_DATA6 0x0246 611 + #define mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX 0 612 + #define mmSDMA1_RLC2_MIDCMD_DATA7 0x0247 613 + #define mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX 0 614 + #define mmSDMA1_RLC2_MIDCMD_DATA8 0x0248 615 + #define mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX 0 616 + #define mmSDMA1_RLC2_MIDCMD_CNTL 0x0249 617 + #define mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX 0 618 + #define mmSDMA1_RLC3_RB_CNTL 0x0260 619 + #define mmSDMA1_RLC3_RB_CNTL_BASE_IDX 0 620 + #define mmSDMA1_RLC3_RB_BASE 0x0261 621 + #define mmSDMA1_RLC3_RB_BASE_BASE_IDX 0 622 + #define mmSDMA1_RLC3_RB_BASE_HI 0x0262 623 + #define mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX 0 624 + #define mmSDMA1_RLC3_RB_RPTR 0x0263 625 + #define mmSDMA1_RLC3_RB_RPTR_BASE_IDX 0 626 + #define mmSDMA1_RLC3_RB_RPTR_HI 0x0264 627 + #define mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX 0 628 + #define mmSDMA1_RLC3_RB_WPTR 0x0265 629 + #define mmSDMA1_RLC3_RB_WPTR_BASE_IDX 0 630 + #define mmSDMA1_RLC3_RB_WPTR_HI 0x0266 631 + #define mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX 0 632 + #define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL 0x0267 633 + #define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 634 + #define mmSDMA1_RLC3_RB_RPTR_ADDR_HI 0x0268 635 + #define mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 636 + #define mmSDMA1_RLC3_RB_RPTR_ADDR_LO 0x0269 637 + #define mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 638 + #define mmSDMA1_RLC3_IB_CNTL 0x026a 639 + #define mmSDMA1_RLC3_IB_CNTL_BASE_IDX 0 640 + #define mmSDMA1_RLC3_IB_RPTR 0x026b 641 + #define mmSDMA1_RLC3_IB_RPTR_BASE_IDX 0 642 + #define mmSDMA1_RLC3_IB_OFFSET 0x026c 643 + #define mmSDMA1_RLC3_IB_OFFSET_BASE_IDX 0 644 + #define mmSDMA1_RLC3_IB_BASE_LO 0x026d 645 + #define mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX 0 646 + #define mmSDMA1_RLC3_IB_BASE_HI 0x026e 647 + #define mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX 0 648 + #define mmSDMA1_RLC3_IB_SIZE 0x026f 649 + #define mmSDMA1_RLC3_IB_SIZE_BASE_IDX 0 650 + #define mmSDMA1_RLC3_SKIP_CNTL 0x0270 651 + #define mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX 0 652 + #define mmSDMA1_RLC3_CONTEXT_STATUS 0x0271 653 + #define mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX 0 654 + #define mmSDMA1_RLC3_DOORBELL 0x0272 655 + #define mmSDMA1_RLC3_DOORBELL_BASE_IDX 0 656 + #define mmSDMA1_RLC3_STATUS 0x0288 657 + #define mmSDMA1_RLC3_STATUS_BASE_IDX 0 658 + #define mmSDMA1_RLC3_DOORBELL_LOG 0x0289 659 + #define mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX 0 660 + #define mmSDMA1_RLC3_WATERMARK 0x028a 661 + #define mmSDMA1_RLC3_WATERMARK_BASE_IDX 0 662 + #define mmSDMA1_RLC3_DOORBELL_OFFSET 0x028b 663 + #define mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX 0 664 + #define mmSDMA1_RLC3_CSA_ADDR_LO 0x028c 665 + #define mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX 0 666 + #define mmSDMA1_RLC3_CSA_ADDR_HI 0x028d 667 + #define mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX 0 668 + #define mmSDMA1_RLC3_IB_SUB_REMAIN 0x028f 669 + #define mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX 0 670 + #define mmSDMA1_RLC3_PREEMPT 0x0290 671 + #define mmSDMA1_RLC3_PREEMPT_BASE_IDX 0 672 + #define mmSDMA1_RLC3_DUMMY_REG 0x0291 673 + #define mmSDMA1_RLC3_DUMMY_REG_BASE_IDX 0 674 + #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 0x0292 675 + #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 676 + #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 0x0293 677 + #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 678 + #define mmSDMA1_RLC3_RB_AQL_CNTL 0x0294 679 + #define mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX 0 680 + #define mmSDMA1_RLC3_MINOR_PTR_UPDATE 0x0295 681 + #define mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 682 + #define mmSDMA1_RLC3_MIDCMD_DATA0 0x02a0 683 + #define mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX 0 684 + #define mmSDMA1_RLC3_MIDCMD_DATA1 0x02a1 685 + #define mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX 0 686 + #define mmSDMA1_RLC3_MIDCMD_DATA2 0x02a2 687 + #define mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX 0 688 + #define mmSDMA1_RLC3_MIDCMD_DATA3 0x02a3 689 + #define mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX 0 690 + #define mmSDMA1_RLC3_MIDCMD_DATA4 0x02a4 691 + #define mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX 0 692 + #define mmSDMA1_RLC3_MIDCMD_DATA5 0x02a5 693 + #define mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX 0 694 + #define mmSDMA1_RLC3_MIDCMD_DATA6 0x02a6 695 + #define mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX 0 696 + #define mmSDMA1_RLC3_MIDCMD_DATA7 0x02a7 697 + #define mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX 0 698 + #define mmSDMA1_RLC3_MIDCMD_DATA8 0x02a8 699 + #define mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX 0 700 + #define mmSDMA1_RLC3_MIDCMD_CNTL 0x02a9 701 + #define mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX 0 702 + #define mmSDMA1_RLC4_RB_CNTL 0x02c0 703 + #define mmSDMA1_RLC4_RB_CNTL_BASE_IDX 0 704 + #define mmSDMA1_RLC4_RB_BASE 0x02c1 705 + #define mmSDMA1_RLC4_RB_BASE_BASE_IDX 0 706 + #define mmSDMA1_RLC4_RB_BASE_HI 0x02c2 707 + #define mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX 0 708 + #define mmSDMA1_RLC4_RB_RPTR 0x02c3 709 + #define mmSDMA1_RLC4_RB_RPTR_BASE_IDX 0 710 + #define mmSDMA1_RLC4_RB_RPTR_HI 0x02c4 711 + #define mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX 0 712 + #define mmSDMA1_RLC4_RB_WPTR 0x02c5 713 + #define mmSDMA1_RLC4_RB_WPTR_BASE_IDX 0 714 + #define mmSDMA1_RLC4_RB_WPTR_HI 0x02c6 715 + #define mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX 0 716 + #define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL 0x02c7 717 + #define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 718 + #define mmSDMA1_RLC4_RB_RPTR_ADDR_HI 0x02c8 719 + #define mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 720 + #define mmSDMA1_RLC4_RB_RPTR_ADDR_LO 0x02c9 721 + #define mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 722 + #define mmSDMA1_RLC4_IB_CNTL 0x02ca 723 + #define mmSDMA1_RLC4_IB_CNTL_BASE_IDX 0 724 + #define mmSDMA1_RLC4_IB_RPTR 0x02cb 725 + #define mmSDMA1_RLC4_IB_RPTR_BASE_IDX 0 726 + #define mmSDMA1_RLC4_IB_OFFSET 0x02cc 727 + #define mmSDMA1_RLC4_IB_OFFSET_BASE_IDX 0 728 + #define mmSDMA1_RLC4_IB_BASE_LO 0x02cd 729 + #define mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX 0 730 + #define mmSDMA1_RLC4_IB_BASE_HI 0x02ce 731 + #define mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX 0 732 + #define mmSDMA1_RLC4_IB_SIZE 0x02cf 733 + #define mmSDMA1_RLC4_IB_SIZE_BASE_IDX 0 734 + #define mmSDMA1_RLC4_SKIP_CNTL 0x02d0 735 + #define mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX 0 736 + #define mmSDMA1_RLC4_CONTEXT_STATUS 0x02d1 737 + #define mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX 0 738 + #define mmSDMA1_RLC4_DOORBELL 0x02d2 739 + #define mmSDMA1_RLC4_DOORBELL_BASE_IDX 0 740 + #define mmSDMA1_RLC4_STATUS 0x02e8 741 + #define mmSDMA1_RLC4_STATUS_BASE_IDX 0 742 + #define mmSDMA1_RLC4_DOORBELL_LOG 0x02e9 743 + #define mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX 0 744 + #define mmSDMA1_RLC4_WATERMARK 0x02ea 745 + #define mmSDMA1_RLC4_WATERMARK_BASE_IDX 0 746 + #define mmSDMA1_RLC4_DOORBELL_OFFSET 0x02eb 747 + #define mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX 0 748 + #define mmSDMA1_RLC4_CSA_ADDR_LO 0x02ec 749 + #define mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX 0 750 + #define mmSDMA1_RLC4_CSA_ADDR_HI 0x02ed 751 + #define mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX 0 752 + #define mmSDMA1_RLC4_IB_SUB_REMAIN 0x02ef 753 + #define mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX 0 754 + #define mmSDMA1_RLC4_PREEMPT 0x02f0 755 + #define mmSDMA1_RLC4_PREEMPT_BASE_IDX 0 756 + #define mmSDMA1_RLC4_DUMMY_REG 0x02f1 757 + #define mmSDMA1_RLC4_DUMMY_REG_BASE_IDX 0 758 + #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 0x02f2 759 + #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 760 + #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 0x02f3 761 + #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 762 + #define mmSDMA1_RLC4_RB_AQL_CNTL 0x02f4 763 + #define mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX 0 764 + #define mmSDMA1_RLC4_MINOR_PTR_UPDATE 0x02f5 765 + #define mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 766 + #define mmSDMA1_RLC4_MIDCMD_DATA0 0x0300 767 + #define mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX 0 768 + #define mmSDMA1_RLC4_MIDCMD_DATA1 0x0301 769 + #define mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX 0 770 + #define mmSDMA1_RLC4_MIDCMD_DATA2 0x0302 771 + #define mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX 0 772 + #define mmSDMA1_RLC4_MIDCMD_DATA3 0x0303 773 + #define mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX 0 774 + #define mmSDMA1_RLC4_MIDCMD_DATA4 0x0304 775 + #define mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX 0 776 + #define mmSDMA1_RLC4_MIDCMD_DATA5 0x0305 777 + #define mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX 0 778 + #define mmSDMA1_RLC4_MIDCMD_DATA6 0x0306 779 + #define mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX 0 780 + #define mmSDMA1_RLC4_MIDCMD_DATA7 0x0307 781 + #define mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX 0 782 + #define mmSDMA1_RLC4_MIDCMD_DATA8 0x0308 783 + #define mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX 0 784 + #define mmSDMA1_RLC4_MIDCMD_CNTL 0x0309 785 + #define mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX 0 786 + #define mmSDMA1_RLC5_RB_CNTL 0x0320 787 + #define mmSDMA1_RLC5_RB_CNTL_BASE_IDX 0 788 + #define mmSDMA1_RLC5_RB_BASE 0x0321 789 + #define mmSDMA1_RLC5_RB_BASE_BASE_IDX 0 790 + #define mmSDMA1_RLC5_RB_BASE_HI 0x0322 791 + #define mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX 0 792 + #define mmSDMA1_RLC5_RB_RPTR 0x0323 793 + #define mmSDMA1_RLC5_RB_RPTR_BASE_IDX 0 794 + #define mmSDMA1_RLC5_RB_RPTR_HI 0x0324 795 + #define mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX 0 796 + #define mmSDMA1_RLC5_RB_WPTR 0x0325 797 + #define mmSDMA1_RLC5_RB_WPTR_BASE_IDX 0 798 + #define mmSDMA1_RLC5_RB_WPTR_HI 0x0326 799 + #define mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX 0 800 + #define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL 0x0327 801 + #define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 802 + #define mmSDMA1_RLC5_RB_RPTR_ADDR_HI 0x0328 803 + #define mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 804 + #define mmSDMA1_RLC5_RB_RPTR_ADDR_LO 0x0329 805 + #define mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 806 + #define mmSDMA1_RLC5_IB_CNTL 0x032a 807 + #define mmSDMA1_RLC5_IB_CNTL_BASE_IDX 0 808 + #define mmSDMA1_RLC5_IB_RPTR 0x032b 809 + #define mmSDMA1_RLC5_IB_RPTR_BASE_IDX 0 810 + #define mmSDMA1_RLC5_IB_OFFSET 0x032c 811 + #define mmSDMA1_RLC5_IB_OFFSET_BASE_IDX 0 812 + #define mmSDMA1_RLC5_IB_BASE_LO 0x032d 813 + #define mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX 0 814 + #define mmSDMA1_RLC5_IB_BASE_HI 0x032e 815 + #define mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX 0 816 + #define mmSDMA1_RLC5_IB_SIZE 0x032f 817 + #define mmSDMA1_RLC5_IB_SIZE_BASE_IDX 0 818 + #define mmSDMA1_RLC5_SKIP_CNTL 0x0330 819 + #define mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX 0 820 + #define mmSDMA1_RLC5_CONTEXT_STATUS 0x0331 821 + #define mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX 0 822 + #define mmSDMA1_RLC5_DOORBELL 0x0332 823 + #define mmSDMA1_RLC5_DOORBELL_BASE_IDX 0 824 + #define mmSDMA1_RLC5_STATUS 0x0348 825 + #define mmSDMA1_RLC5_STATUS_BASE_IDX 0 826 + #define mmSDMA1_RLC5_DOORBELL_LOG 0x0349 827 + #define mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX 0 828 + #define mmSDMA1_RLC5_WATERMARK 0x034a 829 + #define mmSDMA1_RLC5_WATERMARK_BASE_IDX 0 830 + #define mmSDMA1_RLC5_DOORBELL_OFFSET 0x034b 831 + #define mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX 0 832 + #define mmSDMA1_RLC5_CSA_ADDR_LO 0x034c 833 + #define mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX 0 834 + #define mmSDMA1_RLC5_CSA_ADDR_HI 0x034d 835 + #define mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX 0 836 + #define mmSDMA1_RLC5_IB_SUB_REMAIN 0x034f 837 + #define mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX 0 838 + #define mmSDMA1_RLC5_PREEMPT 0x0350 839 + #define mmSDMA1_RLC5_PREEMPT_BASE_IDX 0 840 + #define mmSDMA1_RLC5_DUMMY_REG 0x0351 841 + #define mmSDMA1_RLC5_DUMMY_REG_BASE_IDX 0 842 + #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 0x0352 843 + #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 844 + #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 0x0353 845 + #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 846 + #define mmSDMA1_RLC5_RB_AQL_CNTL 0x0354 847 + #define mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX 0 848 + #define mmSDMA1_RLC5_MINOR_PTR_UPDATE 0x0355 849 + #define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 850 + #define mmSDMA1_RLC5_MIDCMD_DATA0 0x0360 851 + #define mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX 0 852 + #define mmSDMA1_RLC5_MIDCMD_DATA1 0x0361 853 + #define mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX 0 854 + #define mmSDMA1_RLC5_MIDCMD_DATA2 0x0362 855 + #define mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX 0 856 + #define mmSDMA1_RLC5_MIDCMD_DATA3 0x0363 857 + #define mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX 0 858 + #define mmSDMA1_RLC5_MIDCMD_DATA4 0x0364 859 + #define mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX 0 860 + #define mmSDMA1_RLC5_MIDCMD_DATA5 0x0365 861 + #define mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX 0 862 + #define mmSDMA1_RLC5_MIDCMD_DATA6 0x0366 863 + #define mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX 0 864 + #define mmSDMA1_RLC5_MIDCMD_DATA7 0x0367 865 + #define mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX 0 866 + #define mmSDMA1_RLC5_MIDCMD_DATA8 0x0368 867 + #define mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX 0 868 + #define mmSDMA1_RLC5_MIDCMD_CNTL 0x0369 869 + #define mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX 0 870 + #define mmSDMA1_RLC6_RB_CNTL 0x0380 871 + #define mmSDMA1_RLC6_RB_CNTL_BASE_IDX 0 872 + #define mmSDMA1_RLC6_RB_BASE 0x0381 873 + #define mmSDMA1_RLC6_RB_BASE_BASE_IDX 0 874 + #define mmSDMA1_RLC6_RB_BASE_HI 0x0382 875 + #define mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX 0 876 + #define mmSDMA1_RLC6_RB_RPTR 0x0383 877 + #define mmSDMA1_RLC6_RB_RPTR_BASE_IDX 0 878 + #define mmSDMA1_RLC6_RB_RPTR_HI 0x0384 879 + #define mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX 0 880 + #define mmSDMA1_RLC6_RB_WPTR 0x0385 881 + #define mmSDMA1_RLC6_RB_WPTR_BASE_IDX 0 882 + #define mmSDMA1_RLC6_RB_WPTR_HI 0x0386 883 + #define mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX 0 884 + #define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL 0x0387 885 + #define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 886 + #define mmSDMA1_RLC6_RB_RPTR_ADDR_HI 0x0388 887 + #define mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 888 + #define mmSDMA1_RLC6_RB_RPTR_ADDR_LO 0x0389 889 + #define mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 890 + #define mmSDMA1_RLC6_IB_CNTL 0x038a 891 + #define mmSDMA1_RLC6_IB_CNTL_BASE_IDX 0 892 + #define mmSDMA1_RLC6_IB_RPTR 0x038b 893 + #define mmSDMA1_RLC6_IB_RPTR_BASE_IDX 0 894 + #define mmSDMA1_RLC6_IB_OFFSET 0x038c 895 + #define mmSDMA1_RLC6_IB_OFFSET_BASE_IDX 0 896 + #define mmSDMA1_RLC6_IB_BASE_LO 0x038d 897 + #define mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX 0 898 + #define mmSDMA1_RLC6_IB_BASE_HI 0x038e 899 + #define mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX 0 900 + #define mmSDMA1_RLC6_IB_SIZE 0x038f 901 + #define mmSDMA1_RLC6_IB_SIZE_BASE_IDX 0 902 + #define mmSDMA1_RLC6_SKIP_CNTL 0x0390 903 + #define mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX 0 904 + #define mmSDMA1_RLC6_CONTEXT_STATUS 0x0391 905 + #define mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX 0 906 + #define mmSDMA1_RLC6_DOORBELL 0x0392 907 + #define mmSDMA1_RLC6_DOORBELL_BASE_IDX 0 908 + #define mmSDMA1_RLC6_STATUS 0x03a8 909 + #define mmSDMA1_RLC6_STATUS_BASE_IDX 0 910 + #define mmSDMA1_RLC6_DOORBELL_LOG 0x03a9 911 + #define mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX 0 912 + #define mmSDMA1_RLC6_WATERMARK 0x03aa 913 + #define mmSDMA1_RLC6_WATERMARK_BASE_IDX 0 914 + #define mmSDMA1_RLC6_DOORBELL_OFFSET 0x03ab 915 + #define mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX 0 916 + #define mmSDMA1_RLC6_CSA_ADDR_LO 0x03ac 917 + #define mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX 0 918 + #define mmSDMA1_RLC6_CSA_ADDR_HI 0x03ad 919 + #define mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX 0 920 + #define mmSDMA1_RLC6_IB_SUB_REMAIN 0x03af 921 + #define mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX 0 922 + #define mmSDMA1_RLC6_PREEMPT 0x03b0 923 + #define mmSDMA1_RLC6_PREEMPT_BASE_IDX 0 924 + #define mmSDMA1_RLC6_DUMMY_REG 0x03b1 925 + #define mmSDMA1_RLC6_DUMMY_REG_BASE_IDX 0 926 + #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 0x03b2 927 + #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 928 + #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 0x03b3 929 + #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 930 + #define mmSDMA1_RLC6_RB_AQL_CNTL 0x03b4 931 + #define mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX 0 932 + #define mmSDMA1_RLC6_MINOR_PTR_UPDATE 0x03b5 933 + #define mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 934 + #define mmSDMA1_RLC6_MIDCMD_DATA0 0x03c0 935 + #define mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX 0 936 + #define mmSDMA1_RLC6_MIDCMD_DATA1 0x03c1 937 + #define mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX 0 938 + #define mmSDMA1_RLC6_MIDCMD_DATA2 0x03c2 939 + #define mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX 0 940 + #define mmSDMA1_RLC6_MIDCMD_DATA3 0x03c3 941 + #define mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX 0 942 + #define mmSDMA1_RLC6_MIDCMD_DATA4 0x03c4 943 + #define mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX 0 944 + #define mmSDMA1_RLC6_MIDCMD_DATA5 0x03c5 945 + #define mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX 0 946 + #define mmSDMA1_RLC6_MIDCMD_DATA6 0x03c6 947 + #define mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX 0 948 + #define mmSDMA1_RLC6_MIDCMD_DATA7 0x03c7 949 + #define mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX 0 950 + #define mmSDMA1_RLC6_MIDCMD_DATA8 0x03c8 951 + #define mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX 0 952 + #define mmSDMA1_RLC6_MIDCMD_CNTL 0x03c9 953 + #define mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX 0 954 + #define mmSDMA1_RLC7_RB_CNTL 0x03e0 955 + #define mmSDMA1_RLC7_RB_CNTL_BASE_IDX 0 956 + #define mmSDMA1_RLC7_RB_BASE 0x03e1 957 + #define mmSDMA1_RLC7_RB_BASE_BASE_IDX 0 958 + #define mmSDMA1_RLC7_RB_BASE_HI 0x03e2 959 + #define mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX 0 960 + #define mmSDMA1_RLC7_RB_RPTR 0x03e3 961 + #define mmSDMA1_RLC7_RB_RPTR_BASE_IDX 0 962 + #define mmSDMA1_RLC7_RB_RPTR_HI 0x03e4 963 + #define mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX 0 964 + #define mmSDMA1_RLC7_RB_WPTR 0x03e5 965 + #define mmSDMA1_RLC7_RB_WPTR_BASE_IDX 0 966 + #define mmSDMA1_RLC7_RB_WPTR_HI 0x03e6 967 + #define mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX 0 968 + #define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL 0x03e7 969 + #define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 970 + #define mmSDMA1_RLC7_RB_RPTR_ADDR_HI 0x03e8 971 + #define mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 972 + #define mmSDMA1_RLC7_RB_RPTR_ADDR_LO 0x03e9 973 + #define mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 974 + #define mmSDMA1_RLC7_IB_CNTL 0x03ea 975 + #define mmSDMA1_RLC7_IB_CNTL_BASE_IDX 0 976 + #define mmSDMA1_RLC7_IB_RPTR 0x03eb 977 + #define mmSDMA1_RLC7_IB_RPTR_BASE_IDX 0 978 + #define mmSDMA1_RLC7_IB_OFFSET 0x03ec 979 + #define mmSDMA1_RLC7_IB_OFFSET_BASE_IDX 0 980 + #define mmSDMA1_RLC7_IB_BASE_LO 0x03ed 981 + #define mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX 0 982 + #define mmSDMA1_RLC7_IB_BASE_HI 0x03ee 983 + #define mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX 0 984 + #define mmSDMA1_RLC7_IB_SIZE 0x03ef 985 + #define mmSDMA1_RLC7_IB_SIZE_BASE_IDX 0 986 + #define mmSDMA1_RLC7_SKIP_CNTL 0x03f0 987 + #define mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX 0 988 + #define mmSDMA1_RLC7_CONTEXT_STATUS 0x03f1 989 + #define mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX 0 990 + #define mmSDMA1_RLC7_DOORBELL 0x03f2 991 + #define mmSDMA1_RLC7_DOORBELL_BASE_IDX 0 992 + #define mmSDMA1_RLC7_STATUS 0x0408 993 + #define mmSDMA1_RLC7_STATUS_BASE_IDX 0 994 + #define mmSDMA1_RLC7_DOORBELL_LOG 0x0409 995 + #define mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX 0 996 + #define mmSDMA1_RLC7_WATERMARK 0x040a 997 + #define mmSDMA1_RLC7_WATERMARK_BASE_IDX 0 998 + #define mmSDMA1_RLC7_DOORBELL_OFFSET 0x040b 999 + #define mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX 0 1000 + #define mmSDMA1_RLC7_CSA_ADDR_LO 0x040c 1001 + #define mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX 0 1002 + #define mmSDMA1_RLC7_CSA_ADDR_HI 0x040d 1003 + #define mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX 0 1004 + #define mmSDMA1_RLC7_IB_SUB_REMAIN 0x040f 1005 + #define mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX 0 1006 + #define mmSDMA1_RLC7_PREEMPT 0x0410 1007 + #define mmSDMA1_RLC7_PREEMPT_BASE_IDX 0 1008 + #define mmSDMA1_RLC7_DUMMY_REG 0x0411 1009 + #define mmSDMA1_RLC7_DUMMY_REG_BASE_IDX 0 1010 + #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 0x0412 1011 + #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 1012 + #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 0x0413 1013 + #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 1014 + #define mmSDMA1_RLC7_RB_AQL_CNTL 0x0414 1015 + #define mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX 0 1016 + #define mmSDMA1_RLC7_MINOR_PTR_UPDATE 0x0415 1017 + #define mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 1018 + #define mmSDMA1_RLC7_MIDCMD_DATA0 0x0420 1019 + #define mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX 0 1020 + #define mmSDMA1_RLC7_MIDCMD_DATA1 0x0421 1021 + #define mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX 0 1022 + #define mmSDMA1_RLC7_MIDCMD_DATA2 0x0422 1023 + #define mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX 0 1024 + #define mmSDMA1_RLC7_MIDCMD_DATA3 0x0423 1025 + #define mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX 0 1026 + #define mmSDMA1_RLC7_MIDCMD_DATA4 0x0424 1027 + #define mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX 0 1028 + #define mmSDMA1_RLC7_MIDCMD_DATA5 0x0425 1029 + #define mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX 0 1030 + #define mmSDMA1_RLC7_MIDCMD_DATA6 0x0426 1031 + #define mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX 0 1032 + #define mmSDMA1_RLC7_MIDCMD_DATA7 0x0427 1033 + #define mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX 0 1034 + #define mmSDMA1_RLC7_MIDCMD_DATA8 0x0428 1035 + #define mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX 0 1036 + #define mmSDMA1_RLC7_MIDCMD_CNTL 0x0429 1037 + #define mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX 0 1038 + 1039 + #endif
+2948
drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h
··· 1 + /* 2 + * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _sdma1_4_2_0_SH_MASK_HEADER 22 + #define _sdma1_4_2_0_SH_MASK_HEADER 23 + 24 + 25 + // addressBlock: sdma1_sdma1dec 26 + //SDMA1_UCODE_ADDR 27 + #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 28 + #define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29 + //SDMA1_UCODE_DATA 30 + #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 31 + #define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32 + //SDMA1_VM_CNTL 33 + #define SDMA1_VM_CNTL__CMD__SHIFT 0x0 34 + #define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL 35 + //SDMA1_VM_CTX_LO 36 + #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 37 + #define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38 + //SDMA1_VM_CTX_HI 39 + #define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 40 + #define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41 + //SDMA1_ACTIVE_FCN_ID 42 + #define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43 + #define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44 + #define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45 + #define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46 + #define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47 + #define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48 + //SDMA1_VM_CTX_CNTL 49 + #define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 50 + #define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 51 + #define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52 + #define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53 + //SDMA1_VIRT_RESET_REQ 54 + #define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 55 + #define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f 56 + #define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57 + #define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L 58 + //SDMA1_VF_ENABLE 59 + #define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 60 + #define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 61 + //SDMA1_CONTEXT_REG_TYPE0 62 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 63 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 64 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 65 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 66 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 67 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 68 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 69 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 70 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 71 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 72 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa 73 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb 74 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc 75 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd 76 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe 77 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf 78 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 79 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 80 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 81 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 82 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L 83 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L 84 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L 85 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L 86 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L 87 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L 88 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L 89 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 90 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 91 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 92 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L 93 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L 94 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L 95 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L 96 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L 97 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L 98 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L 99 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L 100 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L 101 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L 102 + //SDMA1_CONTEXT_REG_TYPE1 103 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 104 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 105 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa 106 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb 107 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc 108 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd 109 + #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 110 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf 111 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 112 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 113 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 114 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 115 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 116 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 117 + #define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 118 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L 119 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L 120 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L 121 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L 122 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L 123 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L 124 + #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 125 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L 126 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L 127 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L 128 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 129 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 130 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L 131 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 132 + #define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 133 + //SDMA1_CONTEXT_REG_TYPE2 134 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 135 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 136 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 137 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 138 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 139 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 140 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 141 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 142 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 143 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 144 + #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 145 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L 146 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L 147 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L 148 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L 149 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L 150 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L 151 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L 152 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L 153 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L 154 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L 155 + #define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 156 + //SDMA1_CONTEXT_REG_TYPE3 157 + #define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 158 + #define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 159 + //SDMA1_PUB_REG_TYPE0 160 + #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 161 + #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 162 + #define SDMA1_PUB_REG_TYPE0__SDMA1_REGISTER_SECURITY_CNTL__SHIFT 0x2 163 + #define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 164 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 165 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 166 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 167 + #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 168 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 169 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 170 + #define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 171 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb 172 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc 173 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd 174 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe 175 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf 176 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 177 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 178 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 179 + #define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 180 + #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 181 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 182 + #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a 183 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b 184 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c 185 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d 186 + #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e 187 + #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f 188 + #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L 189 + #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L 190 + #define SDMA1_PUB_REG_TYPE0__SDMA1_REGISTER_SECURITY_CNTL_MASK 0x00000004L 191 + #define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 192 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L 193 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L 194 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L 195 + #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L 196 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L 197 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L 198 + #define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 199 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L 200 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L 201 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L 202 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L 203 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L 204 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L 205 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L 206 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L 207 + #define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L 208 + #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 209 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 210 + #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L 211 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L 212 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L 213 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L 214 + #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L 215 + #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L 216 + //SDMA1_PUB_REG_TYPE1 217 + #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 218 + #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 219 + #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 220 + #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 221 + #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 222 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 223 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 224 + #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 225 + #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 226 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 227 + #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa 228 + #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb 229 + #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc 230 + #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd 231 + #define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 232 + #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 233 + #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 234 + #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 235 + #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 236 + #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 237 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 238 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 239 + #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 240 + #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 241 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 242 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 243 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a 244 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b 245 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c 246 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d 247 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e 248 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f 249 + #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L 250 + #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 251 + #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L 252 + #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L 253 + #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L 254 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L 255 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L 256 + #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L 257 + #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L 258 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L 259 + #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L 260 + #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L 261 + #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L 262 + #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L 263 + #define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 264 + #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 265 + #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 266 + #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 267 + #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L 268 + #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L 269 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L 270 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L 271 + #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L 272 + #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L 273 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L 274 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L 275 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L 276 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L 277 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L 278 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L 279 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L 280 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L 281 + //SDMA1_PUB_REG_TYPE2 282 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 283 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 284 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 285 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 286 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 287 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 288 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 289 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 290 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 291 + #define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 292 + #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa 293 + #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb 294 + #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc 295 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd 296 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe 297 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf 298 + #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 299 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 300 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 301 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 302 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 303 + #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 304 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 305 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 306 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 307 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 308 + #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b 309 + #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 310 + #define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e 311 + #define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 312 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L 313 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L 314 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L 315 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L 316 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L 317 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L 318 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L 319 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L 320 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L 321 + #define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L 322 + #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L 323 + #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L 324 + #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L 325 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L 326 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L 327 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L 328 + #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L 329 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L 330 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L 331 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L 332 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L 333 + #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L 334 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L 335 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L 336 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L 337 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 338 + #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L 339 + #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 340 + #define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L 341 + #define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 342 + //SDMA1_PUB_REG_TYPE3 343 + #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 344 + #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 345 + #define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 346 + #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L 347 + #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 348 + #define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 349 + //SDMA1_MMHUB_CNTL 350 + #define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 351 + #define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 352 + //SDMA1_CONTEXT_GROUP_BOUNDARY 353 + #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 354 + #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 355 + //SDMA1_POWER_CNTL 356 + #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 357 + #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 358 + #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 359 + #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 360 + #define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 361 + #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 362 + #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 363 + #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 364 + #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 365 + #define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 366 + //SDMA1_CLK_CTRL 367 + #define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 368 + #define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 369 + #define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc 370 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 371 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 372 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 373 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 374 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 375 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 376 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 377 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 378 + #define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 379 + #define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 380 + #define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L 381 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 382 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 383 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 384 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 385 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 386 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 387 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 388 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 389 + //SDMA1_CNTL 390 + #define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 391 + #define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 392 + #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 393 + #define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 394 + #define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 395 + #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 396 + #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 397 + #define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 398 + #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 399 + #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 400 + #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 401 + #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L 402 + #define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 403 + #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 404 + #define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 405 + #define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 406 + #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 407 + #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 408 + #define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 409 + #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 410 + #define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 411 + #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 412 + //SDMA1_CHICKEN_BITS 413 + #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 414 + #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 415 + #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 416 + #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 417 + #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 418 + #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 419 + #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 420 + #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 421 + #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 422 + #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 423 + #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 424 + #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 425 + #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 426 + #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 427 + #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 428 + #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 429 + #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 430 + #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 431 + #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 432 + #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 433 + #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 434 + #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 435 + #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 436 + #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 437 + #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 438 + #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 439 + //SDMA1_GB_ADDR_CONFIG 440 + #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 441 + #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 442 + #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 443 + #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 444 + #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 445 + #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 446 + #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 447 + #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 448 + #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 449 + #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 450 + //SDMA1_GB_ADDR_CONFIG_READ 451 + #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 452 + #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 453 + #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 454 + #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 455 + #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 456 + #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 457 + #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 458 + #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 459 + #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 460 + #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 461 + //SDMA1_RB_RPTR_FETCH_HI 462 + #define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 463 + #define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 464 + //SDMA1_SEM_WAIT_FAIL_TIMER_CNTL 465 + #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 466 + #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 467 + //SDMA1_RB_RPTR_FETCH 468 + #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 469 + #define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 470 + //SDMA1_IB_OFFSET_FETCH 471 + #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 472 + #define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 473 + //SDMA1_PROGRAM 474 + #define SDMA1_PROGRAM__STREAM__SHIFT 0x0 475 + #define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL 476 + //SDMA1_STATUS_REG 477 + #define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 478 + #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 479 + #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 480 + #define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 481 + #define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 482 + #define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 483 + #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 484 + #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 485 + #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 486 + #define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 487 + #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa 488 + #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 489 + #define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc 490 + #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 491 + #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe 492 + #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 493 + #define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 494 + #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 495 + #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 496 + #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 497 + #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 498 + #define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 499 + #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 500 + #define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 501 + #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a 502 + #define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 503 + #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 504 + #define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e 505 + #define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 506 + #define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L 507 + #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L 508 + #define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L 509 + #define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L 510 + #define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 511 + #define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 512 + #define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 513 + #define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 514 + #define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 515 + #define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L 516 + #define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L 517 + #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 518 + #define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L 519 + #define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 520 + #define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 521 + #define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 522 + #define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 523 + #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 524 + #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 525 + #define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 526 + #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 527 + #define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 528 + #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 529 + #define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 530 + #define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L 531 + #define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 532 + #define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 533 + #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L 534 + #define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 535 + //SDMA1_STATUS1_REG 536 + #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 537 + #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 538 + #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 539 + #define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 540 + #define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 541 + #define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 542 + #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 543 + #define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 544 + #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 545 + #define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 546 + #define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 547 + #define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf 548 + #define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 549 + #define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 550 + #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 551 + #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 552 + #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 553 + #define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 554 + #define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 555 + #define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 556 + #define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 557 + #define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 558 + #define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 559 + #define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 560 + #define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 561 + #define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L 562 + #define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 563 + #define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 564 + //SDMA1_RD_BURST_CNTL 565 + #define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 566 + #define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 567 + #define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 568 + #define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 569 + //SDMA1_HBM_PAGE_CONFIG 570 + #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 571 + #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L 572 + //SDMA1_UCODE_CHECKSUM 573 + #define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 574 + #define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 575 + //SDMA1_F32_CNTL 576 + #define SDMA1_F32_CNTL__HALT__SHIFT 0x0 577 + #define SDMA1_F32_CNTL__STEP__SHIFT 0x1 578 + #define SDMA1_F32_CNTL__HALT_MASK 0x00000001L 579 + #define SDMA1_F32_CNTL__STEP_MASK 0x00000002L 580 + //SDMA1_FREEZE 581 + #define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 582 + #define SDMA1_FREEZE__FREEZE__SHIFT 0x4 583 + #define SDMA1_FREEZE__FROZEN__SHIFT 0x5 584 + #define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 585 + #define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L 586 + #define SDMA1_FREEZE__FREEZE_MASK 0x00000010L 587 + #define SDMA1_FREEZE__FROZEN_MASK 0x00000020L 588 + #define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L 589 + //SDMA1_PHASE0_QUANTUM 590 + #define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 591 + #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 592 + #define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 593 + #define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 594 + #define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 595 + #define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 596 + //SDMA1_PHASE1_QUANTUM 597 + #define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 598 + #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 599 + #define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 600 + #define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 601 + #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 602 + #define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 603 + //SDMA1_EDC_CONFIG 604 + #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 605 + #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 606 + #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 607 + #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 608 + //SDMA1_BA_THRESHOLD 609 + #define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 610 + #define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 611 + #define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 612 + #define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 613 + //SDMA1_ID 614 + #define SDMA1_ID__DEVICE_ID__SHIFT 0x0 615 + #define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL 616 + //SDMA1_VERSION 617 + #define SDMA1_VERSION__MINVER__SHIFT 0x0 618 + #define SDMA1_VERSION__MAJVER__SHIFT 0x8 619 + #define SDMA1_VERSION__REV__SHIFT 0x10 620 + #define SDMA1_VERSION__MINVER_MASK 0x0000007FL 621 + #define SDMA1_VERSION__MAJVER_MASK 0x00007F00L 622 + #define SDMA1_VERSION__REV_MASK 0x003F0000L 623 + //SDMA1_EDC_COUNTER 624 + #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 625 + #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 626 + #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 627 + #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 628 + #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 629 + #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 630 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 631 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 632 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 633 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 634 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 635 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 636 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 637 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 638 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf 639 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 640 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 641 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 642 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 643 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 644 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 645 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 646 + #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 647 + #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 648 + #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L 649 + #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 650 + #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 651 + #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 652 + #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 653 + #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 654 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 655 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 656 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 657 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 658 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 659 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 660 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 661 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 662 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L 663 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L 664 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L 665 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L 666 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L 667 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L 668 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L 669 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L 670 + #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L 671 + #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L 672 + //SDMA1_EDC_COUNTER_CLEAR 673 + #define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 674 + #define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 675 + //SDMA1_STATUS2_REG 676 + #define SDMA1_STATUS2_REG__ID__SHIFT 0x0 677 + #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 678 + #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 679 + #define SDMA1_STATUS2_REG__ID_MASK 0x00000003L 680 + #define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 681 + #define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 682 + //SDMA1_ATOMIC_CNTL 683 + #define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 684 + #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 685 + #define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 686 + #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 687 + //SDMA1_ATOMIC_PREOP_LO 688 + #define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 689 + #define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 690 + //SDMA1_ATOMIC_PREOP_HI 691 + #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 692 + #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 693 + //SDMA1_UTCL1_CNTL 694 + #define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 695 + #define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 696 + #define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 697 + #define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 698 + #define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 699 + #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 700 + #define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 701 + #define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 702 + #define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 703 + #define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 704 + #define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 705 + #define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 706 + //SDMA1_UTCL1_WATERMK 707 + #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 708 + #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 709 + #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 710 + #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 711 + #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL 712 + #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L 713 + #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L 714 + #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L 715 + //SDMA1_UTCL1_RD_STATUS 716 + #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 717 + #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 718 + #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 719 + #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 720 + #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 721 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 722 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 723 + #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 724 + #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 725 + #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 726 + #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 727 + #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 728 + #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 729 + #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 730 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 731 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 732 + #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 733 + #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 734 + #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 735 + #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 736 + #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 737 + #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 738 + #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 739 + #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 740 + #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 741 + #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 742 + #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 743 + #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 744 + #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 745 + #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 746 + #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 747 + #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 748 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 749 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 750 + #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 751 + #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 752 + #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 753 + #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 754 + #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 755 + #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 756 + #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 757 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 758 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 759 + #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 760 + #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 761 + #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 762 + #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 763 + #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 764 + #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 765 + #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 766 + #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 767 + #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 768 + #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 769 + #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 770 + //SDMA1_UTCL1_WR_STATUS 771 + #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 772 + #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 773 + #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 774 + #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 775 + #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 776 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 777 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 778 + #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 779 + #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 780 + #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 781 + #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 782 + #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 783 + #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 784 + #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 785 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 786 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 787 + #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 788 + #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 789 + #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 790 + #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 791 + #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 792 + #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 793 + #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 794 + #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 795 + #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 796 + #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 797 + #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 798 + #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 799 + #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 800 + #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 801 + #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 802 + #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 803 + #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 804 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 805 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 806 + #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 807 + #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 808 + #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 809 + #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 810 + #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 811 + #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 812 + #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 813 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 814 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 815 + #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 816 + #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 817 + #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 818 + #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 819 + #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 820 + #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 821 + #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 822 + #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 823 + #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 824 + #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 825 + #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 826 + #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 827 + //SDMA1_UTCL1_INV0 828 + #define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 829 + #define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 830 + #define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 831 + #define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 832 + #define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 833 + #define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 834 + #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 835 + #define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 836 + #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 837 + #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 838 + #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 839 + #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 840 + #define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 841 + #define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 842 + #define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 843 + #define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 844 + #define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 845 + #define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 846 + #define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 847 + #define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 848 + #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 849 + #define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 850 + #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 851 + #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 852 + #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 853 + #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 854 + #define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 855 + #define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 856 + //SDMA1_UTCL1_INV1 857 + #define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 858 + #define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 859 + //SDMA1_UTCL1_INV2 860 + #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 861 + #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 862 + //SDMA1_UTCL1_RD_XNACK0 863 + #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 864 + #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 865 + //SDMA1_UTCL1_RD_XNACK1 866 + #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 867 + #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 868 + #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 869 + #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 870 + #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 871 + #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 872 + #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 873 + #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 874 + //SDMA1_UTCL1_WR_XNACK0 875 + #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 876 + #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 877 + //SDMA1_UTCL1_WR_XNACK1 878 + #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 879 + #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 880 + #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 881 + #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 882 + #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 883 + #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 884 + #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 885 + #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 886 + //SDMA1_UTCL1_TIMEOUT 887 + #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 888 + #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 889 + #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 890 + #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 891 + //SDMA1_UTCL1_PAGE 892 + #define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 893 + #define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 894 + #define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 895 + #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 896 + #define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 897 + #define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 898 + #define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 899 + #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 900 + //SDMA1_POWER_CNTL_IDLE 901 + #define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 902 + #define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 903 + #define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 904 + #define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 905 + #define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 906 + #define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 907 + //SDMA1_RELAX_ORDERING_LUT 908 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 909 + #define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 910 + #define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 911 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 912 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 913 + #define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 914 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 915 + #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 916 + #define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 917 + #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 918 + #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 919 + #define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 920 + #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 921 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 922 + #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 923 + #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 924 + #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 925 + #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 926 + #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 927 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 928 + #define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 929 + #define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 930 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 931 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 932 + #define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 933 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 934 + #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 935 + #define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 936 + #define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 937 + #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 938 + #define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 939 + #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 940 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 941 + #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 942 + #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 943 + #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 944 + #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 945 + #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 946 + //SDMA1_CHICKEN_BITS_2 947 + #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 948 + #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 949 + //SDMA1_STATUS3_REG 950 + #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 951 + #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 952 + #define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 953 + #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 954 + #define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 955 + #define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 956 + #define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 957 + #define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 958 + #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 959 + #define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 960 + //SDMA1_PHYSICAL_ADDR_LO 961 + #define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 962 + #define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 963 + #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 964 + #define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 965 + #define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 966 + #define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 967 + #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 968 + #define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 969 + //SDMA1_PHYSICAL_ADDR_HI 970 + #define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 971 + #define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 972 + //SDMA1_PHASE2_QUANTUM 973 + #define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 974 + #define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 975 + #define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 976 + #define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 977 + #define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 978 + #define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 979 + //SDMA1_ERROR_LOG 980 + #define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 981 + #define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 982 + #define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 983 + #define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L 984 + //SDMA1_PUB_DUMMY_REG0 985 + #define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 986 + #define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 987 + //SDMA1_PUB_DUMMY_REG1 988 + #define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 989 + #define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 990 + //SDMA1_PUB_DUMMY_REG2 991 + #define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 992 + #define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 993 + //SDMA1_PUB_DUMMY_REG3 994 + #define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 995 + #define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 996 + //SDMA1_F32_COUNTER 997 + #define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 998 + #define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 999 + //SDMA1_PERFMON_CNTL 1000 + #define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1001 + #define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1002 + #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1003 + #define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1004 + #define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1005 + #define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1006 + #define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1007 + #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1008 + #define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1009 + #define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1010 + #define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1011 + #define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1012 + //SDMA1_PERFCOUNTER0_RESULT 1013 + #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1014 + #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1015 + //SDMA1_PERFCOUNTER1_RESULT 1016 + #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1017 + #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1018 + //SDMA1_PERFCOUNTER_TAG_DELAY_RANGE 1019 + #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1020 + #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1021 + #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1022 + #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1023 + #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1024 + #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1025 + //SDMA1_CRD_CNTL 1026 + #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1027 + #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1028 + #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1029 + #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1030 + //SDMA1_GPU_IOV_VIOLATION_LOG 1031 + #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1032 + #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1033 + #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1034 + #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1035 + #define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1036 + #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1037 + #define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1038 + #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1039 + #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1040 + #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1041 + #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1042 + #define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1043 + #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1044 + #define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1045 + //SDMA1_ULV_CNTL 1046 + #define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1047 + #define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 1048 + #define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 1049 + #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1050 + #define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1051 + #define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1052 + #define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1053 + #define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 1054 + #define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 1055 + #define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1056 + #define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1057 + #define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1058 + //SDMA1_EA_DBIT_ADDR_DATA 1059 + #define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1060 + #define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1061 + //SDMA1_EA_DBIT_ADDR_INDEX 1062 + #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1063 + #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1064 + //SDMA1_GFX_RB_CNTL 1065 + #define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1066 + #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1067 + #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1068 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1069 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1070 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1071 + #define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1072 + #define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1073 + #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1074 + #define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1075 + #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1076 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1077 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1078 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1079 + #define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1080 + #define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1081 + //SDMA1_GFX_RB_BASE 1082 + #define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 1083 + #define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1084 + //SDMA1_GFX_RB_BASE_HI 1085 + #define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1086 + #define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1087 + //SDMA1_GFX_RB_RPTR 1088 + #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1089 + #define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1090 + //SDMA1_GFX_RB_RPTR_HI 1091 + #define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1092 + #define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1093 + //SDMA1_GFX_RB_WPTR 1094 + #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1095 + #define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1096 + //SDMA1_GFX_RB_WPTR_HI 1097 + #define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1098 + #define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1099 + //SDMA1_GFX_RB_WPTR_POLL_CNTL 1100 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1101 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1102 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1103 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1104 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1105 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1106 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1107 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1108 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1109 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1110 + //SDMA1_GFX_RB_RPTR_ADDR_HI 1111 + #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1112 + #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1113 + //SDMA1_GFX_RB_RPTR_ADDR_LO 1114 + #define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1115 + #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1116 + #define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1117 + #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1118 + //SDMA1_GFX_IB_CNTL 1119 + #define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1120 + #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1121 + #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1122 + #define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1123 + #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1124 + #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1125 + #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1126 + #define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1127 + //SDMA1_GFX_IB_RPTR 1128 + #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1129 + #define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1130 + //SDMA1_GFX_IB_OFFSET 1131 + #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1132 + #define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1133 + //SDMA1_GFX_IB_BASE_LO 1134 + #define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1135 + #define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1136 + //SDMA1_GFX_IB_BASE_HI 1137 + #define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1138 + #define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1139 + //SDMA1_GFX_IB_SIZE 1140 + #define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 1141 + #define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1142 + //SDMA1_GFX_SKIP_CNTL 1143 + #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1144 + #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1145 + //SDMA1_GFX_CONTEXT_STATUS 1146 + #define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1147 + #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1148 + #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1149 + #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1150 + #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1151 + #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1152 + #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1153 + #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1154 + #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1155 + #define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1156 + #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1157 + #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1158 + #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1159 + #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1160 + #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1161 + #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1162 + //SDMA1_GFX_DOORBELL 1163 + #define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1164 + #define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1165 + #define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1166 + #define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1167 + //SDMA1_GFX_CONTEXT_CNTL 1168 + #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1169 + #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1170 + //SDMA1_GFX_STATUS 1171 + #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1172 + #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1173 + #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1174 + #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1175 + //SDMA1_GFX_DOORBELL_LOG 1176 + #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1177 + #define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1178 + #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1179 + #define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1180 + //SDMA1_GFX_WATERMARK 1181 + #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1182 + #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1183 + #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1184 + #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1185 + //SDMA1_GFX_DOORBELL_OFFSET 1186 + #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1187 + #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1188 + //SDMA1_GFX_CSA_ADDR_LO 1189 + #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1190 + #define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1191 + //SDMA1_GFX_CSA_ADDR_HI 1192 + #define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1193 + #define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1194 + //SDMA1_GFX_IB_SUB_REMAIN 1195 + #define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1196 + #define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1197 + //SDMA1_GFX_PREEMPT 1198 + #define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1199 + #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1200 + //SDMA1_GFX_DUMMY_REG 1201 + #define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1202 + #define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1203 + //SDMA1_GFX_RB_WPTR_POLL_ADDR_HI 1204 + #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1205 + #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1206 + //SDMA1_GFX_RB_WPTR_POLL_ADDR_LO 1207 + #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1208 + #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1209 + //SDMA1_GFX_RB_AQL_CNTL 1210 + #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1211 + #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1212 + #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1213 + #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1214 + #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1215 + #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1216 + //SDMA1_GFX_MINOR_PTR_UPDATE 1217 + #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1218 + #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1219 + //SDMA1_GFX_MIDCMD_DATA0 1220 + #define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1221 + #define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1222 + //SDMA1_GFX_MIDCMD_DATA1 1223 + #define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1224 + #define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1225 + //SDMA1_GFX_MIDCMD_DATA2 1226 + #define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1227 + #define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1228 + //SDMA1_GFX_MIDCMD_DATA3 1229 + #define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1230 + #define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1231 + //SDMA1_GFX_MIDCMD_DATA4 1232 + #define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1233 + #define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1234 + //SDMA1_GFX_MIDCMD_DATA5 1235 + #define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1236 + #define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1237 + //SDMA1_GFX_MIDCMD_DATA6 1238 + #define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1239 + #define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1240 + //SDMA1_GFX_MIDCMD_DATA7 1241 + #define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1242 + #define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1243 + //SDMA1_GFX_MIDCMD_DATA8 1244 + #define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1245 + #define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1246 + //SDMA1_GFX_MIDCMD_CNTL 1247 + #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1248 + #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1249 + #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1250 + #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1251 + #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1252 + #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1253 + #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1254 + #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1255 + //SDMA1_PAGE_RB_CNTL 1256 + #define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1257 + #define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1258 + #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1259 + #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1260 + #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1261 + #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1262 + #define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1263 + #define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1264 + #define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1265 + #define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1266 + #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1267 + #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1268 + #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1269 + #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1270 + #define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1271 + #define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1272 + //SDMA1_PAGE_RB_BASE 1273 + #define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 1274 + #define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1275 + //SDMA1_PAGE_RB_BASE_HI 1276 + #define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1277 + #define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1278 + //SDMA1_PAGE_RB_RPTR 1279 + #define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1280 + #define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1281 + //SDMA1_PAGE_RB_RPTR_HI 1282 + #define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1283 + #define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1284 + //SDMA1_PAGE_RB_WPTR 1285 + #define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1286 + #define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1287 + //SDMA1_PAGE_RB_WPTR_HI 1288 + #define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1289 + #define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1290 + //SDMA1_PAGE_RB_WPTR_POLL_CNTL 1291 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1292 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1293 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1294 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1295 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1296 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1297 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1298 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1299 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1300 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1301 + //SDMA1_PAGE_RB_RPTR_ADDR_HI 1302 + #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1303 + #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1304 + //SDMA1_PAGE_RB_RPTR_ADDR_LO 1305 + #define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1306 + #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1307 + #define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1308 + #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1309 + //SDMA1_PAGE_IB_CNTL 1310 + #define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1311 + #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1312 + #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1313 + #define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1314 + #define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1315 + #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1316 + #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1317 + #define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1318 + //SDMA1_PAGE_IB_RPTR 1319 + #define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1320 + #define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1321 + //SDMA1_PAGE_IB_OFFSET 1322 + #define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1323 + #define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1324 + //SDMA1_PAGE_IB_BASE_LO 1325 + #define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1326 + #define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1327 + //SDMA1_PAGE_IB_BASE_HI 1328 + #define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1329 + #define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1330 + //SDMA1_PAGE_IB_SIZE 1331 + #define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1332 + #define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1333 + //SDMA1_PAGE_SKIP_CNTL 1334 + #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1335 + #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1336 + //SDMA1_PAGE_CONTEXT_STATUS 1337 + #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1338 + #define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1339 + #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1340 + #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1341 + #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1342 + #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1343 + #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1344 + #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1345 + #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1346 + #define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1347 + #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1348 + #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1349 + #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1350 + #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1351 + #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1352 + #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1353 + //SDMA1_PAGE_DOORBELL 1354 + #define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1355 + #define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1356 + #define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1357 + #define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1358 + //SDMA1_PAGE_STATUS 1359 + #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1360 + #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1361 + #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1362 + #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1363 + //SDMA1_PAGE_DOORBELL_LOG 1364 + #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1365 + #define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1366 + #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1367 + #define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1368 + //SDMA1_PAGE_WATERMARK 1369 + #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1370 + #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1371 + #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1372 + #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1373 + //SDMA1_PAGE_DOORBELL_OFFSET 1374 + #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1375 + #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1376 + //SDMA1_PAGE_CSA_ADDR_LO 1377 + #define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1378 + #define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1379 + //SDMA1_PAGE_CSA_ADDR_HI 1380 + #define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1381 + #define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1382 + //SDMA1_PAGE_IB_SUB_REMAIN 1383 + #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1384 + #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1385 + //SDMA1_PAGE_PREEMPT 1386 + #define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1387 + #define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1388 + //SDMA1_PAGE_DUMMY_REG 1389 + #define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1390 + #define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1391 + //SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 1392 + #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1393 + #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1394 + //SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 1395 + #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1396 + #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1397 + //SDMA1_PAGE_RB_AQL_CNTL 1398 + #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1399 + #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1400 + #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1401 + #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1402 + #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1403 + #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1404 + //SDMA1_PAGE_MINOR_PTR_UPDATE 1405 + #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1406 + #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1407 + //SDMA1_PAGE_MIDCMD_DATA0 1408 + #define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1409 + #define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1410 + //SDMA1_PAGE_MIDCMD_DATA1 1411 + #define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1412 + #define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1413 + //SDMA1_PAGE_MIDCMD_DATA2 1414 + #define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1415 + #define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1416 + //SDMA1_PAGE_MIDCMD_DATA3 1417 + #define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1418 + #define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1419 + //SDMA1_PAGE_MIDCMD_DATA4 1420 + #define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1421 + #define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1422 + //SDMA1_PAGE_MIDCMD_DATA5 1423 + #define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1424 + #define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1425 + //SDMA1_PAGE_MIDCMD_DATA6 1426 + #define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1427 + #define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1428 + //SDMA1_PAGE_MIDCMD_DATA7 1429 + #define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1430 + #define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1431 + //SDMA1_PAGE_MIDCMD_DATA8 1432 + #define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1433 + #define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1434 + //SDMA1_PAGE_MIDCMD_CNTL 1435 + #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1436 + #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1437 + #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1438 + #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1439 + #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1440 + #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1441 + #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1442 + #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1443 + //SDMA1_RLC0_RB_CNTL 1444 + #define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1445 + #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1446 + #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1447 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1448 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1449 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1450 + #define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1451 + #define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1452 + #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1453 + #define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1454 + #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1455 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1456 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1457 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1458 + #define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1459 + #define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1460 + //SDMA1_RLC0_RB_BASE 1461 + #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 1462 + #define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1463 + //SDMA1_RLC0_RB_BASE_HI 1464 + #define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1465 + #define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1466 + //SDMA1_RLC0_RB_RPTR 1467 + #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1468 + #define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1469 + //SDMA1_RLC0_RB_RPTR_HI 1470 + #define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1471 + #define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1472 + //SDMA1_RLC0_RB_WPTR 1473 + #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1474 + #define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1475 + //SDMA1_RLC0_RB_WPTR_HI 1476 + #define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1477 + #define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1478 + //SDMA1_RLC0_RB_WPTR_POLL_CNTL 1479 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1480 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1481 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1482 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1483 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1484 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1485 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1486 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1487 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1488 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1489 + //SDMA1_RLC0_RB_RPTR_ADDR_HI 1490 + #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1491 + #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1492 + //SDMA1_RLC0_RB_RPTR_ADDR_LO 1493 + #define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1494 + #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1495 + #define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1496 + #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1497 + //SDMA1_RLC0_IB_CNTL 1498 + #define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1499 + #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1500 + #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1501 + #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1502 + #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1503 + #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1504 + #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1505 + #define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1506 + //SDMA1_RLC0_IB_RPTR 1507 + #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1508 + #define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1509 + //SDMA1_RLC0_IB_OFFSET 1510 + #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1511 + #define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1512 + //SDMA1_RLC0_IB_BASE_LO 1513 + #define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1514 + #define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1515 + //SDMA1_RLC0_IB_BASE_HI 1516 + #define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1517 + #define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1518 + //SDMA1_RLC0_IB_SIZE 1519 + #define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1520 + #define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1521 + //SDMA1_RLC0_SKIP_CNTL 1522 + #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1523 + #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1524 + //SDMA1_RLC0_CONTEXT_STATUS 1525 + #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1526 + #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1527 + #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1528 + #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1529 + #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1530 + #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1531 + #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1532 + #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1533 + #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1534 + #define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1535 + #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1536 + #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1537 + #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1538 + #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1539 + #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1540 + #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1541 + //SDMA1_RLC0_DOORBELL 1542 + #define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1543 + #define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1544 + #define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1545 + #define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1546 + //SDMA1_RLC0_STATUS 1547 + #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1548 + #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1549 + #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1550 + #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1551 + //SDMA1_RLC0_DOORBELL_LOG 1552 + #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1553 + #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1554 + #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1555 + #define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1556 + //SDMA1_RLC0_WATERMARK 1557 + #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1558 + #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1559 + #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1560 + #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1561 + //SDMA1_RLC0_DOORBELL_OFFSET 1562 + #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1563 + #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1564 + //SDMA1_RLC0_CSA_ADDR_LO 1565 + #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1566 + #define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1567 + //SDMA1_RLC0_CSA_ADDR_HI 1568 + #define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1569 + #define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1570 + //SDMA1_RLC0_IB_SUB_REMAIN 1571 + #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1572 + #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1573 + //SDMA1_RLC0_PREEMPT 1574 + #define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1575 + #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1576 + //SDMA1_RLC0_DUMMY_REG 1577 + #define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1578 + #define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1579 + //SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 1580 + #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1581 + #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1582 + //SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 1583 + #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1584 + #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1585 + //SDMA1_RLC0_RB_AQL_CNTL 1586 + #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1587 + #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1588 + #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1589 + #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1590 + #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1591 + #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1592 + //SDMA1_RLC0_MINOR_PTR_UPDATE 1593 + #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1594 + #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1595 + //SDMA1_RLC0_MIDCMD_DATA0 1596 + #define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1597 + #define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1598 + //SDMA1_RLC0_MIDCMD_DATA1 1599 + #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1600 + #define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1601 + //SDMA1_RLC0_MIDCMD_DATA2 1602 + #define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1603 + #define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1604 + //SDMA1_RLC0_MIDCMD_DATA3 1605 + #define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1606 + #define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1607 + //SDMA1_RLC0_MIDCMD_DATA4 1608 + #define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1609 + #define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1610 + //SDMA1_RLC0_MIDCMD_DATA5 1611 + #define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1612 + #define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1613 + //SDMA1_RLC0_MIDCMD_DATA6 1614 + #define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1615 + #define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1616 + //SDMA1_RLC0_MIDCMD_DATA7 1617 + #define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1618 + #define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1619 + //SDMA1_RLC0_MIDCMD_DATA8 1620 + #define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1621 + #define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1622 + //SDMA1_RLC0_MIDCMD_CNTL 1623 + #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1624 + #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1625 + #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1626 + #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1627 + #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1628 + #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1629 + #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1630 + #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1631 + //SDMA1_RLC1_RB_CNTL 1632 + #define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1633 + #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1634 + #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1635 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1636 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1637 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1638 + #define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1639 + #define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1640 + #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1641 + #define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1642 + #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1643 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1644 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1645 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1646 + #define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1647 + #define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1648 + //SDMA1_RLC1_RB_BASE 1649 + #define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 1650 + #define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1651 + //SDMA1_RLC1_RB_BASE_HI 1652 + #define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1653 + #define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1654 + //SDMA1_RLC1_RB_RPTR 1655 + #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1656 + #define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1657 + //SDMA1_RLC1_RB_RPTR_HI 1658 + #define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1659 + #define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1660 + //SDMA1_RLC1_RB_WPTR 1661 + #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1662 + #define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1663 + //SDMA1_RLC1_RB_WPTR_HI 1664 + #define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1665 + #define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1666 + //SDMA1_RLC1_RB_WPTR_POLL_CNTL 1667 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1668 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1669 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1670 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1671 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1672 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1673 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1674 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1675 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1676 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1677 + //SDMA1_RLC1_RB_RPTR_ADDR_HI 1678 + #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1679 + #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1680 + //SDMA1_RLC1_RB_RPTR_ADDR_LO 1681 + #define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1682 + #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1683 + #define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1684 + #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1685 + //SDMA1_RLC1_IB_CNTL 1686 + #define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1687 + #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1688 + #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1689 + #define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1690 + #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1691 + #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1692 + #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1693 + #define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1694 + //SDMA1_RLC1_IB_RPTR 1695 + #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1696 + #define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1697 + //SDMA1_RLC1_IB_OFFSET 1698 + #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1699 + #define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1700 + //SDMA1_RLC1_IB_BASE_LO 1701 + #define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1702 + #define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1703 + //SDMA1_RLC1_IB_BASE_HI 1704 + #define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1705 + #define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1706 + //SDMA1_RLC1_IB_SIZE 1707 + #define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1708 + #define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1709 + //SDMA1_RLC1_SKIP_CNTL 1710 + #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1711 + #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1712 + //SDMA1_RLC1_CONTEXT_STATUS 1713 + #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1714 + #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1715 + #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1716 + #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1717 + #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1718 + #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1719 + #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1720 + #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1721 + #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1722 + #define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1723 + #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1724 + #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1725 + #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1726 + #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1727 + #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1728 + #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1729 + //SDMA1_RLC1_DOORBELL 1730 + #define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1731 + #define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1732 + #define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1733 + #define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1734 + //SDMA1_RLC1_STATUS 1735 + #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1736 + #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1737 + #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1738 + #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1739 + //SDMA1_RLC1_DOORBELL_LOG 1740 + #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1741 + #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1742 + #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1743 + #define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1744 + //SDMA1_RLC1_WATERMARK 1745 + #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1746 + #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1747 + #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1748 + #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1749 + //SDMA1_RLC1_DOORBELL_OFFSET 1750 + #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1751 + #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1752 + //SDMA1_RLC1_CSA_ADDR_LO 1753 + #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1754 + #define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1755 + //SDMA1_RLC1_CSA_ADDR_HI 1756 + #define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1757 + #define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1758 + //SDMA1_RLC1_IB_SUB_REMAIN 1759 + #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1760 + #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1761 + //SDMA1_RLC1_PREEMPT 1762 + #define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1763 + #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1764 + //SDMA1_RLC1_DUMMY_REG 1765 + #define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1766 + #define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1767 + //SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 1768 + #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1769 + #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1770 + //SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 1771 + #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1772 + #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1773 + //SDMA1_RLC1_RB_AQL_CNTL 1774 + #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1775 + #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1776 + #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1777 + #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1778 + #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1779 + #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1780 + //SDMA1_RLC1_MINOR_PTR_UPDATE 1781 + #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1782 + #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1783 + //SDMA1_RLC1_MIDCMD_DATA0 1784 + #define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1785 + #define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1786 + //SDMA1_RLC1_MIDCMD_DATA1 1787 + #define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1788 + #define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1789 + //SDMA1_RLC1_MIDCMD_DATA2 1790 + #define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1791 + #define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1792 + //SDMA1_RLC1_MIDCMD_DATA3 1793 + #define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1794 + #define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1795 + //SDMA1_RLC1_MIDCMD_DATA4 1796 + #define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1797 + #define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1798 + //SDMA1_RLC1_MIDCMD_DATA5 1799 + #define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1800 + #define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1801 + //SDMA1_RLC1_MIDCMD_DATA6 1802 + #define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1803 + #define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1804 + //SDMA1_RLC1_MIDCMD_DATA7 1805 + #define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1806 + #define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1807 + //SDMA1_RLC1_MIDCMD_DATA8 1808 + #define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1809 + #define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1810 + //SDMA1_RLC1_MIDCMD_CNTL 1811 + #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1812 + #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1813 + #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1814 + #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1815 + #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1816 + #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1817 + #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1818 + #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1819 + //SDMA1_RLC2_RB_CNTL 1820 + #define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 1821 + #define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 1822 + #define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1823 + #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1824 + #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1825 + #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1826 + #define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 1827 + #define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 1828 + #define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1829 + #define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1830 + #define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1831 + #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1832 + #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1833 + #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1834 + #define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 1835 + #define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 1836 + //SDMA1_RLC2_RB_BASE 1837 + #define SDMA1_RLC2_RB_BASE__ADDR__SHIFT 0x0 1838 + #define SDMA1_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1839 + //SDMA1_RLC2_RB_BASE_HI 1840 + #define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 1841 + #define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1842 + //SDMA1_RLC2_RB_RPTR 1843 + #define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 1844 + #define SDMA1_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1845 + //SDMA1_RLC2_RB_RPTR_HI 1846 + #define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 1847 + #define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1848 + //SDMA1_RLC2_RB_WPTR 1849 + #define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 1850 + #define SDMA1_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1851 + //SDMA1_RLC2_RB_WPTR_HI 1852 + #define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 1853 + #define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1854 + //SDMA1_RLC2_RB_WPTR_POLL_CNTL 1855 + #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1856 + #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1857 + #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1858 + #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1859 + #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1860 + #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1861 + #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1862 + #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1863 + #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1864 + #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1865 + //SDMA1_RLC2_RB_RPTR_ADDR_HI 1866 + #define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1867 + #define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1868 + //SDMA1_RLC2_RB_RPTR_ADDR_LO 1869 + #define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1870 + #define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1871 + #define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1872 + #define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1873 + //SDMA1_RLC2_IB_CNTL 1874 + #define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 1875 + #define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1876 + #define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1877 + #define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 1878 + #define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1879 + #define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1880 + #define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1881 + #define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1882 + //SDMA1_RLC2_IB_RPTR 1883 + #define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 1884 + #define SDMA1_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1885 + //SDMA1_RLC2_IB_OFFSET 1886 + #define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 1887 + #define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1888 + //SDMA1_RLC2_IB_BASE_LO 1889 + #define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 1890 + #define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1891 + //SDMA1_RLC2_IB_BASE_HI 1892 + #define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 1893 + #define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1894 + //SDMA1_RLC2_IB_SIZE 1895 + #define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT 0x0 1896 + #define SDMA1_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 1897 + //SDMA1_RLC2_SKIP_CNTL 1898 + #define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1899 + #define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1900 + //SDMA1_RLC2_CONTEXT_STATUS 1901 + #define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1902 + #define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 1903 + #define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1904 + #define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1905 + #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1906 + #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1907 + #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1908 + #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1909 + #define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1910 + #define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1911 + #define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1912 + #define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1913 + #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1914 + #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1915 + #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1916 + #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1917 + //SDMA1_RLC2_DOORBELL 1918 + #define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 1919 + #define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 1920 + #define SDMA1_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 1921 + #define SDMA1_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 1922 + //SDMA1_RLC2_STATUS 1923 + #define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1924 + #define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1925 + #define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1926 + #define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1927 + //SDMA1_RLC2_DOORBELL_LOG 1928 + #define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1929 + #define SDMA1_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 1930 + #define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1931 + #define SDMA1_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1932 + //SDMA1_RLC2_WATERMARK 1933 + #define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1934 + #define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1935 + #define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1936 + #define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1937 + //SDMA1_RLC2_DOORBELL_OFFSET 1938 + #define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1939 + #define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1940 + //SDMA1_RLC2_CSA_ADDR_LO 1941 + #define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 1942 + #define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1943 + //SDMA1_RLC2_CSA_ADDR_HI 1944 + #define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 1945 + #define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1946 + //SDMA1_RLC2_IB_SUB_REMAIN 1947 + #define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1948 + #define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1949 + //SDMA1_RLC2_PREEMPT 1950 + #define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 1951 + #define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1952 + //SDMA1_RLC2_DUMMY_REG 1953 + #define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 1954 + #define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1955 + //SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 1956 + #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1957 + #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1958 + //SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 1959 + #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1960 + #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1961 + //SDMA1_RLC2_RB_AQL_CNTL 1962 + #define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1963 + #define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1964 + #define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1965 + #define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1966 + #define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1967 + #define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1968 + //SDMA1_RLC2_MINOR_PTR_UPDATE 1969 + #define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1970 + #define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1971 + //SDMA1_RLC2_MIDCMD_DATA0 1972 + #define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 1973 + #define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1974 + //SDMA1_RLC2_MIDCMD_DATA1 1975 + #define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 1976 + #define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1977 + //SDMA1_RLC2_MIDCMD_DATA2 1978 + #define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 1979 + #define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1980 + //SDMA1_RLC2_MIDCMD_DATA3 1981 + #define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 1982 + #define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1983 + //SDMA1_RLC2_MIDCMD_DATA4 1984 + #define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 1985 + #define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1986 + //SDMA1_RLC2_MIDCMD_DATA5 1987 + #define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 1988 + #define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1989 + //SDMA1_RLC2_MIDCMD_DATA6 1990 + #define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 1991 + #define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1992 + //SDMA1_RLC2_MIDCMD_DATA7 1993 + #define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 1994 + #define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1995 + //SDMA1_RLC2_MIDCMD_DATA8 1996 + #define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 1997 + #define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1998 + //SDMA1_RLC2_MIDCMD_CNTL 1999 + #define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2000 + #define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2001 + #define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2002 + #define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2003 + #define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2004 + #define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2005 + #define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2006 + #define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2007 + //SDMA1_RLC3_RB_CNTL 2008 + #define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 2009 + #define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 2010 + #define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2011 + #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2012 + #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2013 + #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2014 + #define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 2015 + #define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 2016 + #define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2017 + #define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2018 + #define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2019 + #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2020 + #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2021 + #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2022 + #define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 2023 + #define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 2024 + //SDMA1_RLC3_RB_BASE 2025 + #define SDMA1_RLC3_RB_BASE__ADDR__SHIFT 0x0 2026 + #define SDMA1_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2027 + //SDMA1_RLC3_RB_BASE_HI 2028 + #define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 2029 + #define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2030 + //SDMA1_RLC3_RB_RPTR 2031 + #define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 2032 + #define SDMA1_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2033 + //SDMA1_RLC3_RB_RPTR_HI 2034 + #define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 2035 + #define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2036 + //SDMA1_RLC3_RB_WPTR 2037 + #define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 2038 + #define SDMA1_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2039 + //SDMA1_RLC3_RB_WPTR_HI 2040 + #define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 2041 + #define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2042 + //SDMA1_RLC3_RB_WPTR_POLL_CNTL 2043 + #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2044 + #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2045 + #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2046 + #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2047 + #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2048 + #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2049 + #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2050 + #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2051 + #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2052 + #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2053 + //SDMA1_RLC3_RB_RPTR_ADDR_HI 2054 + #define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2055 + #define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2056 + //SDMA1_RLC3_RB_RPTR_ADDR_LO 2057 + #define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2058 + #define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2059 + #define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2060 + #define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2061 + //SDMA1_RLC3_IB_CNTL 2062 + #define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 2063 + #define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2064 + #define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2065 + #define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 2066 + #define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2067 + #define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2068 + #define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2069 + #define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2070 + //SDMA1_RLC3_IB_RPTR 2071 + #define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 2072 + #define SDMA1_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2073 + //SDMA1_RLC3_IB_OFFSET 2074 + #define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 2075 + #define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2076 + //SDMA1_RLC3_IB_BASE_LO 2077 + #define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 2078 + #define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2079 + //SDMA1_RLC3_IB_BASE_HI 2080 + #define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 2081 + #define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2082 + //SDMA1_RLC3_IB_SIZE 2083 + #define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT 0x0 2084 + #define SDMA1_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 2085 + //SDMA1_RLC3_SKIP_CNTL 2086 + #define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2087 + #define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2088 + //SDMA1_RLC3_CONTEXT_STATUS 2089 + #define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2090 + #define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 2091 + #define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2092 + #define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2093 + #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2094 + #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2095 + #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2096 + #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2097 + #define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2098 + #define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2099 + #define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2100 + #define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2101 + #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2102 + #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2103 + #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2104 + #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2105 + //SDMA1_RLC3_DOORBELL 2106 + #define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 2107 + #define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 2108 + #define SDMA1_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 2109 + #define SDMA1_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 2110 + //SDMA1_RLC3_STATUS 2111 + #define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2112 + #define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2113 + #define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2114 + #define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2115 + //SDMA1_RLC3_DOORBELL_LOG 2116 + #define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2117 + #define SDMA1_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 2118 + #define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2119 + #define SDMA1_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2120 + //SDMA1_RLC3_WATERMARK 2121 + #define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2122 + #define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2123 + #define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2124 + #define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2125 + //SDMA1_RLC3_DOORBELL_OFFSET 2126 + #define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2127 + #define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2128 + //SDMA1_RLC3_CSA_ADDR_LO 2129 + #define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 2130 + #define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2131 + //SDMA1_RLC3_CSA_ADDR_HI 2132 + #define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 2133 + #define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2134 + //SDMA1_RLC3_IB_SUB_REMAIN 2135 + #define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2136 + #define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2137 + //SDMA1_RLC3_PREEMPT 2138 + #define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 2139 + #define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2140 + //SDMA1_RLC3_DUMMY_REG 2141 + #define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 2142 + #define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2143 + //SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 2144 + #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2145 + #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2146 + //SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 2147 + #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2148 + #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2149 + //SDMA1_RLC3_RB_AQL_CNTL 2150 + #define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2151 + #define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2152 + #define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2153 + #define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2154 + #define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2155 + #define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2156 + //SDMA1_RLC3_MINOR_PTR_UPDATE 2157 + #define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2158 + #define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2159 + //SDMA1_RLC3_MIDCMD_DATA0 2160 + #define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 2161 + #define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2162 + //SDMA1_RLC3_MIDCMD_DATA1 2163 + #define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 2164 + #define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2165 + //SDMA1_RLC3_MIDCMD_DATA2 2166 + #define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 2167 + #define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2168 + //SDMA1_RLC3_MIDCMD_DATA3 2169 + #define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 2170 + #define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2171 + //SDMA1_RLC3_MIDCMD_DATA4 2172 + #define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 2173 + #define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2174 + //SDMA1_RLC3_MIDCMD_DATA5 2175 + #define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 2176 + #define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2177 + //SDMA1_RLC3_MIDCMD_DATA6 2178 + #define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 2179 + #define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2180 + //SDMA1_RLC3_MIDCMD_DATA7 2181 + #define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 2182 + #define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2183 + //SDMA1_RLC3_MIDCMD_DATA8 2184 + #define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 2185 + #define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2186 + //SDMA1_RLC3_MIDCMD_CNTL 2187 + #define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2188 + #define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2189 + #define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2190 + #define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2191 + #define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2192 + #define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2193 + #define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2194 + #define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2195 + //SDMA1_RLC4_RB_CNTL 2196 + #define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 2197 + #define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 2198 + #define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2199 + #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2200 + #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2201 + #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2202 + #define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 2203 + #define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 2204 + #define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2205 + #define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2206 + #define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2207 + #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2208 + #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2209 + #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2210 + #define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 2211 + #define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 2212 + //SDMA1_RLC4_RB_BASE 2213 + #define SDMA1_RLC4_RB_BASE__ADDR__SHIFT 0x0 2214 + #define SDMA1_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2215 + //SDMA1_RLC4_RB_BASE_HI 2216 + #define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 2217 + #define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2218 + //SDMA1_RLC4_RB_RPTR 2219 + #define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 2220 + #define SDMA1_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2221 + //SDMA1_RLC4_RB_RPTR_HI 2222 + #define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 2223 + #define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2224 + //SDMA1_RLC4_RB_WPTR 2225 + #define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 2226 + #define SDMA1_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2227 + //SDMA1_RLC4_RB_WPTR_HI 2228 + #define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 2229 + #define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2230 + //SDMA1_RLC4_RB_WPTR_POLL_CNTL 2231 + #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2232 + #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2233 + #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2234 + #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2235 + #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2236 + #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2237 + #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2238 + #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2239 + #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2240 + #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2241 + //SDMA1_RLC4_RB_RPTR_ADDR_HI 2242 + #define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2243 + #define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2244 + //SDMA1_RLC4_RB_RPTR_ADDR_LO 2245 + #define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2246 + #define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2247 + #define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2248 + #define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2249 + //SDMA1_RLC4_IB_CNTL 2250 + #define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 2251 + #define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2252 + #define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2253 + #define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 2254 + #define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2255 + #define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2256 + #define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2257 + #define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2258 + //SDMA1_RLC4_IB_RPTR 2259 + #define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 2260 + #define SDMA1_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2261 + //SDMA1_RLC4_IB_OFFSET 2262 + #define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 2263 + #define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2264 + //SDMA1_RLC4_IB_BASE_LO 2265 + #define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 2266 + #define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2267 + //SDMA1_RLC4_IB_BASE_HI 2268 + #define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 2269 + #define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2270 + //SDMA1_RLC4_IB_SIZE 2271 + #define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT 0x0 2272 + #define SDMA1_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 2273 + //SDMA1_RLC4_SKIP_CNTL 2274 + #define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2275 + #define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2276 + //SDMA1_RLC4_CONTEXT_STATUS 2277 + #define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2278 + #define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 2279 + #define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2280 + #define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2281 + #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2282 + #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2283 + #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2284 + #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2285 + #define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2286 + #define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2287 + #define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2288 + #define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2289 + #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2290 + #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2291 + #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2292 + #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2293 + //SDMA1_RLC4_DOORBELL 2294 + #define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 2295 + #define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 2296 + #define SDMA1_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 2297 + #define SDMA1_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 2298 + //SDMA1_RLC4_STATUS 2299 + #define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2300 + #define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2301 + #define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2302 + #define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2303 + //SDMA1_RLC4_DOORBELL_LOG 2304 + #define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2305 + #define SDMA1_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 2306 + #define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2307 + #define SDMA1_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2308 + //SDMA1_RLC4_WATERMARK 2309 + #define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2310 + #define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2311 + #define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2312 + #define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2313 + //SDMA1_RLC4_DOORBELL_OFFSET 2314 + #define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2315 + #define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2316 + //SDMA1_RLC4_CSA_ADDR_LO 2317 + #define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 2318 + #define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2319 + //SDMA1_RLC4_CSA_ADDR_HI 2320 + #define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 2321 + #define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2322 + //SDMA1_RLC4_IB_SUB_REMAIN 2323 + #define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2324 + #define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2325 + //SDMA1_RLC4_PREEMPT 2326 + #define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 2327 + #define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2328 + //SDMA1_RLC4_DUMMY_REG 2329 + #define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 2330 + #define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2331 + //SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 2332 + #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2333 + #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2334 + //SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 2335 + #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2336 + #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2337 + //SDMA1_RLC4_RB_AQL_CNTL 2338 + #define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2339 + #define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2340 + #define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2341 + #define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2342 + #define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2343 + #define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2344 + //SDMA1_RLC4_MINOR_PTR_UPDATE 2345 + #define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2346 + #define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2347 + //SDMA1_RLC4_MIDCMD_DATA0 2348 + #define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 2349 + #define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2350 + //SDMA1_RLC4_MIDCMD_DATA1 2351 + #define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 2352 + #define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2353 + //SDMA1_RLC4_MIDCMD_DATA2 2354 + #define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 2355 + #define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2356 + //SDMA1_RLC4_MIDCMD_DATA3 2357 + #define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 2358 + #define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2359 + //SDMA1_RLC4_MIDCMD_DATA4 2360 + #define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 2361 + #define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2362 + //SDMA1_RLC4_MIDCMD_DATA5 2363 + #define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 2364 + #define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2365 + //SDMA1_RLC4_MIDCMD_DATA6 2366 + #define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 2367 + #define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2368 + //SDMA1_RLC4_MIDCMD_DATA7 2369 + #define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 2370 + #define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2371 + //SDMA1_RLC4_MIDCMD_DATA8 2372 + #define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 2373 + #define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2374 + //SDMA1_RLC4_MIDCMD_CNTL 2375 + #define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2376 + #define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2377 + #define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2378 + #define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2379 + #define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2380 + #define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2381 + #define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2382 + #define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2383 + //SDMA1_RLC5_RB_CNTL 2384 + #define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 2385 + #define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 2386 + #define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2387 + #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2388 + #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2389 + #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2390 + #define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 2391 + #define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 2392 + #define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2393 + #define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2394 + #define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2395 + #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2396 + #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2397 + #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2398 + #define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 2399 + #define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 2400 + //SDMA1_RLC5_RB_BASE 2401 + #define SDMA1_RLC5_RB_BASE__ADDR__SHIFT 0x0 2402 + #define SDMA1_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2403 + //SDMA1_RLC5_RB_BASE_HI 2404 + #define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 2405 + #define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2406 + //SDMA1_RLC5_RB_RPTR 2407 + #define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 2408 + #define SDMA1_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2409 + //SDMA1_RLC5_RB_RPTR_HI 2410 + #define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 2411 + #define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2412 + //SDMA1_RLC5_RB_WPTR 2413 + #define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 2414 + #define SDMA1_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2415 + //SDMA1_RLC5_RB_WPTR_HI 2416 + #define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 2417 + #define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2418 + //SDMA1_RLC5_RB_WPTR_POLL_CNTL 2419 + #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2420 + #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2421 + #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2422 + #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2423 + #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2424 + #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2425 + #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2426 + #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2427 + #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2428 + #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2429 + //SDMA1_RLC5_RB_RPTR_ADDR_HI 2430 + #define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2431 + #define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2432 + //SDMA1_RLC5_RB_RPTR_ADDR_LO 2433 + #define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2434 + #define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2435 + #define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2436 + #define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2437 + //SDMA1_RLC5_IB_CNTL 2438 + #define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 2439 + #define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2440 + #define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2441 + #define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 2442 + #define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2443 + #define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2444 + #define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2445 + #define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2446 + //SDMA1_RLC5_IB_RPTR 2447 + #define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 2448 + #define SDMA1_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2449 + //SDMA1_RLC5_IB_OFFSET 2450 + #define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 2451 + #define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2452 + //SDMA1_RLC5_IB_BASE_LO 2453 + #define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 2454 + #define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2455 + //SDMA1_RLC5_IB_BASE_HI 2456 + #define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 2457 + #define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2458 + //SDMA1_RLC5_IB_SIZE 2459 + #define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT 0x0 2460 + #define SDMA1_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 2461 + //SDMA1_RLC5_SKIP_CNTL 2462 + #define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2463 + #define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2464 + //SDMA1_RLC5_CONTEXT_STATUS 2465 + #define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2466 + #define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 2467 + #define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2468 + #define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2469 + #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2470 + #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2471 + #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2472 + #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2473 + #define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2474 + #define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2475 + #define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2476 + #define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2477 + #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2478 + #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2479 + #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2480 + #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2481 + //SDMA1_RLC5_DOORBELL 2482 + #define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 2483 + #define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 2484 + #define SDMA1_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 2485 + #define SDMA1_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 2486 + //SDMA1_RLC5_STATUS 2487 + #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2488 + #define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2489 + #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2490 + #define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2491 + //SDMA1_RLC5_DOORBELL_LOG 2492 + #define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2493 + #define SDMA1_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 2494 + #define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2495 + #define SDMA1_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2496 + //SDMA1_RLC5_WATERMARK 2497 + #define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2498 + #define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2499 + #define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2500 + #define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2501 + //SDMA1_RLC5_DOORBELL_OFFSET 2502 + #define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2503 + #define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2504 + //SDMA1_RLC5_CSA_ADDR_LO 2505 + #define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 2506 + #define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2507 + //SDMA1_RLC5_CSA_ADDR_HI 2508 + #define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 2509 + #define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2510 + //SDMA1_RLC5_IB_SUB_REMAIN 2511 + #define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2512 + #define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2513 + //SDMA1_RLC5_PREEMPT 2514 + #define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 2515 + #define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2516 + //SDMA1_RLC5_DUMMY_REG 2517 + #define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 2518 + #define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2519 + //SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 2520 + #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2521 + #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2522 + //SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 2523 + #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2524 + #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2525 + //SDMA1_RLC5_RB_AQL_CNTL 2526 + #define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2527 + #define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2528 + #define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2529 + #define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2530 + #define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2531 + #define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2532 + //SDMA1_RLC5_MINOR_PTR_UPDATE 2533 + #define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2534 + #define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2535 + //SDMA1_RLC5_MIDCMD_DATA0 2536 + #define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 2537 + #define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2538 + //SDMA1_RLC5_MIDCMD_DATA1 2539 + #define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 2540 + #define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2541 + //SDMA1_RLC5_MIDCMD_DATA2 2542 + #define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 2543 + #define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2544 + //SDMA1_RLC5_MIDCMD_DATA3 2545 + #define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 2546 + #define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2547 + //SDMA1_RLC5_MIDCMD_DATA4 2548 + #define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 2549 + #define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2550 + //SDMA1_RLC5_MIDCMD_DATA5 2551 + #define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 2552 + #define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2553 + //SDMA1_RLC5_MIDCMD_DATA6 2554 + #define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 2555 + #define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2556 + //SDMA1_RLC5_MIDCMD_DATA7 2557 + #define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 2558 + #define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2559 + //SDMA1_RLC5_MIDCMD_DATA8 2560 + #define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 2561 + #define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2562 + //SDMA1_RLC5_MIDCMD_CNTL 2563 + #define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2564 + #define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2565 + #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2566 + #define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2567 + #define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2568 + #define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2569 + #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2570 + #define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2571 + //SDMA1_RLC6_RB_CNTL 2572 + #define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 2573 + #define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 2574 + #define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2575 + #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2576 + #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2577 + #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2578 + #define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 2579 + #define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 2580 + #define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2581 + #define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2582 + #define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2583 + #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2584 + #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2585 + #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2586 + #define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 2587 + #define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 2588 + //SDMA1_RLC6_RB_BASE 2589 + #define SDMA1_RLC6_RB_BASE__ADDR__SHIFT 0x0 2590 + #define SDMA1_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2591 + //SDMA1_RLC6_RB_BASE_HI 2592 + #define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 2593 + #define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2594 + //SDMA1_RLC6_RB_RPTR 2595 + #define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 2596 + #define SDMA1_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2597 + //SDMA1_RLC6_RB_RPTR_HI 2598 + #define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 2599 + #define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2600 + //SDMA1_RLC6_RB_WPTR 2601 + #define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 2602 + #define SDMA1_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2603 + //SDMA1_RLC6_RB_WPTR_HI 2604 + #define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 2605 + #define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2606 + //SDMA1_RLC6_RB_WPTR_POLL_CNTL 2607 + #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2608 + #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2609 + #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2610 + #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2611 + #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2612 + #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2613 + #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2614 + #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2615 + #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2616 + #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2617 + //SDMA1_RLC6_RB_RPTR_ADDR_HI 2618 + #define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2619 + #define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2620 + //SDMA1_RLC6_RB_RPTR_ADDR_LO 2621 + #define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2622 + #define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2623 + #define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2624 + #define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2625 + //SDMA1_RLC6_IB_CNTL 2626 + #define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 2627 + #define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2628 + #define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2629 + #define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 2630 + #define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2631 + #define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2632 + #define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2633 + #define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2634 + //SDMA1_RLC6_IB_RPTR 2635 + #define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 2636 + #define SDMA1_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2637 + //SDMA1_RLC6_IB_OFFSET 2638 + #define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 2639 + #define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2640 + //SDMA1_RLC6_IB_BASE_LO 2641 + #define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 2642 + #define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2643 + //SDMA1_RLC6_IB_BASE_HI 2644 + #define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 2645 + #define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2646 + //SDMA1_RLC6_IB_SIZE 2647 + #define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT 0x0 2648 + #define SDMA1_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 2649 + //SDMA1_RLC6_SKIP_CNTL 2650 + #define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2651 + #define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2652 + //SDMA1_RLC6_CONTEXT_STATUS 2653 + #define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2654 + #define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2655 + #define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2656 + #define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2657 + #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2658 + #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2659 + #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2660 + #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2661 + #define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2662 + #define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2663 + #define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2664 + #define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2665 + #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2666 + #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2667 + #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2668 + #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2669 + //SDMA1_RLC6_DOORBELL 2670 + #define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 2671 + #define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 2672 + #define SDMA1_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 2673 + #define SDMA1_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 2674 + //SDMA1_RLC6_STATUS 2675 + #define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2676 + #define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2677 + #define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2678 + #define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2679 + //SDMA1_RLC6_DOORBELL_LOG 2680 + #define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2681 + #define SDMA1_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 2682 + #define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2683 + #define SDMA1_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2684 + //SDMA1_RLC6_WATERMARK 2685 + #define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2686 + #define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2687 + #define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2688 + #define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2689 + //SDMA1_RLC6_DOORBELL_OFFSET 2690 + #define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2691 + #define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2692 + //SDMA1_RLC6_CSA_ADDR_LO 2693 + #define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 2694 + #define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2695 + //SDMA1_RLC6_CSA_ADDR_HI 2696 + #define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 2697 + #define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2698 + //SDMA1_RLC6_IB_SUB_REMAIN 2699 + #define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2700 + #define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2701 + //SDMA1_RLC6_PREEMPT 2702 + #define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 2703 + #define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2704 + //SDMA1_RLC6_DUMMY_REG 2705 + #define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 2706 + #define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2707 + //SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 2708 + #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2709 + #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2710 + //SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 2711 + #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2712 + #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2713 + //SDMA1_RLC6_RB_AQL_CNTL 2714 + #define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2715 + #define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2716 + #define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2717 + #define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2718 + #define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2719 + #define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2720 + //SDMA1_RLC6_MINOR_PTR_UPDATE 2721 + #define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2722 + #define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2723 + //SDMA1_RLC6_MIDCMD_DATA0 2724 + #define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 2725 + #define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2726 + //SDMA1_RLC6_MIDCMD_DATA1 2727 + #define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 2728 + #define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2729 + //SDMA1_RLC6_MIDCMD_DATA2 2730 + #define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 2731 + #define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2732 + //SDMA1_RLC6_MIDCMD_DATA3 2733 + #define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 2734 + #define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2735 + //SDMA1_RLC6_MIDCMD_DATA4 2736 + #define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 2737 + #define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2738 + //SDMA1_RLC6_MIDCMD_DATA5 2739 + #define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 2740 + #define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2741 + //SDMA1_RLC6_MIDCMD_DATA6 2742 + #define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 2743 + #define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2744 + //SDMA1_RLC6_MIDCMD_DATA7 2745 + #define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 2746 + #define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2747 + //SDMA1_RLC6_MIDCMD_DATA8 2748 + #define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 2749 + #define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2750 + //SDMA1_RLC6_MIDCMD_CNTL 2751 + #define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2752 + #define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2753 + #define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2754 + #define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2755 + #define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2756 + #define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2757 + #define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2758 + #define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2759 + //SDMA1_RLC7_RB_CNTL 2760 + #define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 2761 + #define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 2762 + #define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2763 + #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2764 + #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2765 + #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2766 + #define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 2767 + #define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 2768 + #define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2769 + #define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2770 + #define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2771 + #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2772 + #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2773 + #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2774 + #define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 2775 + #define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 2776 + //SDMA1_RLC7_RB_BASE 2777 + #define SDMA1_RLC7_RB_BASE__ADDR__SHIFT 0x0 2778 + #define SDMA1_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2779 + //SDMA1_RLC7_RB_BASE_HI 2780 + #define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 2781 + #define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2782 + //SDMA1_RLC7_RB_RPTR 2783 + #define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 2784 + #define SDMA1_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2785 + //SDMA1_RLC7_RB_RPTR_HI 2786 + #define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 2787 + #define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2788 + //SDMA1_RLC7_RB_WPTR 2789 + #define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 2790 + #define SDMA1_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2791 + //SDMA1_RLC7_RB_WPTR_HI 2792 + #define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 2793 + #define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2794 + //SDMA1_RLC7_RB_WPTR_POLL_CNTL 2795 + #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2796 + #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2797 + #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2798 + #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2799 + #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2800 + #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2801 + #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2802 + #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2803 + #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2804 + #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2805 + //SDMA1_RLC7_RB_RPTR_ADDR_HI 2806 + #define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2807 + #define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2808 + //SDMA1_RLC7_RB_RPTR_ADDR_LO 2809 + #define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2810 + #define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2811 + #define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2812 + #define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2813 + //SDMA1_RLC7_IB_CNTL 2814 + #define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 2815 + #define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2816 + #define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2817 + #define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 2818 + #define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2819 + #define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2820 + #define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2821 + #define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2822 + //SDMA1_RLC7_IB_RPTR 2823 + #define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 2824 + #define SDMA1_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2825 + //SDMA1_RLC7_IB_OFFSET 2826 + #define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 2827 + #define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2828 + //SDMA1_RLC7_IB_BASE_LO 2829 + #define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 2830 + #define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2831 + //SDMA1_RLC7_IB_BASE_HI 2832 + #define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 2833 + #define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2834 + //SDMA1_RLC7_IB_SIZE 2835 + #define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT 0x0 2836 + #define SDMA1_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 2837 + //SDMA1_RLC7_SKIP_CNTL 2838 + #define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2839 + #define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2840 + //SDMA1_RLC7_CONTEXT_STATUS 2841 + #define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2842 + #define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 2843 + #define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2844 + #define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2845 + #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2846 + #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2847 + #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2848 + #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2849 + #define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2850 + #define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2851 + #define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2852 + #define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2853 + #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2854 + #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2855 + #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2856 + #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2857 + //SDMA1_RLC7_DOORBELL 2858 + #define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 2859 + #define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 2860 + #define SDMA1_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 2861 + #define SDMA1_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 2862 + //SDMA1_RLC7_STATUS 2863 + #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2864 + #define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2865 + #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2866 + #define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2867 + //SDMA1_RLC7_DOORBELL_LOG 2868 + #define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2869 + #define SDMA1_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 2870 + #define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2871 + #define SDMA1_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2872 + //SDMA1_RLC7_WATERMARK 2873 + #define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2874 + #define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2875 + #define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2876 + #define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2877 + //SDMA1_RLC7_DOORBELL_OFFSET 2878 + #define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2879 + #define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2880 + //SDMA1_RLC7_CSA_ADDR_LO 2881 + #define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 2882 + #define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2883 + //SDMA1_RLC7_CSA_ADDR_HI 2884 + #define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 2885 + #define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2886 + //SDMA1_RLC7_IB_SUB_REMAIN 2887 + #define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2888 + #define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2889 + //SDMA1_RLC7_PREEMPT 2890 + #define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 2891 + #define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2892 + //SDMA1_RLC7_DUMMY_REG 2893 + #define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 2894 + #define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2895 + //SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 2896 + #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2897 + #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2898 + //SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 2899 + #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2900 + #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2901 + //SDMA1_RLC7_RB_AQL_CNTL 2902 + #define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2903 + #define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2904 + #define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2905 + #define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2906 + #define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2907 + #define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2908 + //SDMA1_RLC7_MINOR_PTR_UPDATE 2909 + #define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2910 + #define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2911 + //SDMA1_RLC7_MIDCMD_DATA0 2912 + #define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 2913 + #define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2914 + //SDMA1_RLC7_MIDCMD_DATA1 2915 + #define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 2916 + #define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2917 + //SDMA1_RLC7_MIDCMD_DATA2 2918 + #define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 2919 + #define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2920 + //SDMA1_RLC7_MIDCMD_DATA3 2921 + #define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 2922 + #define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2923 + //SDMA1_RLC7_MIDCMD_DATA4 2924 + #define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 2925 + #define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2926 + //SDMA1_RLC7_MIDCMD_DATA5 2927 + #define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 2928 + #define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2929 + //SDMA1_RLC7_MIDCMD_DATA6 2930 + #define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 2931 + #define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2932 + //SDMA1_RLC7_MIDCMD_DATA7 2933 + #define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 2934 + #define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2935 + //SDMA1_RLC7_MIDCMD_DATA8 2936 + #define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 2937 + #define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2938 + //SDMA1_RLC7_MIDCMD_CNTL 2939 + #define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2940 + #define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2941 + #define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2942 + #define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2943 + #define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2944 + #define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2945 + #define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2946 + #define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2947 + 2948 + #endif