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powerpc/fsl: Force coherent memory on e500mc derivatives

In CoreNet systems it is not allowed to mix M and non-M mappings to the
same memory, and coherent DMA accesses are considered to be M mappings
for this purpose. Ignoring this has been observed to cause hard
lockups in non-SMP kernels on e6500.

Furthermore, e6500 implements the LRAT (logical to real address table)
which allows KVM guests to control the WIMGE bits. This means that
KVM cannot force the M bit on the way it usually does, so the guest had
better set it itself.

Signed-off-by: Scott Wood <scottwood@freescale.com>

Scott Wood c6023202 0d61f0b3

+20 -13
+2 -1
arch/powerpc/include/asm/pte-common.h
··· 109 109 * the processor might need it for DMA coherency. 110 110 */ 111 111 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) 112 - #if defined(CONFIG_SMP) || defined(CONFIG_PPC_STD_MMU) 112 + #if defined(CONFIG_SMP) || defined(CONFIG_PPC_STD_MMU) || \ 113 + defined(CONFIG_PPC_E500MC) 113 114 #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT) 114 115 #else 115 116 #define _PAGE_BASE (_PAGE_BASE_NC)
+8 -5
arch/powerpc/kernel/exceptions-64e.S
··· 1313 1313 sync 1314 1314 isync 1315 1315 1316 - /* The mapping only needs to be cache-coherent on SMP */ 1317 - #ifdef CONFIG_SMP 1318 - #define M_IF_SMP MAS2_M 1316 + /* 1317 + * The mapping only needs to be cache-coherent on SMP, except on 1318 + * Freescale e500mc derivatives where it's also needed for coherent DMA. 1319 + */ 1320 + #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC) 1321 + #define M_IF_NEEDED MAS2_M 1319 1322 #else 1320 - #define M_IF_SMP 0 1323 + #define M_IF_NEEDED 0 1321 1324 #endif 1322 1325 1323 1326 /* 6. Setup KERNELBASE mapping in TLB[0] ··· 1335 1332 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l 1336 1333 mtspr SPRN_MAS1,r6 1337 1334 1338 - LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP) 1335 + LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_NEEDED) 1339 1336 mtspr SPRN_MAS2,r6 1340 1337 1341 1338 rlwinm r5,r5,0,0,25
+9 -6
arch/powerpc/kernel/fsl_booke_entry_mapping.S
··· 152 152 tlbivax 0,r9 153 153 TLBSYNC 154 154 155 - /* The mapping only needs to be cache-coherent on SMP */ 156 - #ifdef CONFIG_SMP 157 - #define M_IF_SMP MAS2_M 155 + /* 156 + * The mapping only needs to be cache-coherent on SMP, except on 157 + * Freescale e500mc derivatives where it's also needed for coherent DMA. 158 + */ 159 + #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC) 160 + #define M_IF_NEEDED MAS2_M 158 161 #else 159 - #define M_IF_SMP 0 162 + #define M_IF_NEEDED 0 160 163 #endif 161 164 162 165 #if defined(ENTRY_MAPPING_BOOT_SETUP) ··· 170 167 lis r6,(MAS1_VALID|MAS1_IPROT)@h 171 168 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l 172 169 mtspr SPRN_MAS1,r6 173 - lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h 174 - ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l 170 + lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@h 171 + ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@l 175 172 mtspr SPRN_MAS2,r6 176 173 mtspr SPRN_MAS3,r8 177 174 tlbwe
+1 -1
arch/powerpc/mm/fsl_booke_mmu.c
··· 112 112 113 113 tsize = __ilog2(size) - 10; 114 114 115 - #ifdef CONFIG_SMP 115 + #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC) 116 116 if ((flags & _PAGE_NO_CACHE) == 0) 117 117 flags |= _PAGE_COHERENT; 118 118 #endif