tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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sh: sh7724: INTC setting update

This patch follows Rev 0.50 manual

Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

authored by

Kuninori Morimoto and committed by
Paul Mundt c5eeff1f 46e9371c

+82 -89
+82 -89
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
··· 511 511 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 512 512 HUDI, 513 513 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3, 514 - _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK, 514 + _2DG_TRI, _2DG_INI, _2DG_CEI, 515 515 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3, 516 - VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI, 517 - SCIFA_SCIFA0, 518 - VPU_VPUI, 519 - TPU_TPUI, 520 - CEU21I, 521 - BEU21I, 522 - USB_USI0, 516 + VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU, 517 + SCIFA3, 518 + VPU, 519 + TPU, 520 + CEU1, 521 + BEU1, 522 + USB0, USB1, 523 523 ATAPI, 524 524 RTC_ATI, RTC_PRI, RTC_CUI, 525 525 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR, 526 526 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR, 527 - KEYSC_KEYI, 527 + KEYSC, 528 528 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2, 529 - VEU3F0I, 529 + VEU0, 530 530 MSIOF_MSIOFI0, MSIOF_MSIOFI1, 531 531 SPU_SPUI0, SPU_SPUI1, 532 - SCIFA_SCIFA1, 533 - /* ICB_ICBI, */ 532 + SCIFA4, 533 + ICB, 534 534 ETHI, 535 535 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 536 536 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 537 - SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, 538 - CMT_CMTI, 539 - TSIF_TSIFI, 540 - /* ICB_LMBI, */ 541 - FSI_FSI, 542 - SCIFA_SCIFA2, 537 + SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3, 538 + CMT, 539 + TSIF, 540 + FSI, 541 + SCIFA5, 543 542 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 544 - IRDA_IRDAI, 543 + IRDA, 545 544 SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2, 546 - JPU_JPUI, 547 - MMC_MMCI0, MMC_MMCI1, MMC_MMCI2, 548 - LCDC_LCDCI, 545 + JPU, 546 + _2DDMAC, 547 + MMC_MMC2I, MMC_MMC3I, 548 + LCDC, 549 549 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 550 550 551 551 /* interrupt groups */ 552 - DMAC1A, _2DG, DMAC0A, VIO, RTC, 553 - DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMC, 552 + DMAC1A, _2DG, DMAC0A, VIO, USB, RTC, 553 + DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF, 554 554 }; 555 555 556 556 static struct intc_vect vectors[] __initdata = { ··· 567 567 INTC_VECT(_2DG_TRI, 0x780), 568 568 INTC_VECT(_2DG_INI, 0x7A0), 569 569 INTC_VECT(_2DG_CEI, 0x7C0), 570 - INTC_VECT(_2DG_BRK, 0x7E0), 571 570 572 571 INTC_VECT(DMAC0A_DEI0, 0x800), 573 572 INTC_VECT(DMAC0A_DEI1, 0x820), 574 573 INTC_VECT(DMAC0A_DEI2, 0x840), 575 574 INTC_VECT(DMAC0A_DEI3, 0x860), 576 575 577 - INTC_VECT(VIO_CEU20I, 0x880), 578 - INTC_VECT(VIO_BEU20I, 0x8A0), 579 - INTC_VECT(VIO_VEU3F1, 0x8C0), 580 - INTC_VECT(VIO_VOUI, 0x8E0), 576 + INTC_VECT(VIO_CEU0, 0x880), 577 + INTC_VECT(VIO_BEU0, 0x8A0), 578 + INTC_VECT(VIO_VEU1, 0x8C0), 579 + INTC_VECT(VIO_VOU, 0x8E0), 581 580 582 - INTC_VECT(SCIFA_SCIFA0, 0x900), 583 - INTC_VECT(VPU_VPUI, 0x980), 584 - INTC_VECT(TPU_TPUI, 0x9A0), 585 - INTC_VECT(CEU21I, 0x9E0), 586 - INTC_VECT(BEU21I, 0xA00), 587 - INTC_VECT(USB_USI0, 0xA20), 588 - INTC_VECT(ATAPI, 0xA60), 581 + INTC_VECT(SCIFA3, 0x900), 582 + INTC_VECT(VPU, 0x980), 583 + INTC_VECT(TPU, 0x9A0), 584 + INTC_VECT(CEU1, 0x9E0), 585 + INTC_VECT(BEU1, 0xA00), 586 + INTC_VECT(USB0, 0xA20), 587 + INTC_VECT(USB1, 0xA40), 588 + INTC_VECT(ATAPI, 0xA60), 589 589 590 590 INTC_VECT(RTC_ATI, 0xA80), 591 591 INTC_VECT(RTC_PRI, 0xAA0), ··· 599 599 INTC_VECT(DMAC0B_DEI5, 0xBA0), 600 600 INTC_VECT(DMAC0B_DADERR, 0xBC0), 601 601 602 - INTC_VECT(KEYSC_KEYI, 0xBE0), 602 + INTC_VECT(KEYSC, 0xBE0), 603 603 INTC_VECT(SCIF_SCIF0, 0xC00), 604 604 INTC_VECT(SCIF_SCIF1, 0xC20), 605 605 INTC_VECT(SCIF_SCIF2, 0xC40), 606 - INTC_VECT(VEU3F0I, 0xC60), 606 + INTC_VECT(VEU0, 0xC60), 607 607 INTC_VECT(MSIOF_MSIOFI0, 0xC80), 608 608 INTC_VECT(MSIOF_MSIOFI1, 0xCA0), 609 609 INTC_VECT(SPU_SPUI0, 0xCC0), 610 610 INTC_VECT(SPU_SPUI1, 0xCE0), 611 - INTC_VECT(SCIFA_SCIFA1, 0xD00), 611 + INTC_VECT(SCIFA4, 0xD00), 612 612 613 - /* INTC_VECT(ICB_ICBI, 0xD20), */ 613 + INTC_VECT(ICB, 0xD20), 614 614 INTC_VECT(ETHI, 0xD60), 615 615 616 616 INTC_VECT(I2C1_ALI, 0xD80), ··· 626 626 INTC_VECT(SDHI0_SDHII0, 0xE80), 627 627 INTC_VECT(SDHI0_SDHII1, 0xEA0), 628 628 INTC_VECT(SDHI0_SDHII2, 0xEC0), 629 + INTC_VECT(SDHI0_SDHII3, 0xEE0), 629 630 630 - INTC_VECT(CMT_CMTI, 0xF00), 631 - INTC_VECT(TSIF_TSIFI, 0xF20), 632 - /* INTC_VECT(ICB_LMBI, 0xF60), */ 633 - INTC_VECT(FSI_FSI, 0xF80), 634 - INTC_VECT(SCIFA_SCIFA2, 0xFA0), 631 + INTC_VECT(CMT, 0xF00), 632 + INTC_VECT(TSIF, 0xF20), 633 + INTC_VECT(FSI, 0xF80), 634 + INTC_VECT(SCIFA5, 0xFA0), 635 635 636 636 INTC_VECT(TMU0_TUNI0, 0x400), 637 637 INTC_VECT(TMU0_TUNI1, 0x420), 638 638 INTC_VECT(TMU0_TUNI2, 0x440), 639 639 640 - INTC_VECT(IRDA_IRDAI, 0x480), 640 + INTC_VECT(IRDA, 0x480), 641 641 642 642 INTC_VECT(SDHI1_SDHII0, 0x4E0), 643 643 INTC_VECT(SDHI1_SDHII1, 0x500), 644 644 INTC_VECT(SDHI1_SDHII2, 0x520), 645 645 646 - INTC_VECT(JPU_JPUI, 0x560), 646 + INTC_VECT(JPU, 0x560), 647 + INTC_VECT(_2DDMAC, 0x4A0), 647 648 648 - INTC_VECT(MMC_MMCI0, 0x580), 649 - INTC_VECT(MMC_MMCI1, 0x5A0), 650 - INTC_VECT(MMC_MMCI2, 0x5C0), 649 + INTC_VECT(MMC_MMC2I, 0x5A0), 650 + INTC_VECT(MMC_MMC3I, 0x5C0), 651 651 652 - INTC_VECT(LCDC_LCDCI, 0xF40), 652 + INTC_VECT(LCDC, 0xF40), 653 653 654 654 INTC_VECT(TMU1_TUNI0, 0x920), 655 655 INTC_VECT(TMU1_TUNI1, 0x940), ··· 658 658 659 659 static struct intc_group groups[] __initdata = { 660 660 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3), 661 - INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK), 661 + INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI), 662 662 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3), 663 - INTC_GROUP(VIO, VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI), 663 + INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU), 664 + INTC_GROUP(USB, USB0, USB1), 664 665 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 665 666 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR), 666 667 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), 667 668 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 668 669 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 669 - INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2), 670 + INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3), 670 671 INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2), 671 672 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), 672 - INTC_GROUP(MMC, MMC_MMCI0, MMC_MMCI1, MMC_MMCI2), 673 + INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I), 673 674 }; 674 675 675 - /* FIXMEEEEEEEEEEEEEEEEEEE !!!!! */ 676 - /* very bad manual !! */ 677 676 static struct intc_mask_reg mask_registers[] __initdata = { 678 677 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 679 678 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 680 - /*SDHII3?*/0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } }, 679 + 0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } }, 681 680 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 682 - { VIO_VOUI, VIO_VEU3F1, VIO_BEU20I, VIO_CEU20I, 681 + { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, 683 682 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, 684 683 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 685 - { 0, 0, 0, VPU_VPUI, ATAPI, ETHI, 0, /*SCIFA3*/SCIFA_SCIFA0 } }, 684 + { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } }, 686 685 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 687 686 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0, 688 - SPU_SPUI1, SPU_SPUI0, BEU21I, IRDA_IRDAI } }, 687 + SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } }, 689 688 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 690 689 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0, 691 - JPU_JPUI, 0, 0, LCDC_LCDCI } }, 690 + JPU, 0, 0, LCDC } }, 692 691 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 693 - { KEYSC_KEYI, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4, 694 - VEU3F0I, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } }, 692 + { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4, 693 + VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } }, 695 694 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 696 - { 0, 0, /*ICB_ICBI*/0, /*SCIFA4*/SCIFA_SCIFA1, 697 - CEU21I, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } }, 695 + { 0, 0, ICB, SCIFA4, 696 + CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } }, 698 697 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 699 698 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 700 699 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, 701 700 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 702 - { /*SDHII3*/0, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0, 703 - 0, 0, /*SCIFA5*/SCIFA_SCIFA2, FSI_FSI } }, 701 + { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0, 702 + 0, 0, SCIFA5, FSI } }, 704 703 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 705 - { 0, 0, 0, CMT_CMTI, 0, /*USB1*/0, USB_USI0, 0 } }, 704 + { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, 706 705 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 707 706 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4, 708 - 0, RTC_ATI, RTC_PRI, RTC_CUI } }, 707 + 0, RTC_CUI, RTC_PRI, RTC_ATI } }, 709 708 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 710 - { _2DG_BRK, _2DG_CEI, _2DG_INI, _2DG_TRI, 711 - 0, TPU_TPUI, /*ICB_LMBI*/0, TSIF_TSIFI } }, 709 + { 0, _2DG_CEI, _2DG_INI, _2DG_TRI, 710 + 0, TPU, 0, TSIF } }, 712 711 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 713 - { 0, 0, 0, 0, 0, 0, 0, 0/*2DDMAC*/ } }, 712 + { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } }, 714 713 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 715 714 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 716 715 }; 717 716 718 717 static struct intc_prio_reg prio_registers[] __initdata = { 719 718 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, 720 - TMU0_TUNI2, IRDA_IRDAI } }, 721 - { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU_JPUI, LCDC_LCDCI, 722 - DMAC1A, BEU21I } }, 719 + TMU0_TUNI2, IRDA } }, 720 + { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } }, 723 721 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, 724 722 TMU1_TUNI2, SPU } }, 725 - { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMC, 0, ATAPI } }, 726 - { 0xa4080010, 0, 16, 4, /* IPRE */ 727 - { DMAC0A, /*BEU?VEU?*/VIO, /*SCIFA3*/SCIFA_SCIFA0, /*VPU5F*/ 728 - VPU_VPUI } }, 729 - { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, 730 - USB_USI0, CMT_CMTI } }, 723 + { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } }, 724 + { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } }, 725 + { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } }, 731 726 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, 732 - SCIF_SCIF2, VEU3F0I } }, 727 + SCIF_SCIF2, VEU0 } }, 733 728 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1, 734 729 I2C1, I2C0 } }, 735 - { 0xa4080020, 0, 16, 4, /* IPRI */ { /*SCIFA4*/SCIFA_SCIFA1, /*ICB*/0, 736 - TSIF_TSIFI, _2DG/*ICB?*/ } }, 737 - { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU21I, ETHI, FSI_FSI, SDHI1 } }, 738 - { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, /*ICB?*/0, SDHI0 } }, 739 - { 0xa408002c, 0, 16, 4, /* IPRL */ { /*SCIFA5*/SCIFA_SCIFA2, 0, 740 - TPU_TPUI, /*2DDMAC*/0 } }, 730 + { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } }, 731 + { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } }, 732 + { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } }, 733 + { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } }, 741 734 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 742 735 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 743 736 };