drm/i915/lnl+/tc: Use the cached max lane count value

Use the cached max lane count value on LNL+, to account for scenarios
where this value is queried after the HW cleared the corresponding pin
assignment value in the TCSS_DDI_STATUS register after the sink got
disconnected.

For consistency, follow-up changes will use the cached max lane count
value on other platforms as well and will also cache the pin assignment
value in a similar way.

Cc: [e-mail] # v6.8+
Reported-by: Charlton Lin <[e-mail]>
Tested-by: Khaled Almahallawy <[e-mail]>
Reviewed-by: Mika Kahola <[e-mail]>
Signed-off-by: Imre Deak <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]
(cherry picked from commit afc4e84388079f4d5ba05271632b7a4d8d85165c)
Signed-off-by: Tvrtko Ursulin <[e-mail]>

drivers/gpu/drm/i915/display/intel_tc.c

···
 
 int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
 {
+	struct intel_display *display = to_intel_display(dig_port);
 	struct intel_tc_port *tc = to_tc_port(dig_port);
 
 	if (!intel_encoder_is_tc(&dig_port->base))
 		return 4;
 
-	return get_max_lane_count(tc);
+	if (DISPLAY_VER(display) < 20)
+		return get_max_lane_count(tc);
+
+	return tc->max_lane_count;
 }
 
 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,