dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate

Add two properties of ref_clk and coefficient used by U2 slew rate
calibrate which may vary on different SoCs

Signed-off-by: Chunfeng Yun <[e-mail]>
Reviewed-by: Matthias Brugger <[e-mail]>
Signed-off-by: Kishon Vijay Abraham I <[e-mail]>

Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt

···
  - reg		: offset and length of register shared by multiple ports,
 		  exclude port's private register. It is needed on mt2701
 		  and mt8173, but not on mt2712.
+ - mediatek,src-ref-clk-mhz	: frequency of reference clock for slew rate
+		  calibrate
+ - mediatek,src-coef	: coefficient for slew rate calibrate, depends on
+		  SoC process
 
 Required properties (port (child) node):
 - reg		: address and length of the register set for the port.