···168168{169169 struct fapll_data *fd = to_fapll(hw);170170 u32 fapll_n, fapll_p, v;171171- long long rate;171171+ u64 rate;172172173173 if (ti_fapll_clock_is_bypass(fd))174174 return parent_rate;···314314{315315 struct fapll_synth *synth = to_synth(hw);316316 u32 synth_div_m;317317- long long rate;317317+ u64 rate;318318319319 /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */320320 if (!synth->div)