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dt-bindings: reset: imx7: Document usage on i.MX8MP SoC
The driver now supports i.MX8MP, so update bindings accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
authored by
Anson Huang
and committed by
Philipp Zabel
c4e181d6
ecd910f4
+53
-1
+3
-1
Documentation/devicetree/bindings/reset/fsl,imx7-src.txt
+3
-1
Documentation/devicetree/bindings/reset/fsl,imx7-src.txt
···
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- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"
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- For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"
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- For i.MX8MN SoCs should be "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"
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- For i.MX8MP SoCs should be "fsl,imx8mp-src", "syscon"
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- reg: should be register base and length as documented in the
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datasheet
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- interrupts: Should contain SRC interrupt
···
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<dt-bindings/reset/imx7-reset.h> for i.MX7,
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM and
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MN
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MN and
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<dt-bindings/reset/imx8mp-reset.h> for i.MX8MP
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include/dt-bindings/reset/imx8mp-reset.h
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include/dt-bindings/reset/imx8mp-reset.h
···
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2020 NXP
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*/
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#ifndef DT_BINDING_RESET_IMX8MP_H
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#define DT_BINDING_RESET_IMX8MP_H
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#define IMX8MP_RESET_A53_CORE_POR_RESET0 0
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#define IMX8MP_RESET_A53_CORE_POR_RESET1 1
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#define IMX8MP_RESET_A53_CORE_POR_RESET2 2
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#define IMX8MP_RESET_A53_CORE_POR_RESET3 3
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#define IMX8MP_RESET_A53_CORE_RESET0 4
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#define IMX8MP_RESET_A53_CORE_RESET1 5
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#define IMX8MP_RESET_A53_CORE_RESET2 6
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#define IMX8MP_RESET_A53_CORE_RESET3 7
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#define IMX8MP_RESET_A53_DBG_RESET0 8
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#define IMX8MP_RESET_A53_DBG_RESET1 9
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#define IMX8MP_RESET_A53_DBG_RESET2 10
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#define IMX8MP_RESET_A53_DBG_RESET3 11
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#define IMX8MP_RESET_A53_ETM_RESET0 12
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#define IMX8MP_RESET_A53_ETM_RESET1 13
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#define IMX8MP_RESET_A53_ETM_RESET2 14
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#define IMX8MP_RESET_A53_ETM_RESET3 15
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#define IMX8MP_RESET_A53_SOC_DBG_RESET 16
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#define IMX8MP_RESET_A53_L2RESET 17
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#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18
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#define IMX8MP_RESET_OTG1_PHY_RESET 19
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#define IMX8MP_RESET_OTG2_PHY_RESET 20
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#define IMX8MP_RESET_SUPERMIX_RESET 21
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#define IMX8MP_RESET_AUDIOMIX_RESET 22
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#define IMX8MP_RESET_MLMIX_RESET 23
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#define IMX8MP_RESET_PCIEPHY 24
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#define IMX8MP_RESET_PCIEPHY_PERST 25
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#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26
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#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27
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#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28
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#define IMX8MP_RESET_MEDIA_RESET 29
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#define IMX8MP_RESET_GPU2D_RESET 30
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#define IMX8MP_RESET_GPU3D_RESET 31
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#define IMX8MP_RESET_GPU_RESET 32
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#define IMX8MP_RESET_VPU_RESET 33
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#define IMX8MP_RESET_VPU_G1_RESET 34
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#define IMX8MP_RESET_VPU_G2_RESET 35
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#define IMX8MP_RESET_VPUVC8KE_RESET 36
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#define IMX8MP_RESET_NOC_RESET 37
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#define IMX8MP_RESET_NUM 38
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#endif