drm/amdgpu: add hdp v5_2_1 ip headers · tjh.dev/kernel@c4d1c90

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

drm/amdgpu: add hdp v5_2_1 ip headers

Add hdp v5.2.1 offset and shift mask ip header files.

v2: squash in updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Huang Rui and committed by

Alex Deucher 3 years ago c4d1c905 0c1e5527

+901

2 changed files

expand all

drivers

gpu

drm

amd

include

asic_reg

hdp

hdp_5_2_1_offset.h

hdp_5_2_1_sh_mask.h

+217

drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_2_1_offset.h

+684

drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_2_1_sh_mask.h

··· 1 + /* 2 + * Copyright 2021 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + #ifndef _hdp_5_2_1_SH_MASK_HEADER 24 + #define _hdp_5_2_1_SH_MASK_HEADER 25 + 26 + 27 + // addressBlock: hdp_hdpdec 28 + //HDP_MMHUB_TLVL 29 + #define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0 30 + #define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4 31 + #define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8 32 + #define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc 33 + #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10 34 + #define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x0000000FL 35 + #define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x000000F0L 36 + #define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000F00L 37 + #define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x0000F000L 38 + #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x000F0000L 39 + //HDP_MMHUB_UNITID 40 + #define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0 41 + #define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8 42 + #define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10 43 + #define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL 44 + #define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L 45 + #define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L 46 + //HDP_NONSURFACE_BASE 47 + #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0 48 + #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL 49 + //HDP_NONSURFACE_INFO 50 + #define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4 51 + #define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8 52 + #define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L 53 + #define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L 54 + //HDP_NONSURFACE_BASE_HI 55 + #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0 56 + #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL 57 + //HDP_SURFACE_WRITE_FLAGS 58 + #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT 0x0 59 + #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT 0x1 60 + #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK 0x00000001L 61 + #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK 0x00000002L 62 + //HDP_SURFACE_READ_FLAGS 63 + #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT 0x0 64 + #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT 0x1 65 + #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK 0x00000001L 66 + #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK 0x00000002L 67 + //HDP_SURFACE_WRITE_FLAGS_CLR 68 + #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT 0x0 69 + #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT 0x1 70 + #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK 0x00000001L 71 + #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK 0x00000002L 72 + //HDP_SURFACE_READ_FLAGS_CLR 73 + #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT 0x0 74 + #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT 0x1 75 + #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK 0x00000001L 76 + #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK 0x00000002L 77 + //HDP_NONSURF_FLAGS 78 + #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 79 + #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 80 + #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L 81 + #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L 82 + //HDP_NONSURF_FLAGS_CLR 83 + #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 84 + #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 85 + #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L 86 + #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L 87 + //HDP_HOST_PATH_CNTL 88 + #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 89 + #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb 90 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12 91 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 92 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 93 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16 94 + #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d 95 + #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L 96 + #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L 97 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L 98 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L 99 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L 100 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L 101 + #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L 102 + //HDP_SW_SEMAPHORE 103 + #define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 104 + #define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL 105 + //HDP_DEBUG0 106 + #define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 107 + #define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL 108 + //HDP_LAST_SURFACE_HIT 109 + #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 110 + #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L 111 + //HDP_OUTSTANDING_REQ 112 + #define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 113 + #define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 114 + #define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL 115 + #define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L 116 + //HDP_MISC_CNTL 117 + #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2 118 + #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 119 + #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT 0x8 120 + #define HDP_MISC_CNTL__EARLY_WRACK_MISSING_PROTECT_ENABLE__SHIFT 0x9 121 + #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb 122 + #define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe 123 + #define HDP_MISC_CNTL__NACK_ENABLE__SHIFT 0x13 124 + #define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT 0x14 125 + #define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 126 + #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT 0x16 127 + #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17 128 + #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18 129 + #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e 130 + #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL 131 + #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L 132 + #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK 0x00000100L 133 + #define HDP_MISC_CNTL__EARLY_WRACK_MISSING_PROTECT_ENABLE_MASK 0x00000200L 134 + #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L 135 + #define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK 0x0000C000L 136 + #define HDP_MISC_CNTL__NACK_ENABLE_MASK 0x00080000L 137 + #define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE_MASK 0x00100000L 138 + #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L 139 + #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK 0x00400000L 140 + #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L 141 + #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L 142 + #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L 143 + //HDP_MEM_POWER_CTRL 144 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN__SHIFT 0x0 145 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN__SHIFT 0x1 146 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN__SHIFT 0x2 147 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN__SHIFT 0x3 148 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS__SHIFT 0x4 149 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 150 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe 151 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT 0x10 152 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT 0x11 153 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT 0x12 154 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT 0x13 155 + #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14 156 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18 157 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0x1e 158 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN_MASK 0x00000001L 159 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK 0x00000002L 160 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK 0x00000004L 161 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK 0x00000008L 162 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS_MASK 0x00000070L 163 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L 164 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L 165 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 166 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 167 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK 0x00040000L 168 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK 0x00080000L 169 + #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK 0x00700000L 170 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L 171 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY_MASK 0xC0000000L 172 + //HDP_MMHUB_CNTL 173 + #define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0 174 + #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1 175 + #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2 176 + #define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L 177 + #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L 178 + #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L 179 + //HDP_VERSION 180 + #define HDP_VERSION__MINVER__SHIFT 0x0 181 + #define HDP_VERSION__MAJVER__SHIFT 0x8 182 + #define HDP_VERSION__REV__SHIFT 0x10 183 + #define HDP_VERSION__MINVER_MASK 0x000000FFL 184 + #define HDP_VERSION__MAJVER_MASK 0x0000FF00L 185 + #define HDP_VERSION__REV_MASK 0x00FF0000L 186 + //HDP_CLK_CNTL 187 + #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0 188 + #define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a 189 + #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1b 190 + #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c 191 + #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d 192 + #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e 193 + #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f 194 + #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL 195 + #define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L 196 + #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK 0x08000000L 197 + #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L 198 + #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L 199 + #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L 200 + #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L 201 + //HDP_MEMIO_CNTL 202 + #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 203 + #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 204 + #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 205 + #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 206 + #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 207 + #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 208 + #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe 209 + #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf 210 + #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 211 + #define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 212 + #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L 213 + #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L 214 + #define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL 215 + #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L 216 + #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L 217 + #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L 218 + #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L 219 + #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L 220 + #define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L 221 + #define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L 222 + //HDP_MEMIO_ADDR 223 + #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 224 + #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL 225 + //HDP_MEMIO_STATUS 226 + #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 227 + #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 228 + #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 229 + #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 230 + #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L 231 + #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L 232 + #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L 233 + #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L 234 + //HDP_MEMIO_WR_DATA 235 + #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 236 + #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL 237 + //HDP_MEMIO_RD_DATA 238 + #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 239 + #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL 240 + //HDP_XDP_DIRECT2HDP_FIRST 241 + #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 242 + #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL 243 + //HDP_XDP_D2H_FLUSH 244 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 245 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 246 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 247 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb 248 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 249 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 250 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 251 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 252 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL 253 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L 254 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L 255 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L 256 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L 257 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L 258 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L 259 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L 260 + //HDP_XDP_D2H_BAR_UPDATE 261 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 262 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 263 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 264 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL 265 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L 266 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L 267 + //HDP_XDP_D2H_RSVD_3 268 + #define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 269 + #define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL 270 + //HDP_XDP_D2H_RSVD_4 271 + #define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 272 + #define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL 273 + //HDP_XDP_D2H_RSVD_5 274 + #define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 275 + #define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL 276 + //HDP_XDP_D2H_RSVD_6 277 + #define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 278 + #define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL 279 + //HDP_XDP_D2H_RSVD_7 280 + #define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 281 + #define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL 282 + //HDP_XDP_D2H_RSVD_8 283 + #define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 284 + #define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL 285 + //HDP_XDP_D2H_RSVD_9 286 + #define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 287 + #define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL 288 + //HDP_XDP_D2H_RSVD_10 289 + #define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 290 + #define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL 291 + //HDP_XDP_D2H_RSVD_11 292 + #define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 293 + #define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL 294 + //HDP_XDP_D2H_RSVD_12 295 + #define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 296 + #define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL 297 + //HDP_XDP_D2H_RSVD_13 298 + #define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 299 + #define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL 300 + //HDP_XDP_D2H_RSVD_14 301 + #define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 302 + #define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL 303 + //HDP_XDP_D2H_RSVD_15 304 + #define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 305 + #define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL 306 + //HDP_XDP_D2H_RSVD_16 307 + #define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 308 + #define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL 309 + //HDP_XDP_D2H_RSVD_17 310 + #define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 311 + #define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL 312 + //HDP_XDP_D2H_RSVD_18 313 + #define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 314 + #define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL 315 + //HDP_XDP_D2H_RSVD_19 316 + #define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 317 + #define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL 318 + //HDP_XDP_D2H_RSVD_20 319 + #define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 320 + #define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL 321 + //HDP_XDP_D2H_RSVD_21 322 + #define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 323 + #define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL 324 + //HDP_XDP_D2H_RSVD_22 325 + #define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 326 + #define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL 327 + //HDP_XDP_D2H_RSVD_23 328 + #define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 329 + #define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL 330 + //HDP_XDP_D2H_RSVD_24 331 + #define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 332 + #define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL 333 + //HDP_XDP_D2H_RSVD_25 334 + #define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 335 + #define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL 336 + //HDP_XDP_D2H_RSVD_26 337 + #define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 338 + #define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL 339 + //HDP_XDP_D2H_RSVD_27 340 + #define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 341 + #define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL 342 + //HDP_XDP_D2H_RSVD_28 343 + #define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 344 + #define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL 345 + //HDP_XDP_D2H_RSVD_29 346 + #define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 347 + #define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL 348 + //HDP_XDP_D2H_RSVD_30 349 + #define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 350 + #define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL 351 + //HDP_XDP_D2H_RSVD_31 352 + #define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 353 + #define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL 354 + //HDP_XDP_D2H_RSVD_32 355 + #define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 356 + #define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL 357 + //HDP_XDP_D2H_RSVD_33 358 + #define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 359 + #define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL 360 + //HDP_XDP_D2H_RSVD_34 361 + #define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 362 + #define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL 363 + //HDP_XDP_DIRECT2HDP_LAST 364 + #define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 365 + #define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL 366 + //HDP_XDP_P2P_BAR_CFG 367 + #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 368 + #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 369 + #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL 370 + #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L 371 + //HDP_XDP_P2P_MBX_OFFSET 372 + #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 373 + #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL 374 + //HDP_XDP_P2P_MBX_ADDR0 375 + #define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 376 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3 377 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14 378 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18 379 + #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L 380 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L 381 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L 382 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L 383 + //HDP_XDP_P2P_MBX_ADDR1 384 + #define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 385 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3 386 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14 387 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18 388 + #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L 389 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L 390 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L 391 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L 392 + //HDP_XDP_P2P_MBX_ADDR2 393 + #define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 394 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3 395 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14 396 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18 397 + #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L 398 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L 399 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L 400 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L 401 + //HDP_XDP_P2P_MBX_ADDR3 402 + #define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 403 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3 404 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14 405 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18 406 + #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L 407 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L 408 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L 409 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L 410 + //HDP_XDP_P2P_MBX_ADDR4 411 + #define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 412 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3 413 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14 414 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18 415 + #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L 416 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L 417 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L 418 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L 419 + //HDP_XDP_P2P_MBX_ADDR5 420 + #define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 421 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3 422 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14 423 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18 424 + #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L 425 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L 426 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L 427 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L 428 + //HDP_XDP_P2P_MBX_ADDR6 429 + #define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 430 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3 431 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14 432 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18 433 + #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L 434 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L 435 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L 436 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L 437 + //HDP_XDP_HDP_MBX_MC_CFG 438 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0 439 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4 440 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8 441 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc 442 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd 443 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe 444 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL 445 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L 446 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L 447 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L 448 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L 449 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L 450 + //HDP_XDP_HDP_MC_CFG 451 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3 452 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4 453 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8 454 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc 455 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd 456 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe 457 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L 458 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L 459 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L 460 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L 461 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L 462 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L 463 + //HDP_XDP_HST_CFG 464 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 465 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 466 + #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3 467 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4 468 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5 469 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L 470 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L 471 + #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L 472 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L 473 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L 474 + //HDP_XDP_HDP_IPH_CFG 475 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc 476 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd 477 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L 478 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L 479 + //HDP_XDP_P2P_BAR0 480 + #define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 481 + #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 482 + #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 483 + #define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL 484 + #define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L 485 + #define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L 486 + //HDP_XDP_P2P_BAR1 487 + #define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 488 + #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 489 + #define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 490 + #define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL 491 + #define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L 492 + #define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L 493 + //HDP_XDP_P2P_BAR2 494 + #define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 495 + #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 496 + #define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 497 + #define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL 498 + #define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L 499 + #define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L 500 + //HDP_XDP_P2P_BAR3 501 + #define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 502 + #define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 503 + #define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 504 + #define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL 505 + #define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L 506 + #define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L 507 + //HDP_XDP_P2P_BAR4 508 + #define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 509 + #define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 510 + #define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 511 + #define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL 512 + #define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L 513 + #define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L 514 + //HDP_XDP_P2P_BAR5 515 + #define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 516 + #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 517 + #define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 518 + #define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL 519 + #define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L 520 + #define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L 521 + //HDP_XDP_P2P_BAR6 522 + #define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 523 + #define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 524 + #define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 525 + #define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL 526 + #define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L 527 + #define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L 528 + //HDP_XDP_P2P_BAR7 529 + #define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 530 + #define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 531 + #define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 532 + #define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL 533 + #define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L 534 + #define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L 535 + //HDP_XDP_FLUSH_ARMED_STS 536 + #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 537 + #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL 538 + //HDP_XDP_FLUSH_CNTR0_STS 539 + #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 540 + #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL 541 + //HDP_XDP_BUSY_STS 542 + #define HDP_XDP_BUSY_STS__BUSY_BITS_0__SHIFT 0x0 543 + #define HDP_XDP_BUSY_STS__BUSY_BITS_1__SHIFT 0x1 544 + #define HDP_XDP_BUSY_STS__BUSY_BITS_2__SHIFT 0x2 545 + #define HDP_XDP_BUSY_STS__BUSY_BITS_3__SHIFT 0x3 546 + #define HDP_XDP_BUSY_STS__BUSY_BITS_4__SHIFT 0x4 547 + #define HDP_XDP_BUSY_STS__BUSY_BITS_5__SHIFT 0x5 548 + #define HDP_XDP_BUSY_STS__BUSY_BITS_6__SHIFT 0x6 549 + #define HDP_XDP_BUSY_STS__BUSY_BITS_7__SHIFT 0x7 550 + #define HDP_XDP_BUSY_STS__BUSY_BITS_8__SHIFT 0x8 551 + #define HDP_XDP_BUSY_STS__BUSY_BITS_9__SHIFT 0x9 552 + #define HDP_XDP_BUSY_STS__BUSY_BITS_10__SHIFT 0xa 553 + #define HDP_XDP_BUSY_STS__BUSY_BITS_11__SHIFT 0xb 554 + #define HDP_XDP_BUSY_STS__BUSY_BITS_12__SHIFT 0xc 555 + #define HDP_XDP_BUSY_STS__BUSY_BITS_13__SHIFT 0xd 556 + #define HDP_XDP_BUSY_STS__BUSY_BITS_14__SHIFT 0xe 557 + #define HDP_XDP_BUSY_STS__BUSY_BITS_15__SHIFT 0xf 558 + #define HDP_XDP_BUSY_STS__BUSY_BITS_16__SHIFT 0x10 559 + #define HDP_XDP_BUSY_STS__BUSY_BITS_17__SHIFT 0x11 560 + #define HDP_XDP_BUSY_STS__BUSY_BITS_18__SHIFT 0x12 561 + #define HDP_XDP_BUSY_STS__BUSY_BITS_19__SHIFT 0x13 562 + #define HDP_XDP_BUSY_STS__BUSY_BITS_20__SHIFT 0x14 563 + #define HDP_XDP_BUSY_STS__BUSY_BITS_21__SHIFT 0x15 564 + #define HDP_XDP_BUSY_STS__BUSY_BITS_22__SHIFT 0x16 565 + #define HDP_XDP_BUSY_STS__BUSY_BITS_23__SHIFT 0x17 566 + #define HDP_XDP_BUSY_STS__Z_FENCE_BIT__SHIFT 0x18 567 + #define HDP_XDP_BUSY_STS__BUSY_BITS_0_MASK 0x00000001L 568 + #define HDP_XDP_BUSY_STS__BUSY_BITS_1_MASK 0x00000002L 569 + #define HDP_XDP_BUSY_STS__BUSY_BITS_2_MASK 0x00000004L 570 + #define HDP_XDP_BUSY_STS__BUSY_BITS_3_MASK 0x00000008L 571 + #define HDP_XDP_BUSY_STS__BUSY_BITS_4_MASK 0x00000010L 572 + #define HDP_XDP_BUSY_STS__BUSY_BITS_5_MASK 0x00000020L 573 + #define HDP_XDP_BUSY_STS__BUSY_BITS_6_MASK 0x00000040L 574 + #define HDP_XDP_BUSY_STS__BUSY_BITS_7_MASK 0x00000080L 575 + #define HDP_XDP_BUSY_STS__BUSY_BITS_8_MASK 0x00000100L 576 + #define HDP_XDP_BUSY_STS__BUSY_BITS_9_MASK 0x00000200L 577 + #define HDP_XDP_BUSY_STS__BUSY_BITS_10_MASK 0x00000400L 578 + #define HDP_XDP_BUSY_STS__BUSY_BITS_11_MASK 0x00000800L 579 + #define HDP_XDP_BUSY_STS__BUSY_BITS_12_MASK 0x00001000L 580 + #define HDP_XDP_BUSY_STS__BUSY_BITS_13_MASK 0x00002000L 581 + #define HDP_XDP_BUSY_STS__BUSY_BITS_14_MASK 0x00004000L 582 + #define HDP_XDP_BUSY_STS__BUSY_BITS_15_MASK 0x00008000L 583 + #define HDP_XDP_BUSY_STS__BUSY_BITS_16_MASK 0x00010000L 584 + #define HDP_XDP_BUSY_STS__BUSY_BITS_17_MASK 0x00020000L 585 + #define HDP_XDP_BUSY_STS__BUSY_BITS_18_MASK 0x00040000L 586 + #define HDP_XDP_BUSY_STS__BUSY_BITS_19_MASK 0x00080000L 587 + #define HDP_XDP_BUSY_STS__BUSY_BITS_20_MASK 0x00100000L 588 + #define HDP_XDP_BUSY_STS__BUSY_BITS_21_MASK 0x00200000L 589 + #define HDP_XDP_BUSY_STS__BUSY_BITS_22_MASK 0x00400000L 590 + #define HDP_XDP_BUSY_STS__BUSY_BITS_23_MASK 0x00800000L 591 + #define HDP_XDP_BUSY_STS__Z_FENCE_BIT_MASK 0x01000000L 592 + //HDP_XDP_STICKY 593 + #define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 594 + #define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 595 + #define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL 596 + #define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L 597 + //HDP_XDP_CHKN 598 + #define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 599 + #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 600 + #define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 601 + #define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 602 + #define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL 603 + #define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L 604 + #define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L 605 + #define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L 606 + //HDP_XDP_BARS_ADDR_39_36 607 + #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 608 + #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 609 + #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 610 + #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc 611 + #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 612 + #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 613 + #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 614 + #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c 615 + #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL 616 + #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L 617 + #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L 618 + #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L 619 + #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L 620 + #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L 621 + #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L 622 + #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L 623 + //HDP_XDP_MC_VM_FB_LOCATION_BASE 624 + #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 625 + #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL 626 + //HDP_XDP_GPU_IOV_VIOLATION_LOG 627 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 628 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 629 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 630 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 631 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 632 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 633 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 634 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 635 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 636 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L 637 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 638 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 639 + //HDP_XDP_GPU_IOV_VIOLATION_LOG2 640 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 641 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL 642 + //HDP_XDP_MMHUB_ERROR 643 + #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1 644 + #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2 645 + #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3 646 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED__SHIFT 0x4 647 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5 648 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6 649 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7 650 + #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9 651 + #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa 652 + #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb 653 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED__SHIFT 0xc 654 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd 655 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe 656 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf 657 + #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11 658 + #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12 659 + #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13 660 + #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15 661 + #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16 662 + #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17 663 + #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L 664 + #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L 665 + #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L 666 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED_MASK 0x00000010L 667 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L 668 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L 669 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L 670 + #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L 671 + #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L 672 + #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L 673 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED_MASK 0x00001000L 674 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L 675 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L 676 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L 677 + #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L 678 + #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L 679 + #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L 680 + #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L 681 + #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L 682 + #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L 683 + 684 + #endif