phy: qcom: qmp-combo: Add new PHY sequences for SM8750

+221

drivers/phy/qualcomm/phy-qcom-qmp-combo.c

··· 32 32 #include "phy-qcom-qmp-pcs-usb-v4.h" 33 33 #include "phy-qcom-qmp-pcs-usb-v5.h" 34 34 #include "phy-qcom-qmp-pcs-usb-v6.h" 35 + #include "phy-qcom-qmp-pcs-usb-v8.h" 35 36 36 37 #include "phy-qcom-qmp-dp-com-v3.h" 37 38 ··· 211 210 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_N4_TX_TX_EMP_POST1_LVL, 212 211 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_N4_TX_HIGHZ_DRVR_EN, 213 212 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN, 213 + }; 214 + 215 + static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 216 + [QPHY_SW_RESET] = QPHY_V8_PCS_SW_RESET, 217 + [QPHY_START_CTRL] = QPHY_V8_PCS_START_CONTROL, 218 + [QPHY_PCS_STATUS] = QPHY_V8_PCS_PCS_STATUS1, 219 + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_PCS_POWER_DOWN_CONTROL, 220 + 221 + /* In PCS_USB */ 222 + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL, 223 + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR, 224 + 225 + [QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL, 226 + [QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS, 227 + [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS, 228 + [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, 229 + 230 + [QPHY_TX_TX_POL_INV] = QSERDES_V8_TX_TX_POL_INV, 231 + [QPHY_TX_TX_DRV_LVL] = QSERDES_V8_TX_TX_DRV_LVL, 232 + [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_TX_TX_EMP_POST1_LVL, 233 + [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V8_TX_HIGHZ_DRVR_EN, 234 + [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN, 214 235 }; 215 236 216 237 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { ··· 1494 1471 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10), 1495 1472 }; 1496 1473 1474 + static const struct qmp_phy_init_tbl sm8750_usb3_serdes_tbl[] = { 1475 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 1476 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1, 0x01), 1477 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x02), 1478 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x16), 1479 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x36), 1480 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE1, 0x04), 1481 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x16), 1482 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x41), 1483 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x41), 1484 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE1, 0x00), 1485 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE1, 0x55), 1486 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE1, 0x75), 1487 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE1, 0x01), 1488 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x01), 1489 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE1, 0x25), 1490 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE1, 0x02), 1491 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 1492 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 1493 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 1494 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 1495 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 1496 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1497 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x02), 1498 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x16), 1499 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x36), 1500 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x08), 1501 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x1a), 1502 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41), 1503 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE0, 0x00), 1504 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE0, 0x55), 1505 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE0, 0x75), 1506 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE0, 0x01), 1507 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE0, 0x25), 1508 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE0, 0x02), 1509 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BG_TIMER, 0x0a), 1510 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_EN_CENTER, 0x01), 1511 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER1, 0x62), 1512 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER2, 0x02), 1513 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_BUF_ENABLE, 0x0c), 1514 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0x1a), 1515 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x14), 1516 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04), 1517 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORE_CLK_EN, 0x20), 1518 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16), 1519 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 1520 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a), 1521 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36), 1522 + QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADDITIONAL_MISC, 0x0c), 1523 + }; 1524 + 1525 + static const struct qmp_phy_init_tbl sm8750_usb3_tx_tbl[] = { 1526 + QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_TX, 0x00), 1527 + QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_RX, 0x00), 1528 + QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1529 + QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 1530 + QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_1, 0xf5), 1531 + QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_3, 0x11), 1532 + QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_4, 0x31), 1533 + QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_5, 0x5f), 1534 + QMP_PHY_INIT_CFG(QSERDES_V8_TX_RCV_DETECT_LVL_2, 0x12), 1535 + QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x21, 1), 1536 + QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x05, 2), 1537 + }; 1538 + 1539 + static const struct qmp_phy_init_tbl sm8750_usb3_rx_tbl[] = { 1540 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FO_GAIN, 0x0a), 1541 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_GAIN, 0x06), 1542 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1543 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1544 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1545 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1546 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_PI_CONTROLS, 0x99), 1547 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH1, 0x08), 1548 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH2, 0x08), 1549 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN1, 0x00), 1550 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN2, 0x0a), 1551 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE, 0x20), 1552 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL1, 0x54), 1553 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL2, 0x0f), 1554 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_GM_CAL, 0x13), 1555 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1556 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1557 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1558 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW, 0x07), 1559 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1560 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1561 + 1562 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_ENABLES, 0x0c), 1563 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CNTRL, 0x04), 1564 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1565 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_LOW, 0x3f), 1566 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH, 0xbf), 1567 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH2, 0xff), 1568 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH3, 0xdf), 1569 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH4, 0xed), 1570 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_LOW, 0x19), 1571 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH, 0x09), 1572 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH2, 0x91), 1573 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH3, 0xb7), 1574 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH4, 0xaa), 1575 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_EN_TIMER, 0x04), 1576 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1577 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_DCC_CTRL1, 0x0c), 1578 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_VTH_CODE, 0x10), 1579 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_CTRL1, 0x14), 1580 + QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_TRIM, 0x08), 1581 + }; 1582 + 1583 + static const struct qmp_phy_init_tbl sm8750_usb3_pcs_tbl[] = { 1584 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1585 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG2, 0x89), 1586 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG3, 0x20), 1587 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG6, 0x13), 1588 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_REFGEN_REQ_CONFIG1, 0x21), 1589 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_RX_SIGDET_LVL, 0x55), 1590 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1591 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1592 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_CDR_RESET_TIME, 0x0a), 1593 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1594 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1595 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_PCS_TX_RX_CONFIG, 0x0c), 1596 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG1, 0x4b), 1597 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG5, 0x10), 1598 + }; 1599 + 1600 + static const struct qmp_phy_init_tbl sm8750_usb3_pcs_usb_tbl[] = { 1601 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1602 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07), 1603 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L, 0x40), 1604 + QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H, 0x00), 1605 + }; 1606 + 1497 1607 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = { 1498 1608 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1499 1609 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ··· 1935 1779 .usb3_pcs_usb = 0x1700, 1936 1780 .dp_serdes = 0x2000, 1937 1781 .dp_dp_phy = 0x2200, 1782 + }; 1783 + 1784 + static const struct qmp_combo_offsets qmp_combo_offsets_v8 = { 1785 + .com = 0x0000, 1786 + .txa = 0x1400, 1787 + .rxa = 0x1600, 1788 + .txb = 0x1800, 1789 + .rxb = 0x1a00, 1790 + .usb3_serdes = 0x1000, 1791 + .usb3_pcs_misc = 0x1c00, 1792 + .usb3_pcs = 0x1e00, 1793 + .usb3_pcs_usb = 0x2100, 1794 + .dp_serdes = 0x3000, 1795 + .dp_txa = 0x3400, 1796 + .dp_txb = 0x3800, 1797 + .dp_dp_phy = 0x3c00, 1938 1798 }; 1939 1799 1940 1800 static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = { ··· 2446 2274 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2447 2275 2448 2276 .regs = qmp_v6_usb3phy_regs_layout, 2277 + .reset_list = msm8996_usb3phy_reset_l, 2278 + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2279 + .vreg_list = qmp_phy_vreg_l, 2280 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2281 + }; 2282 + 2283 + static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = { 2284 + .offsets = &qmp_combo_offsets_v8, 2285 + 2286 + .serdes_tbl = sm8750_usb3_serdes_tbl, 2287 + .serdes_tbl_num = ARRAY_SIZE(sm8750_usb3_serdes_tbl), 2288 + .tx_tbl = sm8750_usb3_tx_tbl, 2289 + .tx_tbl_num = ARRAY_SIZE(sm8750_usb3_tx_tbl), 2290 + .rx_tbl = sm8750_usb3_rx_tbl, 2291 + .rx_tbl_num = ARRAY_SIZE(sm8750_usb3_rx_tbl), 2292 + .pcs_tbl = sm8750_usb3_pcs_tbl, 2293 + .pcs_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_tbl), 2294 + .pcs_usb_tbl = sm8750_usb3_pcs_usb_tbl, 2295 + .pcs_usb_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_usb_tbl), 2296 + 2297 + .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2298 + .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2299 + .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2300 + .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2301 + 2302 + .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2303 + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2304 + .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2305 + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2306 + .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2307 + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2308 + .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2309 + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2310 + 2311 + .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2312 + .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2313 + .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2314 + .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2315 + 2316 + .dp_aux_init = qmp_v4_dp_aux_init, 2317 + .configure_dp_tx = qmp_v4_configure_dp_tx, 2318 + .configure_dp_phy = qmp_v4_configure_dp_phy, 2319 + .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2320 + 2321 + .regs = qmp_v8_usb3phy_regs_layout, 2449 2322 .reset_list = msm8996_usb3phy_reset_l, 2450 2323 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2451 2324 .vreg_list = qmp_phy_vreg_l, ··· 4131 3914 { 4132 3915 .compatible = "qcom,sm8650-qmp-usb3-dp-phy", 4133 3916 .data = &sm8650_usb3dpphy_cfg, 3917 + }, 3918 + { 3919 + .compatible = "qcom,sm8750-qmp-usb3-dp-phy", 3920 + .data = &sm8750_usb3dpphy_cfg, 4134 3921 }, 4135 3922 { 4136 3923 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy",

+38

drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v8.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_PCS_USB_V8_H_ 7 + #define QCOM_PHY_QMP_PCS_USB_V8_H_ 8 + 9 + #define QPHY_V8_PCS_USB_POWER_STATE_CONFIG1 0x00 10 + #define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_STATUS 0x04 11 + #define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL 0x08 12 + #define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL2 0x0c 13 + #define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x10 14 + #define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR 0x14 15 + #define QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL 0x18 16 + #define QPHY_V8_PCS_USB_LFPS_TX_ECSTART 0x1c 17 + #define QPHY_V8_PCS_USB_LFPS_PER_TIMER_VAL 0x20 18 + #define QPHY_V8_PCS_USB_LFPS_TX_END_CNT_U3_START 0x24 19 + #define QPHY_V8_PCS_USB_LFPS_CONFIG1 0x28 20 + #define QPHY_V8_PCS_USB_RXEQTRAINING_LOCK_TIME 0x2c 21 + #define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME 0x30 22 + #define QPHY_V8_PCS_USB_RXEQTRAINING_CTLE_TIME 0x34 23 + #define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME_S2 0x38 24 + #define QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2 0x3c 25 + #define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L 0x40 26 + #define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H 0x44 27 + #define QPHY_V8_PCS_USB_ARCVR_DTCT_EN_PERIOD 0x48 28 + #define QPHY_V8_PCS_USB_ARCVR_DTCT_CM_DLY 0x4c 29 + #define QPHY_V8_PCS_USB_TXONESZEROS_RUN_LENGTH 0x50 30 + #define QPHY_V8_PCS_USB_ALFPS_DEGLITCH_VAL 0x54 31 + #define QPHY_V8_PCS_USB_SIGDET_STARTUP_TIMER_VAL 0x58 32 + #define QPHY_V8_PCS_USB_TEST_CONTROL 0x5c 33 + #define QPHY_V8_PCS_USB_RXTERMINATION_DLY_SEL 0x60 34 + #define QPHY_V8_PCS_USB_POWER_STATE_CONFIG2 0x64 35 + #define QPHY_V8_PCS_USB_POWER_STATE_CONFIG3 0x68 36 + #define QPHY_V8_PCS_USB_POWER_STATE_CONFIG4 0x6c 37 + 38 + #endif

+32

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_PCS_V8_H_ 7 + #define QCOM_PHY_QMP_PCS_V8_H_ 8 + 9 + /* Only for QMP V8 PHY - USB/PCIe PCS registers */ 10 + #define QPHY_V8_PCS_SW_RESET 0x000 11 + #define QPHY_V8_PCS_PCS_STATUS1 0x014 12 + #define QPHY_V8_PCS_POWER_DOWN_CONTROL 0x040 13 + #define QPHY_V8_PCS_START_CONTROL 0x044 14 + #define QPHY_V8_PCS_POWER_STATE_CONFIG1 0x090 15 + #define QPHY_V8_PCS_LOCK_DETECT_CONFIG1 0x0c4 16 + #define QPHY_V8_PCS_LOCK_DETECT_CONFIG2 0x0c8 17 + #define QPHY_V8_PCS_LOCK_DETECT_CONFIG3 0x0cc 18 + #define QPHY_V8_PCS_LOCK_DETECT_CONFIG6 0x0d8 19 + #define QPHY_V8_PCS_REFGEN_REQ_CONFIG1 0x0dc 20 + #define QPHY_V8_PCS_RX_SIGDET_LVL 0x188 21 + #define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 22 + #define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 23 + #define QPHY_V8_PCS_RATE_SLEW_CNTRL1 0x198 24 + #define QPHY_V8_PCS_CDR_RESET_TIME 0x1b0 25 + #define QPHY_V8_PCS_ALIGN_DETECT_CONFIG1 0x1c0 26 + #define QPHY_V8_PCS_ALIGN_DETECT_CONFIG2 0x1c4 27 + #define QPHY_V8_PCS_PCS_TX_RX_CONFIG 0x1d0 28 + #define QPHY_V8_PCS_EQ_CONFIG1 0x1dc 29 + #define QPHY_V8_PCS_EQ_CONFIG2 0x1e0 30 + #define QPHY_V8_PCS_EQ_CONFIG5 0x1ec 31 + 32 + #endif

+64

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_QSERDES_COM_V8_H_ 7 + #define QCOM_PHY_QMP_QSERDES_COM_V8_H_ 8 + 9 + /* Only for QMP V8 PHY - QSERDES COM registers */ 10 + #define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1 0x000 11 + #define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1 0x004 12 + #define QSERDES_V8_COM_SSC_STEP_SIZE3_MODE1 0x008 13 + #define QSERDES_V8_COM_CP_CTRL_MODE1 0x010 14 + #define QSERDES_V8_COM_PLL_RCTRL_MODE1 0x014 15 + #define QSERDES_V8_COM_PLL_CCTRL_MODE1 0x018 16 + #define QSERDES_V8_COM_CORECLK_DIV_MODE1 0x01c 17 + #define QSERDES_V8_COM_LOCK_CMP1_MODE1 0x020 18 + #define QSERDES_V8_COM_LOCK_CMP2_MODE1 0x024 19 + #define QSERDES_V8_COM_DEC_START_MODE1 0x028 20 + #define QSERDES_V8_COM_DEC_START_MSB_MODE1 0x02c 21 + #define QSERDES_V8_COM_DIV_FRAC_START1_MODE1 0x030 22 + #define QSERDES_V8_COM_DIV_FRAC_START2_MODE1 0x034 23 + #define QSERDES_V8_COM_DIV_FRAC_START3_MODE1 0x038 24 + #define QSERDES_V8_COM_HSCLK_SEL_1 0x03c 25 + #define QSERDES_V8_COM_VCO_TUNE1_MODE1 0x048 26 + #define QSERDES_V8_COM_VCO_TUNE2_MODE1 0x04c 27 + #define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x050 28 + #define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x054 29 + #define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058 30 + #define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c 31 + #define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0 0x060 32 + #define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0 0x064 33 + #define QSERDES_V8_COM_CP_CTRL_MODE0 0x070 34 + #define QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074 35 + #define QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078 36 + #define QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080 37 + #define QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084 38 + #define QSERDES_V8_COM_DEC_START_MODE0 0x088 39 + #define QSERDES_V8_COM_DEC_START_MSB_MODE0 0x08c 40 + #define QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090 41 + #define QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094 42 + #define QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098 43 + #define QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8 44 + #define QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac 45 + #define QSERDES_V8_COM_BG_TIMER 0x0bc 46 + #define QSERDES_V8_COM_SSC_EN_CENTER 0x0c0 47 + #define QSERDES_V8_COM_SSC_PER1 0x0cc 48 + #define QSERDES_V8_COM_SSC_PER2 0x0d0 49 + #define QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc 50 + #define QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8 51 + #define QSERDES_V8_COM_SYSCLK_EN_SEL 0x110 52 + #define QSERDES_V8_COM_RESETSM_CNTRL 0x118 53 + #define QSERDES_V8_COM_LOCK_CMP_CFG 0x124 54 + #define QSERDES_V8_COM_VCO_TUNE_MAP 0x140 55 + #define QSERDES_V8_COM_CORE_CLK_EN 0x170 56 + #define QSERDES_V8_COM_CMN_CONFIG_1 0x174 57 + #define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4 58 + #define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8 59 + #define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac 60 + #define QSERDES_V8_COM_ADDITIONAL_MISC 0x1b4 61 + #define QSERDES_V8_COM_CMN_STATUS 0x2c8 62 + #define QSERDES_V8_COM_C_READY_STATUS 0x2f0 63 + 64 + #endif

+68

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v8.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V8_H_ 7 + #define QCOM_PHY_QMP_QSERDES_TXRX_V8_H_ 8 + 9 + #define QSERDES_V8_TX_TX_EMP_POST1_LVL 0x00c 10 + #define QSERDES_V8_TX_TX_DRV_LVL 0x014 11 + #define QSERDES_V8_TX_RES_CODE_LANE_TX 0x034 12 + #define QSERDES_V8_TX_RES_CODE_LANE_RX 0x038 13 + #define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX 0x03c 14 + #define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX 0x040 15 + #define QSERDES_V8_TX_TRANSCEIVER_BIAS_EN 0x054 16 + #define QSERDES_V8_TX_HIGHZ_DRVR_EN 0x058 17 + #define QSERDES_V8_TX_TX_POL_INV 0x05c 18 + #define QSERDES_V8_TX_LANE_MODE_1 0x084 19 + #define QSERDES_V8_TX_LANE_MODE_2 0x088 20 + #define QSERDES_V8_TX_LANE_MODE_3 0x08c 21 + #define QSERDES_V8_TX_LANE_MODE_4 0x090 22 + #define QSERDES_V8_TX_LANE_MODE_5 0x094 23 + #define QSERDES_V8_TX_RCV_DETECT_LVL_2 0x0a4 24 + #define QSERDES_V8_TX_PI_QEC_CTRL 0x0e4 25 + 26 + #define QSERDES_V8_RX_UCDR_FO_GAIN 0x008 27 + #define QSERDES_V8_RX_UCDR_SO_GAIN 0x014 28 + #define QSERDES_V8_RX_UCDR_SVS_FO_GAIN 0x020 29 + #define QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN 0x030 30 + #define QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 31 + #define QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 32 + #define QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 33 + #define QSERDES_V8_RX_UCDR_PI_CONTROLS 0x044 34 + #define QSERDES_V8_RX_UCDR_SB2_THRESH1 0x04c 35 + #define QSERDES_V8_RX_UCDR_SB2_THRESH2 0x050 36 + #define QSERDES_V8_RX_UCDR_SB2_GAIN1 0x054 37 + #define QSERDES_V8_RX_UCDR_SB2_GAIN2 0x058 38 + #define QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE 0x060 39 + #define QSERDES_V8_RX_VGA_CAL_CNTRL1 0x0d4 40 + #define QSERDES_V8_RX_VGA_CAL_CNTRL2 0x0d8 41 + #define QSERDES_V8_RX_GM_CAL 0x0dc 42 + #define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 43 + #define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 44 + #define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 45 + #define QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW 0x0f8 46 + #define QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 47 + #define QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 48 + #define QSERDES_V8_RX_SIGDET_ENABLES 0x118 49 + #define QSERDES_V8_RX_SIGDET_CNTRL 0x11c 50 + #define QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL 0x124 51 + #define QSERDES_V8_RX_RX_MODE_00_LOW 0x15c 52 + #define QSERDES_V8_RX_RX_MODE_00_HIGH 0x160 53 + #define QSERDES_V8_RX_RX_MODE_00_HIGH2 0x164 54 + #define QSERDES_V8_RX_RX_MODE_00_HIGH3 0x168 55 + #define QSERDES_V8_RX_RX_MODE_00_HIGH4 0x16c 56 + #define QSERDES_V8_RX_RX_MODE_01_LOW 0x170 57 + #define QSERDES_V8_RX_RX_MODE_01_HIGH 0x174 58 + #define QSERDES_V8_RX_RX_MODE_01_HIGH2 0x178 59 + #define QSERDES_V8_RX_RX_MODE_01_HIGH3 0x17c 60 + #define QSERDES_V8_RX_RX_MODE_01_HIGH4 0x180 61 + #define QSERDES_V8_RX_DFE_EN_TIMER 0x1a0 62 + #define QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 63 + #define QSERDES_V8_RX_DCC_CTRL1 0x1a8 64 + #define QSERDES_V8_RX_VTH_CODE 0x1b0 65 + #define QSERDES_V8_RX_SIGDET_CAL_CTRL1 0x1e4 66 + #define QSERDES_V8_RX_SIGDET_CAL_TRIM 0x1f8 67 + 68 + #endif

+5

drivers/phy/qualcomm/phy-qcom-qmp.h

··· 30 30 #include "phy-qcom-qmp-qserdes-com-v7.h" 31 31 #include "phy-qcom-qmp-qserdes-txrx-v7.h" 32 32 33 + #include "phy-qcom-qmp-qserdes-com-v8.h" 34 + #include "phy-qcom-qmp-qserdes-txrx-v8.h" 35 + 33 36 #include "phy-qcom-qmp-qserdes-pll.h" 34 37 35 38 #include "phy-qcom-qmp-pcs-v2.h" ··· 54 51 #include "phy-qcom-qmp-pcs-v6_20.h" 55 52 56 53 #include "phy-qcom-qmp-pcs-v7.h" 54 + 55 + #include "phy-qcom-qmp-pcs-v8.h" 57 56 58 57 /* QPHY_SW_RESET bit */ 59 58 #define SW_RESET BIT(0)