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staging: rtl8192u: clean up blank line style issues

Add missing and remove unnecessary blank lines to clear checkpatch
issues.

CHECK: Please use a blank line after function/struct/union/enum declarations
CHECK: Blank lines aren't necessary before a close brace '}'
CHECK: Please don't use multiple blank lines
CHECK: Blank lines aren't necessary after an open brace '{'

Signed-off-by: Michael Straube <straube.linux@gmail.com>
Link: https://lore.kernel.org/r/20200919150823.16923-1-straube.linux@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Michael Straube and committed by
Greg Kroah-Hartman
c4309727 9079371e

+4 -81
+1 -11
drivers/staging/rtl8192u/r8192U_dm.c
··· 26 26 static u32 edca_setting_DL[HT_IOT_PEER_MAX] = { 27 27 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0x00a44f, 0x5ea44f 28 28 }; 29 + 29 30 static u32 edca_setting_UL[HT_IOT_PEER_MAX] = { 30 31 0x5e4322, 0x00a44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f 31 32 }; ··· 600 599 priv->rfa_txpowertrackingindex++; 601 600 priv->rfa_txpowertrackingindex_real++; 602 601 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); 603 - 604 602 } 605 603 } 606 604 priv->cck_present_attenuation_difference ··· 1268 1268 priv->btxpower_tracking = true; 1269 1269 priv->txpower_count = 0; 1270 1270 priv->btxpower_trackingInit = false; 1271 - 1272 1271 } 1273 1272 1274 1273 static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev) ··· 1772 1773 /* 1.5 Higher EDCCA. */ 1773 1774 /*PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);*/ 1774 1775 return; 1775 - 1776 1776 } 1777 1777 1778 1778 /* 2. When RSSI increase, We have to judge if it is larger than a threshold ··· 1834 1836 1835 1837 /* 2.5 DIG On. */ 1836 1838 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite. */ 1837 - 1838 1839 } 1839 1840 1840 1841 dm_ctrl_initgain_byrssi_highpwr(dev); ··· 2154 2157 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]); 2155 2158 priv->bis_cur_rdlstate = false; 2156 2159 } 2157 - 2158 2160 } 2159 2161 2160 2162 priv->bcurrent_turbo_EDCA = true; ··· 2186 2190 cpu_to_le32s(&u4bAcParam); 2187 2191 2188 2192 write_nic_dword(dev, EDCAPARA_BE, u4bAcParam); 2189 - 2190 2193 2191 2194 /* Check ACM bit. 2192 2195 * If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13. ··· 2291 2296 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n"); 2292 2297 priv->bpbc_pressed = true; 2293 2298 } 2294 - 2295 2299 } 2296 2300 2297 2301 /*----------------------------------------------------------------------------- ··· 2489 2495 cck_rx_ver2_min_index = i; 2490 2496 } 2491 2497 } 2492 - 2493 2498 } 2494 2499 } 2495 2500 } ··· 2708 2715 2709 2716 priv->ContinueDiffCount = 0; 2710 2717 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); 2711 - 2712 2718 } 2713 2719 2714 2720 static void dm_StartSWFsync(struct net_device *dev) ··· 2743 2751 add_timer(&priv->fsync_timer); 2744 2752 2745 2753 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd); 2746 - 2747 2754 } 2748 2755 2749 2756 static void dm_EndHWFsync(struct net_device *dev) ··· 2750 2759 RT_TRACE(COMP_HALDM, "%s\n", __func__); 2751 2760 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); 2752 2761 write_nic_byte(dev, 0xc3b, 0x49); 2753 - 2754 2762 } 2755 2763 2756 2764 void dm_check_fsync(struct net_device *dev)
+1
drivers/staging/rtl8192u/r8192U_hw.h
··· 239 239 #define EPROM_W_BIT BIT(1) 240 240 #define EPROM_R_BIT BIT(0) 241 241 }; 242 + 242 243 //---------------------------------------------------------------------------- 243 244 // 818xB AnaParm & AnaParm2 Register 244 245 //----------------------------------------------------------------------------
+2 -29
drivers/staging/rtl8192u/r8192U_wx.c
··· 138 138 priv->force_reset = *extra; 139 139 mutex_unlock(&priv->wx_mutex); 140 140 return 0; 141 - 142 141 } 143 142 144 143 static int r8192_wx_set_rawtx(struct net_device *dev, ··· 154 155 mutex_unlock(&priv->wx_mutex); 155 156 156 157 return ret; 157 - 158 158 } 159 159 160 160 static int r8192_wx_set_crcmon(struct net_device *dev, ··· 216 218 /* Scan capabilities */ 217 219 __u8 scan_capa; 218 220 }; 221 + 219 222 static int rtl8180_wx_get_range(struct net_device *dev, 220 223 struct iw_request_info *info, 221 224 union iwreq_data *wrqu, char *extra) ··· 293 294 /* range->max_r_time; */ /* Maximal retry lifetime */ 294 295 295 296 for (i = 0, val = 0; i < 14; i++) { 296 - 297 297 /* Include only legal frequencies for some countries */ 298 298 if ((GET_DOT11D_INFO(priv->ieee80211)->channel_map)[i+1]) { 299 299 range->freq[val].i = i + 1; ··· 348 350 return ret; 349 351 } 350 352 351 - 352 353 static int r8192_wx_get_scan(struct net_device *dev, struct iw_request_info *a, 353 354 union iwreq_data *wrqu, char *b) 354 355 { 355 - 356 356 int ret; 357 357 struct r8192_priv *priv = ieee80211_priv(dev); 358 358 ··· 440 444 return 0; 441 445 } 442 446 443 - 444 447 static int r8192_wx_get_frag(struct net_device *dev, 445 448 struct iw_request_info *info, 446 449 union iwreq_data *wrqu, char *extra) ··· 453 458 return 0; 454 459 } 455 460 456 - 457 461 static int r8192_wx_set_wap(struct net_device *dev, 458 462 struct iw_request_info *info, 459 463 union iwreq_data *awrq, 460 464 char *extra) 461 465 { 462 - 463 466 int ret; 464 467 struct r8192_priv *priv = ieee80211_priv(dev); 465 468 /* struct sockaddr *temp = (struct sockaddr *)awrq; */ ··· 468 475 mutex_unlock(&priv->wx_mutex); 469 476 470 477 return ret; 471 - 472 478 } 473 479 474 480 static int r8192_wx_get_wap(struct net_device *dev, ··· 514 522 515 523 mutex_unlock(&priv->wx_mutex); 516 524 517 - 518 - 519 525 /* sometimes, the length is zero while we do not type key value */ 520 526 if (wrqu->encoding.length != 0) { 521 - 522 527 for (i = 0; i < 4; i++) { 523 528 hwkey[i] |= key[4*i+0]&mask; 524 529 if (i == 1 && (4*i+1) == wrqu->encoding.length) ··· 561 572 zero_addr[key_idx], 562 573 0, /* DefaultKey */ 563 574 hwkey); /* KeyContent */ 564 - 565 575 } 566 576 567 577 else if (wrqu->encoding.length == 0xd) { ··· 574 586 zero_addr[key_idx], 575 587 0, /* DefaultKey */ 576 588 hwkey); /* KeyContent */ 577 - 578 589 } else { 579 590 netdev_warn(dev, "wrong type in WEP, not WEP40 and WEP104\n"); 580 591 } 581 - 582 592 } 583 593 584 594 return ret; 585 595 } 586 596 587 - 588 597 static int r8192_wx_set_scan_type(struct net_device *dev, struct iw_request_info *aa, 589 598 union iwreq_data *wrqu, char *p) 590 599 { 591 - 592 600 struct r8192_priv *priv = ieee80211_priv(dev); 593 601 int *parms = (int *)p; 594 602 int mode = parms[0]; ··· 593 609 594 610 return 1; 595 611 } 596 - 597 - 598 612 599 613 static int r8192_wx_set_retry(struct net_device *dev, 600 614 struct iw_request_info *info, ··· 645 663 { 646 664 struct r8192_priv *priv = ieee80211_priv(dev); 647 665 648 - 649 666 wrqu->retry.disabled = 0; /* can't be disabled */ 650 667 651 668 if ((wrqu->retry.flags & IW_RETRY_TYPE) == ··· 678 697 struct iw_request_info *info, 679 698 union iwreq_data *wrqu, char *extra) 680 699 { 681 - 682 700 struct r8192_priv *priv = ieee80211_priv(dev); 683 701 short err = 0; 684 702 ··· 705 725 int ret = 0; 706 726 struct r8192_priv *priv = ieee80211_priv(dev); 707 727 struct ieee80211_device *ieee = priv->ieee80211; 708 - 709 728 710 729 mutex_lock(&priv->wx_mutex); 711 730 ret = ieee80211_wx_set_encode_ext(priv->ieee80211, info, wrqu, extra); ··· 737 758 memcpy((u8 *)key, ext->key, 16); /* we only get 16 bytes key.why? WB 2008.7.1 */ 738 759 739 760 if ((alg & KEY_TYPE_WEP40) && (ieee->auth_mode != 2)) { 740 - 741 761 setKey(dev, 742 762 idx, /* EntryNao */ 743 763 idx, /* KeyIndex */ ··· 762 784 0, /* DefaultKey */ 763 785 key); /* KeyContent */ 764 786 } 765 - 766 - 767 787 } 768 788 769 789 end_hw_sec: 770 790 771 791 mutex_unlock(&priv->wx_mutex); 772 792 return ret; 773 - 774 793 } 794 + 775 795 static int r8192_wx_set_auth(struct net_device *dev, 776 796 struct iw_request_info *info, 777 797 union iwreq_data *data, char *extra) ··· 787 811 struct iw_request_info *info, 788 812 union iwreq_data *wrqu, char *extra) 789 813 { 790 - 791 814 int ret = 0; 792 815 struct r8192_priv *priv = ieee80211_priv(dev); 793 816 ··· 808 833 ret = ieee80211_wx_set_gen_ie(priv->ieee80211, extra, data->data.length); 809 834 mutex_unlock(&priv->wx_mutex); 810 835 return ret; 811 - 812 - 813 836 } 814 837 815 838 static int dummy(struct net_device *dev, struct iw_request_info *a,
-1
drivers/staging/rtl8192u/r819xU_cmdpkt.c
··· 336 336 priv->stats.txretrycount += pstx_status->txretry; 337 337 priv->stats.txfeedbackretry += pstx_status->txretry; 338 338 339 - 340 339 priv->stats.txmulticast += pstx_status->txmcok; 341 340 priv->stats.txbroadcast += pstx_status->txbcok; 342 341 priv->stats.txunicast += pstx_status->txucok;
-6
drivers/staging/rtl8192u/r819xU_firmware.c
··· 54 54 if ((buffer_len - frag_offset) > frag_threshold) { 55 55 frag_length = frag_threshold; 56 56 bLastIniPkt = 0; 57 - 58 57 } else { 59 58 frag_length = buffer_len - frag_offset; 60 59 bLastIniPkt = 1; 61 - 62 60 } 63 61 64 62 /* Allocate skb buffer to contain firmware info and tx descriptor info ··· 102 104 } while (frag_offset < buffer_len); 103 105 104 106 return rt_status; 105 - 106 107 } 107 108 108 109 /* ··· 169 172 170 173 static bool CPUcheck_firmware_ready(struct net_device *dev) 171 174 { 172 - 173 175 bool rt_status = true; 174 176 int check_time = 200000; 175 177 u32 CPU_status = 0; ··· 193 197 RT_TRACE(COMP_ERR, "ERR in %s()\n", __func__); 194 198 rt_status = false; 195 199 return rt_status; 196 - 197 200 } 198 201 199 202 bool init_firmware(struct net_device *dev) ··· 333 338 RT_TRACE(COMP_ERR, "ERR in %s()\n", __func__); 334 339 rt_status = false; 335 340 return rt_status; 336 - 337 341 } 338 342 339 343 MODULE_FIRMWARE("RTL8192U/boot.img");
-3
drivers/staging/rtl8192u/r819xU_firmware_img.h
··· 13 13 #define RadioD_ArrayLength 1 14 14 #define PHY_REGArrayLength 1 15 15 16 - 17 16 extern u32 Rtl8192UsbPHY_REGArray[]; 18 17 extern u32 Rtl8192UsbPHY_REG_1T2RArray[]; 19 18 extern u32 Rtl8192UsbRadioA_Array[]; ··· 22 23 extern u32 Rtl8192UsbMACPHY_Array[]; 23 24 extern u32 Rtl8192UsbMACPHY_Array_PG[]; 24 25 extern u32 Rtl8192UsbAGCTAB_Array[]; 25 - 26 - 27 26 28 27 #endif
-28
drivers/staging/rtl8192u/r819xU_phy.c
··· 67 67 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask, 68 68 u32 data) 69 69 { 70 - 71 70 u32 reg, bitshift; 72 71 73 72 if (bitmask != bMaskDWord) { ··· 168 169 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); 169 170 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); 170 171 171 - 172 172 /* TODO: we should not delay such a long time. Ask for help from SD3 */ 173 173 usleep_range(1000, 1000); 174 174 175 175 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, 176 176 bLSSIReadBackData); 177 - 178 177 179 178 /* Switch back to Reg_Mode0 */ 180 179 if (priv->rf_chip == RF_8256) { ··· 216 219 217 220 offset &= 0x3f; 218 221 if (priv->rf_chip == RF_8256) { 219 - 220 222 if (offset >= 31) { 221 223 priv->RfReg0Value[e_rfpath] |= 0x140; 222 224 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, ··· 243 247 244 248 /* Write operation */ 245 249 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); 246 - 247 250 248 251 if (offset == 0x0) 249 252 priv->RfReg0Value[e_rfpath] = data; ··· 325 330 u32 reg, bitshift; 326 331 struct r8192_priv *priv = ieee80211_priv(dev); 327 332 328 - 329 333 if (!rtl8192_phy_CheckIsLegalRFPath(dev, e_rfpath)) 330 334 return 0; 331 335 if (priv->Rf_Mode == RF_OP_By_FW) { ··· 336 342 bitshift = ffs(bitmask) - 1; 337 343 reg = (reg & bitmask) >> bitshift; 338 344 return reg; 339 - 340 345 } 341 346 342 347 /****************************************************************************** ··· 693 700 WriteAddr[HW90_BLOCK_RF] = 0x3; 694 701 RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock); 695 702 for (i = 0; i < CheckTimes; i++) { 696 - 697 703 /* Write data to register and readback */ 698 704 switch (CheckBlock) { 699 705 case HW90_BLOCK_MAC: ··· 726 734 ret = 1; 727 735 break; 728 736 } 729 - 730 737 731 738 /* Check whether readback data is correct */ 732 739 if (reg != WriteData[i]) { ··· 834 843 */ 835 844 rtl8192_BB_Config_ParaFile(dev); 836 845 } 837 - 838 846 839 847 /****************************************************************************** 840 848 * function: This function obtains the initialization value of Tx power Level ··· 951 961 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, 952 962 enum rf90_radio_path_e e_rfpath) 953 963 { 954 - 955 964 int i; 956 965 957 966 switch (e_rfpath) { 958 967 case RF90_PATH_A: 959 968 for (i = 0; i < RadioA_ArrayLength; i = i+2) { 960 - 961 969 if (Rtl8192UsbRadioA_Array[i] == 0xfe) { 962 970 mdelay(100); 963 971 continue; ··· 965 977 bMask12Bits, 966 978 Rtl8192UsbRadioA_Array[i+1]); 967 979 mdelay(1); 968 - 969 980 } 970 981 break; 971 982 case RF90_PATH_B: 972 983 for (i = 0; i < RadioB_ArrayLength; i = i+2) { 973 - 974 984 if (Rtl8192UsbRadioB_Array[i] == 0xfe) { 975 985 mdelay(100); 976 986 continue; ··· 978 992 bMask12Bits, 979 993 Rtl8192UsbRadioB_Array[i+1]); 980 994 mdelay(1); 981 - 982 995 } 983 996 break; 984 997 case RF90_PATH_C: 985 998 for (i = 0; i < RadioC_ArrayLength; i = i+2) { 986 - 987 999 if (Rtl8192UsbRadioC_Array[i] == 0xfe) { 988 1000 mdelay(100); 989 1001 continue; ··· 991 1007 bMask12Bits, 992 1008 Rtl8192UsbRadioC_Array[i+1]); 993 1009 mdelay(1); 994 - 995 1010 } 996 1011 break; 997 1012 case RF90_PATH_D: 998 1013 for (i = 0; i < RadioD_ArrayLength; i = i+2) { 999 - 1000 1014 if (Rtl8192UsbRadioD_Array[i] == 0xfe) { 1001 1015 mdelay(100); 1002 1016 continue; ··· 1004 1022 bMask12Bits, 1005 1023 Rtl8192UsbRadioD_Array[i+1]); 1006 1024 mdelay(1); 1007 - 1008 1025 } 1009 1026 break; 1010 1027 default: ··· 1011 1030 } 1012 1031 1013 1032 return 0; 1014 - 1015 1033 } 1016 1034 1017 1035 /****************************************************************************** ··· 1205 1225 } 1206 1226 /* FIXME: need to check whether channel is legal or not here */ 1207 1227 1208 - 1209 1228 /* <1> Fill up pre common command. */ 1210 1229 PreCommonCmdCnt = 0; 1211 1230 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, ··· 1264 1285 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); 1265 1286 return true; 1266 1287 } 1267 - 1268 1288 1269 1289 do { 1270 1290 switch (*stage) { ··· 1356 1378 *****************************************************************************/ 1357 1379 void rtl8192_SwChnl_WorkItem(struct net_device *dev) 1358 1380 { 1359 - 1360 1381 struct r8192_priv *priv = ieee80211_priv(dev); 1361 1382 1362 1383 RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", 1363 1384 priv->chan); 1364 - 1365 1385 1366 1386 rtl8192_phy_FinishSwChnlNow(dev, priv->chan); 1367 1387 ··· 1435 1459 *****************************************************************************/ 1436 1460 void rtl8192_SetBWModeWorkItem(struct net_device *dev) 1437 1461 { 1438 - 1439 1462 struct r8192_priv *priv = ieee80211_priv(dev); 1440 1463 u8 regBwOpMode; 1441 1464 1442 1465 RT_TRACE(COMP_SWBW, "%s() Switch to %s bandwidth\n", __func__, 1443 1466 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); 1444 - 1445 1467 1446 1468 if (priv->rf_chip == RF_PSEUDO_11N) { 1447 1469 priv->SetBWModeInProgress = false; ··· 1537 1563 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n", 1538 1564 priv->CurrentChannelBW); 1539 1565 break; 1540 - 1541 1566 } 1542 1567 /* Skip over setting of J-mode in BB register here. 1543 1568 * Default value is "None J mode". ··· 1597 1624 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; 1598 1625 1599 1626 rtl8192_SetBWModeWorkItem(dev); 1600 - 1601 1627 } 1602 1628 1603 1629 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
-3
drivers/staging/rtl8192u/r819xU_phyreg.h
··· 2 2 #ifndef _R819XU_PHYREG_H 3 3 #define _R819XU_PHYREG_H 4 4 5 - 6 5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/ 7 6 8 7 /* page8 */ ··· 80 81 #define rOFDM0_XDTxIQImbalance 0xc98 81 82 #define rOFDM0_XDTxAFE 0xc9c 82 83 83 - 84 84 /* page d */ 85 85 #define rOFDM1_LSTF 0xd00 86 86 #define rOFDM1_TRxPathEnable 0xd04 ··· 92 94 #define rTxAGC_Mcs07_Mcs04 0xe14 93 95 #define rTxAGC_Mcs11_Mcs08 0xe18 94 96 #define rTxAGC_Mcs15_Mcs12 0xe1c 95 - 96 97 97 98 /* RF 98 99 * Zebra1