Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

x86/platform/intel/pmc_atom: Print index of device in loop

The register mapping may change from one platform to another.
Thus, indices might be not the same on different platforms. The
patch makes the code to print the device index dynamically at
run time.

The patch also changes the for loop to iterate over the map
until a terminator is found.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Aubrey Li <aubrey.li@linux.intel.com>
Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>
Cc: Kumar P Mahesh <mahesh.kumar.p@intel.com>
Link: http://lkml.kernel.org/r/1436192944-56496-3-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

authored by

Andy Shevchenko and committed by
Ingo Molnar
c3c65aa6 68872eb9

+63 -63
+63 -63
arch/x86/kernel/pmc_atom.c
··· 43 43 }; 44 44 45 45 static const struct pmc_bit_map dev_map[] = { 46 - {"0 - LPSS1_F0_DMA", BIT_LPSS1_F0_DMA}, 47 - {"1 - LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1}, 48 - {"2 - LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2}, 49 - {"3 - LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1}, 50 - {"4 - LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2}, 51 - {"5 - LPSS1_F5_SPI", BIT_LPSS1_F5_SPI}, 52 - {"6 - LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX}, 53 - {"7 - LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX}, 54 - {"8 - SCC_EMMC", BIT_SCC_EMMC}, 55 - {"9 - SCC_SDIO", BIT_SCC_SDIO}, 56 - {"10 - SCC_SDCARD", BIT_SCC_SDCARD}, 57 - {"11 - SCC_MIPI", BIT_SCC_MIPI}, 58 - {"12 - HDA", BIT_HDA}, 59 - {"13 - LPE", BIT_LPE}, 60 - {"14 - OTG", BIT_OTG}, 61 - {"15 - USH", BIT_USH}, 62 - {"16 - GBE", BIT_GBE}, 63 - {"17 - SATA", BIT_SATA}, 64 - {"18 - USB_EHCI", BIT_USB_EHCI}, 65 - {"19 - SEC", BIT_SEC}, 66 - {"20 - PCIE_PORT0", BIT_PCIE_PORT0}, 67 - {"21 - PCIE_PORT1", BIT_PCIE_PORT1}, 68 - {"22 - PCIE_PORT2", BIT_PCIE_PORT2}, 69 - {"23 - PCIE_PORT3", BIT_PCIE_PORT3}, 70 - {"24 - LPSS2_F0_DMA", BIT_LPSS2_F0_DMA}, 71 - {"25 - LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1}, 72 - {"26 - LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2}, 73 - {"27 - LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3}, 74 - {"28 - LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4}, 75 - {"29 - LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5}, 76 - {"30 - LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6}, 77 - {"31 - LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7}, 78 - {"32 - SMB", BIT_SMB}, 79 - {"33 - OTG_SS_PHY", BIT_OTG_SS_PHY}, 80 - {"34 - USH_SS_PHY", BIT_USH_SS_PHY}, 81 - {"35 - DFX", BIT_DFX}, 46 + {"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA}, 47 + {"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1}, 48 + {"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2}, 49 + {"LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1}, 50 + {"LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2}, 51 + {"LPSS1_F5_SPI", BIT_LPSS1_F5_SPI}, 52 + {"LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX}, 53 + {"LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX}, 54 + {"SCC_EMMC", BIT_SCC_EMMC}, 55 + {"SCC_SDIO", BIT_SCC_SDIO}, 56 + {"SCC_SDCARD", BIT_SCC_SDCARD}, 57 + {"SCC_MIPI", BIT_SCC_MIPI}, 58 + {"HDA", BIT_HDA}, 59 + {"LPE", BIT_LPE}, 60 + {"OTG", BIT_OTG}, 61 + {"USH", BIT_USH}, 62 + {"GBE", BIT_GBE}, 63 + {"SATA", BIT_SATA}, 64 + {"USB_EHCI", BIT_USB_EHCI}, 65 + {"SEC", BIT_SEC}, 66 + {"PCIE_PORT0", BIT_PCIE_PORT0}, 67 + {"PCIE_PORT1", BIT_PCIE_PORT1}, 68 + {"PCIE_PORT2", BIT_PCIE_PORT2}, 69 + {"PCIE_PORT3", BIT_PCIE_PORT3}, 70 + {"LPSS2_F0_DMA", BIT_LPSS2_F0_DMA}, 71 + {"LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1}, 72 + {"LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2}, 73 + {"LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3}, 74 + {"LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4}, 75 + {"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5}, 76 + {"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6}, 77 + {"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7}, 78 + {"SMB", BIT_SMB}, 79 + {"OTG_SS_PHY", BIT_OTG_SS_PHY}, 80 + {"USH_SS_PHY", BIT_USH_SS_PHY}, 81 + {"DFX", BIT_DFX}, 82 + {}, 82 83 }; 83 84 84 85 static const struct pmc_bit_map pss_map[] = { 85 - {"0 - GBE", PMC_PSS_BIT_GBE}, 86 - {"1 - SATA", PMC_PSS_BIT_SATA}, 87 - {"2 - HDA", PMC_PSS_BIT_HDA}, 88 - {"3 - SEC", PMC_PSS_BIT_SEC}, 89 - {"4 - PCIE", PMC_PSS_BIT_PCIE}, 90 - {"5 - LPSS", PMC_PSS_BIT_LPSS}, 91 - {"6 - LPE", PMC_PSS_BIT_LPE}, 92 - {"7 - DFX", PMC_PSS_BIT_DFX}, 93 - {"8 - USH_CTRL", PMC_PSS_BIT_USH_CTRL}, 94 - {"9 - USH_SUS", PMC_PSS_BIT_USH_SUS}, 95 - {"10 - USH_VCCS", PMC_PSS_BIT_USH_VCCS}, 96 - {"11 - USH_VCCA", PMC_PSS_BIT_USH_VCCA}, 97 - {"12 - OTG_CTRL", PMC_PSS_BIT_OTG_CTRL}, 98 - {"13 - OTG_VCCS", PMC_PSS_BIT_OTG_VCCS}, 99 - {"14 - OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK}, 100 - {"15 - OTG_VCCA", PMC_PSS_BIT_OTG_VCCA}, 101 - {"16 - USB", PMC_PSS_BIT_USB}, 102 - {"17 - USB_SUS", PMC_PSS_BIT_USB_SUS}, 86 + {"GBE", PMC_PSS_BIT_GBE}, 87 + {"SATA", PMC_PSS_BIT_SATA}, 88 + {"HDA", PMC_PSS_BIT_HDA}, 89 + {"SEC", PMC_PSS_BIT_SEC}, 90 + {"PCIE", PMC_PSS_BIT_PCIE}, 91 + {"LPSS", PMC_PSS_BIT_LPSS}, 92 + {"LPE", PMC_PSS_BIT_LPE}, 93 + {"DFX", PMC_PSS_BIT_DFX}, 94 + {"USH_CTRL", PMC_PSS_BIT_USH_CTRL}, 95 + {"USH_SUS", PMC_PSS_BIT_USH_SUS}, 96 + {"USH_VCCS", PMC_PSS_BIT_USH_VCCS}, 97 + {"USH_VCCA", PMC_PSS_BIT_USH_VCCA}, 98 + {"OTG_CTRL", PMC_PSS_BIT_OTG_CTRL}, 99 + {"OTG_VCCS", PMC_PSS_BIT_OTG_VCCS}, 100 + {"OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK}, 101 + {"OTG_VCCA", PMC_PSS_BIT_OTG_VCCA}, 102 + {"USB", PMC_PSS_BIT_USB}, 103 + {"USB_SUS", PMC_PSS_BIT_USB_SUS}, 104 + {}, 103 105 }; 104 106 105 107 static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset) ··· 174 172 struct pmc_dev *pmc = s->private; 175 173 u32 func_dis, func_dis_2, func_dis_index; 176 174 u32 d3_sts_0, d3_sts_1, d3_sts_index; 177 - int dev_num, dev_index, reg_index; 175 + int dev_index, reg_index; 178 176 179 177 func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS); 180 178 func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2); 181 179 d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0); 182 180 d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1); 183 181 184 - dev_num = ARRAY_SIZE(dev_map); 185 - 186 - for (dev_index = 0; dev_index < dev_num; dev_index++) { 182 + for (dev_index = 0; dev_map[dev_index].name; dev_index++) { 187 183 reg_index = dev_index / PMC_REG_BIT_WIDTH; 188 184 if (reg_index) { 189 185 func_dis_index = func_dis_2; ··· 191 191 d3_sts_index = d3_sts_0; 192 192 } 193 193 194 - seq_printf(s, "Dev: %-32s\tState: %s [%s]\n", 195 - dev_map[dev_index].name, 194 + seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n", 195 + dev_index, dev_map[dev_index].name, 196 196 dev_map[dev_index].bit_mask & func_dis_index ? 197 197 "Disabled" : "Enabled ", 198 198 dev_map[dev_index].bit_mask & d3_sts_index ? ··· 219 219 u32 pss = pmc_reg_read(pmc, PMC_PSS); 220 220 int pss_index; 221 221 222 - for (pss_index = 0; pss_index < ARRAY_SIZE(pss_map); pss_index++) { 223 - seq_printf(s, "Island: %-32s\tState: %s\n", 224 - pss_map[pss_index].name, 222 + for (pss_index = 0; pss_map[pss_index].name; pss_index++) { 223 + seq_printf(s, "Island: %-2d - %-32s\tState: %s\n", 224 + pss_index, pss_map[pss_index].name, 225 225 pss_map[pss_index].bit_mask & pss ? "Off" : "On"); 226 226 } 227 227 return 0;