commit c3a2f0dfe1cecac76950f340f540c1a887dd2500 · tjh.dev/kernel

+1 -1

drivers/scsi/qla2xxx/qla_attr.c

··· 206 206 .name = "optrom", 207 207 .mode = S_IRUSR | S_IWUSR, 208 208 }, 209 - .size = OPTROM_SIZE_24XX, 209 + .size = 0, 210 210 .read = qla2x00_sysfs_read_optrom, 211 211 .write = qla2x00_sysfs_write_optrom, 212 212 };

+925 -219

drivers/scsi/qla2xxx/qla_dbg.c

··· 37 37 return ptr + (ha->response_q_length * sizeof(response_t)); 38 38 } 39 39 40 + static int 41 + qla2xxx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram, 42 + uint32_t cram_size, uint32_t *ext_mem, void **nxt) 43 + { 44 + int rval; 45 + uint32_t cnt, stat, timer, risc_address, ext_mem_cnt; 46 + uint16_t mb[4]; 47 + struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 48 + 49 + rval = QLA_SUCCESS; 50 + risc_address = ext_mem_cnt = 0; 51 + memset(mb, 0, sizeof(mb)); 52 + 53 + /* Code RAM. */ 54 + risc_address = 0x20000; 55 + WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED); 56 + clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 57 + 58 + for (cnt = 0; cnt < cram_size / 4 && rval == QLA_SUCCESS; 59 + cnt++, risc_address++) { 60 + WRT_REG_WORD(&reg->mailbox1, LSW(risc_address)); 61 + WRT_REG_WORD(&reg->mailbox8, MSW(risc_address)); 62 + RD_REG_WORD(&reg->mailbox8); 63 + WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); 64 + 65 + for (timer = 6000000; timer; timer--) { 66 + /* Check for pending interrupts. */ 67 + stat = RD_REG_DWORD(&reg->host_status); 68 + if (stat & HSRX_RISC_INT) { 69 + stat &= 0xff; 70 + 71 + if (stat == 0x1 || stat == 0x2 || 72 + stat == 0x10 || stat == 0x11) { 73 + set_bit(MBX_INTERRUPT, 74 + &ha->mbx_cmd_flags); 75 + 76 + mb[0] = RD_REG_WORD(&reg->mailbox0); 77 + mb[2] = RD_REG_WORD(&reg->mailbox2); 78 + mb[3] = RD_REG_WORD(&reg->mailbox3); 79 + 80 + WRT_REG_DWORD(&reg->hccr, 81 + HCCRX_CLR_RISC_INT); 82 + RD_REG_DWORD(&reg->hccr); 83 + break; 84 + } 85 + 86 + /* Clear this intr; it wasn't a mailbox intr */ 87 + WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); 88 + RD_REG_DWORD(&reg->hccr); 89 + } 90 + udelay(5); 91 + } 92 + 93 + if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 94 + rval = mb[0] & MBS_MASK; 95 + code_ram[cnt] = htonl((mb[3] << 16) | mb[2]); 96 + } else { 97 + rval = QLA_FUNCTION_FAILED; 98 + } 99 + } 100 + 101 + if (rval == QLA_SUCCESS) { 102 + /* External Memory. */ 103 + risc_address = 0x100000; 104 + ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1; 105 + WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED); 106 + clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 107 + } 108 + for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS; 109 + cnt++, risc_address++) { 110 + WRT_REG_WORD(&reg->mailbox1, LSW(risc_address)); 111 + WRT_REG_WORD(&reg->mailbox8, MSW(risc_address)); 112 + RD_REG_WORD(&reg->mailbox8); 113 + WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); 114 + 115 + for (timer = 6000000; timer; timer--) { 116 + /* Check for pending interrupts. */ 117 + stat = RD_REG_DWORD(&reg->host_status); 118 + if (stat & HSRX_RISC_INT) { 119 + stat &= 0xff; 120 + 121 + if (stat == 0x1 || stat == 0x2 || 122 + stat == 0x10 || stat == 0x11) { 123 + set_bit(MBX_INTERRUPT, 124 + &ha->mbx_cmd_flags); 125 + 126 + mb[0] = RD_REG_WORD(&reg->mailbox0); 127 + mb[2] = RD_REG_WORD(&reg->mailbox2); 128 + mb[3] = RD_REG_WORD(&reg->mailbox3); 129 + 130 + WRT_REG_DWORD(&reg->hccr, 131 + HCCRX_CLR_RISC_INT); 132 + RD_REG_DWORD(&reg->hccr); 133 + break; 134 + } 135 + 136 + /* Clear this intr; it wasn't a mailbox intr */ 137 + WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); 138 + RD_REG_DWORD(&reg->hccr); 139 + } 140 + udelay(5); 141 + } 142 + 143 + if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 144 + rval = mb[0] & MBS_MASK; 145 + ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]); 146 + } else { 147 + rval = QLA_FUNCTION_FAILED; 148 + } 149 + } 150 + 151 + *nxt = rval == QLA_SUCCESS ? &ext_mem[cnt]: NULL; 152 + return rval; 153 + } 154 + 40 155 /** 41 156 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. 42 157 * @ha: HA context ··· 748 633 qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) 749 634 { 750 635 int rval; 751 - uint32_t cnt, timer; 636 + uint32_t cnt; 752 637 uint32_t risc_address; 753 - uint16_t mb[4], wd; 638 + uint16_t mb0, wd; 754 639 755 - uint32_t stat; 756 640 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 757 641 uint32_t __iomem *dmp_reg; 758 642 uint32_t *iter_reg; ··· 759 645 unsigned long flags; 760 646 struct qla24xx_fw_dump *fw; 761 647 uint32_t ext_mem_cnt; 762 - void *eft; 648 + void *nxt; 763 649 764 650 risc_address = ext_mem_cnt = 0; 765 - memset(mb, 0, sizeof(mb)); 766 651 flags = 0; 767 652 768 653 if (!hardware_locked) ··· 814 701 /* Shadow registers. */ 815 702 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 816 703 RD_REG_DWORD(&reg->iobase_addr); 817 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 818 - WRT_REG_DWORD(dmp_reg, 0xB0000000); 819 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 820 - fw->shadow_reg[0] = htonl(RD_REG_DWORD(dmp_reg)); 704 + WRT_REG_DWORD(&reg->iobase_select, 0xB0000000); 705 + fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 821 706 822 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 823 - WRT_REG_DWORD(dmp_reg, 0xB0100000); 824 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 825 - fw->shadow_reg[1] = htonl(RD_REG_DWORD(dmp_reg)); 707 + WRT_REG_DWORD(&reg->iobase_select, 0xB0100000); 708 + fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 826 709 827 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 828 - WRT_REG_DWORD(dmp_reg, 0xB0200000); 829 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 830 - fw->shadow_reg[2] = htonl(RD_REG_DWORD(dmp_reg)); 710 + WRT_REG_DWORD(&reg->iobase_select, 0xB0200000); 711 + fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 831 712 832 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 833 - WRT_REG_DWORD(dmp_reg, 0xB0300000); 834 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 835 - fw->shadow_reg[3] = htonl(RD_REG_DWORD(dmp_reg)); 713 + WRT_REG_DWORD(&reg->iobase_select, 0xB0300000); 714 + fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 836 715 837 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 838 - WRT_REG_DWORD(dmp_reg, 0xB0400000); 839 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 840 - fw->shadow_reg[4] = htonl(RD_REG_DWORD(dmp_reg)); 716 + WRT_REG_DWORD(&reg->iobase_select, 0xB0400000); 717 + fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 841 718 842 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 843 - WRT_REG_DWORD(dmp_reg, 0xB0500000); 844 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 845 - fw->shadow_reg[5] = htonl(RD_REG_DWORD(dmp_reg)); 719 + WRT_REG_DWORD(&reg->iobase_select, 0xB0500000); 720 + fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 846 721 847 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 848 - WRT_REG_DWORD(dmp_reg, 0xB0600000); 849 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 850 - fw->shadow_reg[6] = htonl(RD_REG_DWORD(dmp_reg)); 722 + WRT_REG_DWORD(&reg->iobase_select, 0xB0600000); 723 + fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 851 724 852 725 /* Mailbox registers. */ 853 - mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 726 + mbx_reg = &reg->mailbox0; 854 727 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 855 728 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 856 729 857 730 /* Transfer sequence registers. */ 858 731 iter_reg = fw->xseq_gp_reg; 859 732 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00); 860 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 733 + dmp_reg = &reg->iobase_window; 861 734 for (cnt = 0; cnt < 16; cnt++) 862 735 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 863 736 864 737 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10); 865 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 738 + dmp_reg = &reg->iobase_window; 866 739 for (cnt = 0; cnt < 16; cnt++) 867 740 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 868 741 869 742 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20); 870 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 743 + dmp_reg = &reg->iobase_window; 871 744 for (cnt = 0; cnt < 16; cnt++) 872 745 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 873 746 874 747 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30); 875 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 748 + dmp_reg = &reg->iobase_window; 876 749 for (cnt = 0; cnt < 16; cnt++) 877 750 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 878 751 879 752 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40); 880 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 753 + dmp_reg = &reg->iobase_window; 881 754 for (cnt = 0; cnt < 16; cnt++) 882 755 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 883 756 884 757 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50); 885 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 758 + dmp_reg = &reg->iobase_window; 886 759 for (cnt = 0; cnt < 16; cnt++) 887 760 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 888 761 889 762 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60); 890 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 763 + dmp_reg = &reg->iobase_window; 891 764 for (cnt = 0; cnt < 16; cnt++) 892 765 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 893 766 894 767 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70); 895 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 768 + dmp_reg = &reg->iobase_window; 896 769 for (cnt = 0; cnt < 16; cnt++) 897 770 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 898 771 899 772 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0); 900 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 773 + dmp_reg = &reg->iobase_window; 901 774 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) 902 775 fw->xseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 903 776 904 777 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0); 905 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 778 + dmp_reg = &reg->iobase_window; 906 779 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) 907 780 fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 908 781 909 782 /* Receive sequence registers. */ 910 783 iter_reg = fw->rseq_gp_reg; 911 784 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00); 912 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 785 + dmp_reg = &reg->iobase_window; 913 786 for (cnt = 0; cnt < 16; cnt++) 914 787 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 915 788 916 789 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10); 917 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 790 + dmp_reg = &reg->iobase_window; 918 791 for (cnt = 0; cnt < 16; cnt++) 919 792 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 920 793 921 794 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20); 922 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 795 + dmp_reg = &reg->iobase_window; 923 796 for (cnt = 0; cnt < 16; cnt++) 924 797 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 925 798 926 799 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30); 927 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 800 + dmp_reg = &reg->iobase_window; 928 801 for (cnt = 0; cnt < 16; cnt++) 929 802 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 930 803 931 804 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40); 932 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 805 + dmp_reg = &reg->iobase_window; 933 806 for (cnt = 0; cnt < 16; cnt++) 934 807 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 935 808 936 809 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50); 937 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 810 + dmp_reg = &reg->iobase_window; 938 811 for (cnt = 0; cnt < 16; cnt++) 939 812 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 940 813 941 814 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60); 942 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 815 + dmp_reg = &reg->iobase_window; 943 816 for (cnt = 0; cnt < 16; cnt++) 944 817 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 945 818 946 819 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70); 947 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 820 + dmp_reg = &reg->iobase_window; 948 821 for (cnt = 0; cnt < 16; cnt++) 949 822 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 950 823 951 824 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0); 952 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 825 + dmp_reg = &reg->iobase_window; 953 826 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) 954 827 fw->rseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 955 828 956 829 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0); 957 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 830 + dmp_reg = &reg->iobase_window; 958 831 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) 959 832 fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 960 833 961 834 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0); 962 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 835 + dmp_reg = &reg->iobase_window; 963 836 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) 964 837 fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 965 838 966 839 /* Command DMA registers. */ 967 840 WRT_REG_DWORD(&reg->iobase_addr, 0x7100); 968 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 841 + dmp_reg = &reg->iobase_window; 969 842 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) 970 843 fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 971 844 972 845 /* Queues. */ 973 846 iter_reg = fw->req0_dma_reg; 974 847 WRT_REG_DWORD(&reg->iobase_addr, 0x7200); 975 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 848 + dmp_reg = &reg->iobase_window; 976 849 for (cnt = 0; cnt < 8; cnt++) 977 850 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 978 851 979 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 852 + dmp_reg = &reg->iobase_q; 980 853 for (cnt = 0; cnt < 7; cnt++) 981 854 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 982 855 983 856 iter_reg = fw->resp0_dma_reg; 984 857 WRT_REG_DWORD(&reg->iobase_addr, 0x7300); 985 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 858 + dmp_reg = &reg->iobase_window; 986 859 for (cnt = 0; cnt < 8; cnt++) 987 860 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 988 861 989 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 862 + dmp_reg = &reg->iobase_q; 990 863 for (cnt = 0; cnt < 7; cnt++) 991 864 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 992 865 993 866 iter_reg = fw->req1_dma_reg; 994 867 WRT_REG_DWORD(&reg->iobase_addr, 0x7400); 995 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 868 + dmp_reg = &reg->iobase_window; 996 869 for (cnt = 0; cnt < 8; cnt++) 997 870 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 998 871 999 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 872 + dmp_reg = &reg->iobase_q; 1000 873 for (cnt = 0; cnt < 7; cnt++) 1001 874 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1002 875 1003 876 /* Transmit DMA registers. */ 1004 877 iter_reg = fw->xmt0_dma_reg; 1005 878 WRT_REG_DWORD(&reg->iobase_addr, 0x7600); 1006 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 879 + dmp_reg = &reg->iobase_window; 1007 880 for (cnt = 0; cnt < 16; cnt++) 1008 881 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1009 882 1010 883 WRT_REG_DWORD(&reg->iobase_addr, 0x7610); 1011 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 884 + dmp_reg = &reg->iobase_window; 1012 885 for (cnt = 0; cnt < 16; cnt++) 1013 886 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1014 887 1015 888 iter_reg = fw->xmt1_dma_reg; 1016 889 WRT_REG_DWORD(&reg->iobase_addr, 0x7620); 1017 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 890 + dmp_reg = &reg->iobase_window; 1018 891 for (cnt = 0; cnt < 16; cnt++) 1019 892 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1020 893 1021 894 WRT_REG_DWORD(&reg->iobase_addr, 0x7630); 1022 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 895 + dmp_reg = &reg->iobase_window; 1023 896 for (cnt = 0; cnt < 16; cnt++) 1024 897 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1025 898 1026 899 iter_reg = fw->xmt2_dma_reg; 1027 900 WRT_REG_DWORD(&reg->iobase_addr, 0x7640); 1028 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 901 + dmp_reg = &reg->iobase_window; 1029 902 for (cnt = 0; cnt < 16; cnt++) 1030 903 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1031 904 1032 905 WRT_REG_DWORD(&reg->iobase_addr, 0x7650); 1033 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 906 + dmp_reg = &reg->iobase_window; 1034 907 for (cnt = 0; cnt < 16; cnt++) 1035 908 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1036 909 1037 910 iter_reg = fw->xmt3_dma_reg; 1038 911 WRT_REG_DWORD(&reg->iobase_addr, 0x7660); 1039 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 912 + dmp_reg = &reg->iobase_window; 1040 913 for (cnt = 0; cnt < 16; cnt++) 1041 914 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1042 915 1043 916 WRT_REG_DWORD(&reg->iobase_addr, 0x7670); 1044 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 917 + dmp_reg = &reg->iobase_window; 1045 918 for (cnt = 0; cnt < 16; cnt++) 1046 919 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1047 920 1048 921 iter_reg = fw->xmt4_dma_reg; 1049 922 WRT_REG_DWORD(&reg->iobase_addr, 0x7680); 1050 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 923 + dmp_reg = &reg->iobase_window; 1051 924 for (cnt = 0; cnt < 16; cnt++) 1052 925 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1053 926 1054 927 WRT_REG_DWORD(&reg->iobase_addr, 0x7690); 1055 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 928 + dmp_reg = &reg->iobase_window; 1056 929 for (cnt = 0; cnt < 16; cnt++) 1057 930 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1058 931 1059 932 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0); 1060 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 933 + dmp_reg = &reg->iobase_window; 1061 934 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) 1062 935 fw->xmt_data_dma_reg[cnt] = 1063 936 htonl(RD_REG_DWORD(dmp_reg++)); ··· 1051 952 /* Receive DMA registers. */ 1052 953 iter_reg = fw->rcvt0_data_dma_reg; 1053 954 WRT_REG_DWORD(&reg->iobase_addr, 0x7700); 1054 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 955 + dmp_reg = &reg->iobase_window; 1055 956 for (cnt = 0; cnt < 16; cnt++) 1056 957 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1057 958 1058 959 WRT_REG_DWORD(&reg->iobase_addr, 0x7710); 1059 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 960 + dmp_reg = &reg->iobase_window; 1060 961 for (cnt = 0; cnt < 16; cnt++) 1061 962 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1062 963 1063 964 iter_reg = fw->rcvt1_data_dma_reg; 1064 965 WRT_REG_DWORD(&reg->iobase_addr, 0x7720); 1065 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 966 + dmp_reg = &reg->iobase_window; 1066 967 for (cnt = 0; cnt < 16; cnt++) 1067 968 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1068 969 1069 970 WRT_REG_DWORD(&reg->iobase_addr, 0x7730); 1070 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 971 + dmp_reg = &reg->iobase_window; 1071 972 for (cnt = 0; cnt < 16; cnt++) 1072 973 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1073 974 1074 975 /* RISC registers. */ 1075 976 iter_reg = fw->risc_gp_reg; 1076 977 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00); 1077 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 978 + dmp_reg = &reg->iobase_window; 1078 979 for (cnt = 0; cnt < 16; cnt++) 1079 980 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1080 981 1081 982 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10); 1082 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 983 + dmp_reg = &reg->iobase_window; 1083 984 for (cnt = 0; cnt < 16; cnt++) 1084 985 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1085 986 1086 987 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20); 1087 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 988 + dmp_reg = &reg->iobase_window; 1088 989 for (cnt = 0; cnt < 16; cnt++) 1089 990 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1090 991 1091 992 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30); 1092 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 993 + dmp_reg = &reg->iobase_window; 1093 994 for (cnt = 0; cnt < 16; cnt++) 1094 995 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1095 996 1096 997 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40); 1097 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 998 + dmp_reg = &reg->iobase_window; 1098 999 for (cnt = 0; cnt < 16; cnt++) 1099 1000 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1100 1001 1101 1002 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50); 1102 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1003 + dmp_reg = &reg->iobase_window; 1103 1004 for (cnt = 0; cnt < 16; cnt++) 1104 1005 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1105 1006 1106 1007 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60); 1107 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1008 + dmp_reg = &reg->iobase_window; 1108 1009 for (cnt = 0; cnt < 16; cnt++) 1109 1010 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1110 1011 1111 1012 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 1112 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1013 + dmp_reg = &reg->iobase_window; 1113 1014 for (cnt = 0; cnt < 16; cnt++) 1114 1015 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1115 1016 1116 1017 /* Local memory controller registers. */ 1117 1018 iter_reg = fw->lmc_reg; 1118 1019 WRT_REG_DWORD(&reg->iobase_addr, 0x3000); 1119 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1020 + dmp_reg = &reg->iobase_window; 1120 1021 for (cnt = 0; cnt < 16; cnt++) 1121 1022 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1122 1023 1123 1024 WRT_REG_DWORD(&reg->iobase_addr, 0x3010); 1124 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1025 + dmp_reg = &reg->iobase_window; 1125 1026 for (cnt = 0; cnt < 16; cnt++) 1126 1027 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1127 1028 1128 1029 WRT_REG_DWORD(&reg->iobase_addr, 0x3020); 1129 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1030 + dmp_reg = &reg->iobase_window; 1130 1031 for (cnt = 0; cnt < 16; cnt++) 1131 1032 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1132 1033 1133 1034 WRT_REG_DWORD(&reg->iobase_addr, 0x3030); 1134 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1035 + dmp_reg = &reg->iobase_window; 1135 1036 for (cnt = 0; cnt < 16; cnt++) 1136 1037 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1137 1038 1138 1039 WRT_REG_DWORD(&reg->iobase_addr, 0x3040); 1139 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1040 + dmp_reg = &reg->iobase_window; 1140 1041 for (cnt = 0; cnt < 16; cnt++) 1141 1042 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1142 1043 1143 1044 WRT_REG_DWORD(&reg->iobase_addr, 0x3050); 1144 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1045 + dmp_reg = &reg->iobase_window; 1145 1046 for (cnt = 0; cnt < 16; cnt++) 1146 1047 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1147 1048 1148 1049 WRT_REG_DWORD(&reg->iobase_addr, 0x3060); 1149 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1050 + dmp_reg = &reg->iobase_window; 1150 1051 for (cnt = 0; cnt < 16; cnt++) 1151 1052 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1152 1053 1153 1054 /* Fibre Protocol Module registers. */ 1154 1055 iter_reg = fw->fpm_hdw_reg; 1155 1056 WRT_REG_DWORD(&reg->iobase_addr, 0x4000); 1156 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1057 + dmp_reg = &reg->iobase_window; 1157 1058 for (cnt = 0; cnt < 16; cnt++) 1158 1059 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1159 1060 1160 1061 WRT_REG_DWORD(&reg->iobase_addr, 0x4010); 1161 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1062 + dmp_reg = &reg->iobase_window; 1162 1063 for (cnt = 0; cnt < 16; cnt++) 1163 1064 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1164 1065 1165 1066 WRT_REG_DWORD(&reg->iobase_addr, 0x4020); 1166 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1067 + dmp_reg = &reg->iobase_window; 1167 1068 for (cnt = 0; cnt < 16; cnt++) 1168 1069 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1169 1070 1170 1071 WRT_REG_DWORD(&reg->iobase_addr, 0x4030); 1171 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1072 + dmp_reg = &reg->iobase_window; 1172 1073 for (cnt = 0; cnt < 16; cnt++) 1173 1074 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1174 1075 1175 1076 WRT_REG_DWORD(&reg->iobase_addr, 0x4040); 1176 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1077 + dmp_reg = &reg->iobase_window; 1177 1078 for (cnt = 0; cnt < 16; cnt++) 1178 1079 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1179 1080 1180 1081 WRT_REG_DWORD(&reg->iobase_addr, 0x4050); 1181 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1082 + dmp_reg = &reg->iobase_window; 1182 1083 for (cnt = 0; cnt < 16; cnt++) 1183 1084 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1184 1085 1185 1086 WRT_REG_DWORD(&reg->iobase_addr, 0x4060); 1186 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1087 + dmp_reg = &reg->iobase_window; 1187 1088 for (cnt = 0; cnt < 16; cnt++) 1188 1089 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1189 1090 1190 1091 WRT_REG_DWORD(&reg->iobase_addr, 0x4070); 1191 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1092 + dmp_reg = &reg->iobase_window; 1192 1093 for (cnt = 0; cnt < 16; cnt++) 1193 1094 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1194 1095 1195 1096 WRT_REG_DWORD(&reg->iobase_addr, 0x4080); 1196 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1097 + dmp_reg = &reg->iobase_window; 1197 1098 for (cnt = 0; cnt < 16; cnt++) 1198 1099 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1199 1100 1200 1101 WRT_REG_DWORD(&reg->iobase_addr, 0x4090); 1201 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1102 + dmp_reg = &reg->iobase_window; 1202 1103 for (cnt = 0; cnt < 16; cnt++) 1203 1104 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1204 1105 1205 1106 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0); 1206 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1107 + dmp_reg = &reg->iobase_window; 1207 1108 for (cnt = 0; cnt < 16; cnt++) 1208 1109 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1209 1110 1210 1111 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0); 1211 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1112 + dmp_reg = &reg->iobase_window; 1212 1113 for (cnt = 0; cnt < 16; cnt++) 1213 1114 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1214 1115 1215 1116 /* Frame Buffer registers. */ 1216 1117 iter_reg = fw->fb_hdw_reg; 1217 1118 WRT_REG_DWORD(&reg->iobase_addr, 0x6000); 1218 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1119 + dmp_reg = &reg->iobase_window; 1219 1120 for (cnt = 0; cnt < 16; cnt++) 1220 1121 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1221 1122 1222 1123 WRT_REG_DWORD(&reg->iobase_addr, 0x6010); 1223 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1124 + dmp_reg = &reg->iobase_window; 1224 1125 for (cnt = 0; cnt < 16; cnt++) 1225 1126 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1226 1127 1227 1128 WRT_REG_DWORD(&reg->iobase_addr, 0x6020); 1228 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1129 + dmp_reg = &reg->iobase_window; 1229 1130 for (cnt = 0; cnt < 16; cnt++) 1230 1131 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1231 1132 1232 1133 WRT_REG_DWORD(&reg->iobase_addr, 0x6030); 1233 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1134 + dmp_reg = &reg->iobase_window; 1234 1135 for (cnt = 0; cnt < 16; cnt++) 1235 1136 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1236 1137 1237 1138 WRT_REG_DWORD(&reg->iobase_addr, 0x6040); 1238 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1139 + dmp_reg = &reg->iobase_window; 1239 1140 for (cnt = 0; cnt < 16; cnt++) 1240 1141 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1241 1142 1242 1143 WRT_REG_DWORD(&reg->iobase_addr, 0x6100); 1243 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1144 + dmp_reg = &reg->iobase_window; 1244 1145 for (cnt = 0; cnt < 16; cnt++) 1245 1146 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1246 1147 1247 1148 WRT_REG_DWORD(&reg->iobase_addr, 0x6130); 1248 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1149 + dmp_reg = &reg->iobase_window; 1249 1150 for (cnt = 0; cnt < 16; cnt++) 1250 1151 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1251 1152 1252 1153 WRT_REG_DWORD(&reg->iobase_addr, 0x6150); 1253 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1154 + dmp_reg = &reg->iobase_window; 1254 1155 for (cnt = 0; cnt < 16; cnt++) 1255 1156 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1256 1157 1257 1158 WRT_REG_DWORD(&reg->iobase_addr, 0x6170); 1258 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1159 + dmp_reg = &reg->iobase_window; 1259 1160 for (cnt = 0; cnt < 16; cnt++) 1260 1161 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1261 1162 1262 1163 WRT_REG_DWORD(&reg->iobase_addr, 0x6190); 1263 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1164 + dmp_reg = &reg->iobase_window; 1264 1165 for (cnt = 0; cnt < 16; cnt++) 1265 1166 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1266 1167 1267 1168 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0); 1268 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1169 + dmp_reg = &reg->iobase_window; 1269 1170 for (cnt = 0; cnt < 16; cnt++) 1270 1171 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1271 1172 ··· 1286 1187 1287 1188 udelay(100); 1288 1189 /* Wait for firmware to complete NVRAM accesses. */ 1289 - mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1290 - for (cnt = 10000 ; cnt && mb[0]; cnt--) { 1190 + mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1191 + for (cnt = 10000 ; cnt && mb0; cnt--) { 1291 1192 udelay(5); 1292 - mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1193 + mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1293 1194 barrier(); 1294 1195 } 1295 1196 ··· 1313 1214 rval = QLA_FUNCTION_TIMEOUT; 1314 1215 } 1315 1216 1316 - /* Memory. */ 1317 - if (rval == QLA_SUCCESS) { 1318 - /* Code RAM. */ 1319 - risc_address = 0x20000; 1320 - WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED); 1321 - clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 1322 - } 1323 - for (cnt = 0; cnt < sizeof(fw->code_ram) / 4 && rval == QLA_SUCCESS; 1324 - cnt++, risc_address++) { 1325 - WRT_REG_WORD(&reg->mailbox1, LSW(risc_address)); 1326 - WRT_REG_WORD(&reg->mailbox8, MSW(risc_address)); 1327 - RD_REG_WORD(&reg->mailbox8); 1328 - WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); 1329 - 1330 - for (timer = 6000000; timer; timer--) { 1331 - /* Check for pending interrupts. */ 1332 - stat = RD_REG_DWORD(&reg->host_status); 1333 - if (stat & HSRX_RISC_INT) { 1334 - stat &= 0xff; 1335 - 1336 - if (stat == 0x1 || stat == 0x2 || 1337 - stat == 0x10 || stat == 0x11) { 1338 - set_bit(MBX_INTERRUPT, 1339 - &ha->mbx_cmd_flags); 1340 - 1341 - mb[0] = RD_REG_WORD(&reg->mailbox0); 1342 - mb[2] = RD_REG_WORD(&reg->mailbox2); 1343 - mb[3] = RD_REG_WORD(&reg->mailbox3); 1344 - 1345 - WRT_REG_DWORD(&reg->hccr, 1346 - HCCRX_CLR_RISC_INT); 1347 - RD_REG_DWORD(&reg->hccr); 1348 - break; 1349 - } 1350 - 1351 - /* Clear this intr; it wasn't a mailbox intr */ 1352 - WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); 1353 - RD_REG_DWORD(&reg->hccr); 1354 - } 1355 - udelay(5); 1356 - } 1357 - 1358 - if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 1359 - rval = mb[0] & MBS_MASK; 1360 - fw->code_ram[cnt] = htonl((mb[3] << 16) | mb[2]); 1361 - } else { 1362 - rval = QLA_FUNCTION_FAILED; 1363 - } 1364 - } 1217 + if (rval == QLA_SUCCESS) 1218 + rval = qla2xxx_dump_memory(ha, fw->code_ram, 1219 + sizeof(fw->code_ram), fw->ext_mem, &nxt); 1365 1220 1366 1221 if (rval == QLA_SUCCESS) { 1367 - /* External Memory. */ 1368 - risc_address = 0x100000; 1369 - ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1; 1370 - WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED); 1371 - clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 1372 - } 1373 - for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS; 1374 - cnt++, risc_address++) { 1375 - WRT_REG_WORD(&reg->mailbox1, LSW(risc_address)); 1376 - WRT_REG_WORD(&reg->mailbox8, MSW(risc_address)); 1377 - RD_REG_WORD(&reg->mailbox8); 1378 - WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); 1379 - 1380 - for (timer = 6000000; timer; timer--) { 1381 - /* Check for pending interrupts. */ 1382 - stat = RD_REG_DWORD(&reg->host_status); 1383 - if (stat & HSRX_RISC_INT) { 1384 - stat &= 0xff; 1385 - 1386 - if (stat == 0x1 || stat == 0x2 || 1387 - stat == 0x10 || stat == 0x11) { 1388 - set_bit(MBX_INTERRUPT, 1389 - &ha->mbx_cmd_flags); 1390 - 1391 - mb[0] = RD_REG_WORD(&reg->mailbox0); 1392 - mb[2] = RD_REG_WORD(&reg->mailbox2); 1393 - mb[3] = RD_REG_WORD(&reg->mailbox3); 1394 - 1395 - WRT_REG_DWORD(&reg->hccr, 1396 - HCCRX_CLR_RISC_INT); 1397 - RD_REG_DWORD(&reg->hccr); 1398 - break; 1399 - } 1400 - 1401 - /* Clear this intr; it wasn't a mailbox intr */ 1402 - WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); 1403 - RD_REG_DWORD(&reg->hccr); 1404 - } 1405 - udelay(5); 1406 - } 1407 - 1408 - if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 1409 - rval = mb[0] & MBS_MASK; 1410 - fw->ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]); 1411 - } else { 1412 - rval = QLA_FUNCTION_FAILED; 1413 - } 1414 - } 1415 - 1416 - if (rval == QLA_SUCCESS) { 1417 - eft = qla2xxx_copy_queues(ha, &fw->ext_mem[cnt]); 1222 + nxt = qla2xxx_copy_queues(ha, nxt); 1418 1223 if (ha->eft) 1419 - memcpy(eft, ha->eft, ntohl(ha->fw_dump->eft_size)); 1224 + memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size)); 1420 1225 } 1421 1226 1422 1227 if (rval != QLA_SUCCESS) { ··· 1336 1333 } 1337 1334 1338 1335 qla24xx_fw_dump_failed: 1336 + if (!hardware_locked) 1337 + spin_unlock_irqrestore(&ha->hardware_lock, flags); 1338 + } 1339 + 1340 + void 1341 + qla25xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) 1342 + { 1343 + int rval; 1344 + uint32_t cnt; 1345 + uint32_t risc_address; 1346 + uint16_t mb0, wd; 1347 + 1348 + struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1349 + uint32_t __iomem *dmp_reg; 1350 + uint32_t *iter_reg; 1351 + uint16_t __iomem *mbx_reg; 1352 + unsigned long flags; 1353 + struct qla25xx_fw_dump *fw; 1354 + uint32_t ext_mem_cnt; 1355 + void *nxt; 1356 + 1357 + risc_address = ext_mem_cnt = 0; 1358 + flags = 0; 1359 + 1360 + if (!hardware_locked) 1361 + spin_lock_irqsave(&ha->hardware_lock, flags); 1362 + 1363 + if (!ha->fw_dump) { 1364 + qla_printk(KERN_WARNING, ha, 1365 + "No buffer available for dump!!!\n"); 1366 + goto qla25xx_fw_dump_failed; 1367 + } 1368 + 1369 + if (ha->fw_dumped) { 1370 + qla_printk(KERN_WARNING, ha, 1371 + "Firmware has been previously dumped (%p) -- ignoring " 1372 + "request...\n", ha->fw_dump); 1373 + goto qla25xx_fw_dump_failed; 1374 + } 1375 + fw = &ha->fw_dump->isp.isp25; 1376 + qla2xxx_prep_dump(ha, ha->fw_dump); 1377 + 1378 + rval = QLA_SUCCESS; 1379 + fw->host_status = htonl(RD_REG_DWORD(&reg->host_status)); 1380 + 1381 + /* Pause RISC. */ 1382 + if ((RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0) { 1383 + WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET | 1384 + HCCRX_CLR_HOST_INT); 1385 + RD_REG_DWORD(&reg->hccr); /* PCI Posting. */ 1386 + WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE); 1387 + for (cnt = 30000; 1388 + (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 && 1389 + rval == QLA_SUCCESS; cnt--) { 1390 + if (cnt) 1391 + udelay(100); 1392 + else 1393 + rval = QLA_FUNCTION_TIMEOUT; 1394 + } 1395 + } 1396 + 1397 + if (rval == QLA_SUCCESS) { 1398 + /* Host interface registers. */ 1399 + dmp_reg = (uint32_t __iomem *)(reg + 0); 1400 + for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1401 + fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1402 + 1403 + /* Disable interrupts. */ 1404 + WRT_REG_DWORD(&reg->ictrl, 0); 1405 + RD_REG_DWORD(&reg->ictrl); 1406 + 1407 + /* Shadow registers. */ 1408 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 1409 + RD_REG_DWORD(&reg->iobase_addr); 1410 + WRT_REG_DWORD(&reg->iobase_select, 0xB0000000); 1411 + fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1412 + 1413 + WRT_REG_DWORD(&reg->iobase_select, 0xB0100000); 1414 + fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1415 + 1416 + WRT_REG_DWORD(&reg->iobase_select, 0xB0200000); 1417 + fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1418 + 1419 + WRT_REG_DWORD(&reg->iobase_select, 0xB0300000); 1420 + fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1421 + 1422 + WRT_REG_DWORD(&reg->iobase_select, 0xB0400000); 1423 + fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1424 + 1425 + WRT_REG_DWORD(&reg->iobase_select, 0xB0500000); 1426 + fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1427 + 1428 + WRT_REG_DWORD(&reg->iobase_select, 0xB0600000); 1429 + fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1430 + 1431 + WRT_REG_DWORD(&reg->iobase_select, 0xB0700000); 1432 + fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1433 + 1434 + WRT_REG_DWORD(&reg->iobase_select, 0xB0800000); 1435 + fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1436 + 1437 + WRT_REG_DWORD(&reg->iobase_select, 0xB0900000); 1438 + fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1439 + 1440 + WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000); 1441 + fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1442 + 1443 + /* RISC I/O register. */ 1444 + WRT_REG_DWORD(&reg->iobase_addr, 0x0010); 1445 + RD_REG_DWORD(&reg->iobase_addr); 1446 + fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window)); 1447 + 1448 + /* Mailbox registers. */ 1449 + mbx_reg = &reg->mailbox0; 1450 + for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1451 + fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1452 + 1453 + /* Transfer sequence registers. */ 1454 + iter_reg = fw->xseq_gp_reg; 1455 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF00); 1456 + dmp_reg = &reg->iobase_window; 1457 + for (cnt = 0; cnt < 16; cnt++) 1458 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1459 + 1460 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF10); 1461 + dmp_reg = &reg->iobase_window; 1462 + for (cnt = 0; cnt < 16; cnt++) 1463 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1464 + 1465 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF20); 1466 + dmp_reg = &reg->iobase_window; 1467 + for (cnt = 0; cnt < 16; cnt++) 1468 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1469 + 1470 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF30); 1471 + dmp_reg = &reg->iobase_window; 1472 + for (cnt = 0; cnt < 16; cnt++) 1473 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1474 + 1475 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF40); 1476 + dmp_reg = &reg->iobase_window; 1477 + for (cnt = 0; cnt < 16; cnt++) 1478 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1479 + 1480 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF50); 1481 + dmp_reg = &reg->iobase_window; 1482 + for (cnt = 0; cnt < 16; cnt++) 1483 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1484 + 1485 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF60); 1486 + dmp_reg = &reg->iobase_window; 1487 + for (cnt = 0; cnt < 16; cnt++) 1488 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1489 + 1490 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF70); 1491 + dmp_reg = &reg->iobase_window; 1492 + for (cnt = 0; cnt < 16; cnt++) 1493 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1494 + 1495 + iter_reg = fw->xseq_0_reg; 1496 + WRT_REG_DWORD(&reg->iobase_addr, 0xBFC0); 1497 + dmp_reg = &reg->iobase_window; 1498 + for (cnt = 0; cnt < 16; cnt++) 1499 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1500 + 1501 + WRT_REG_DWORD(&reg->iobase_addr, 0xBFD0); 1502 + dmp_reg = &reg->iobase_window; 1503 + for (cnt = 0; cnt < 16; cnt++) 1504 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1505 + 1506 + WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0); 1507 + dmp_reg = &reg->iobase_window; 1508 + for (cnt = 0; cnt < 16; cnt++) 1509 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1510 + 1511 + WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0); 1512 + dmp_reg = &reg->iobase_window; 1513 + for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) 1514 + fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1515 + 1516 + /* Receive sequence registers. */ 1517 + iter_reg = fw->rseq_gp_reg; 1518 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF00); 1519 + dmp_reg = &reg->iobase_window; 1520 + for (cnt = 0; cnt < 16; cnt++) 1521 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1522 + 1523 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF10); 1524 + dmp_reg = &reg->iobase_window; 1525 + for (cnt = 0; cnt < 16; cnt++) 1526 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1527 + 1528 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF20); 1529 + dmp_reg = &reg->iobase_window; 1530 + for (cnt = 0; cnt < 16; cnt++) 1531 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1532 + 1533 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF30); 1534 + dmp_reg = &reg->iobase_window; 1535 + for (cnt = 0; cnt < 16; cnt++) 1536 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1537 + 1538 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF40); 1539 + dmp_reg = &reg->iobase_window; 1540 + for (cnt = 0; cnt < 16; cnt++) 1541 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1542 + 1543 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF50); 1544 + dmp_reg = &reg->iobase_window; 1545 + for (cnt = 0; cnt < 16; cnt++) 1546 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1547 + 1548 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF60); 1549 + dmp_reg = &reg->iobase_window; 1550 + for (cnt = 0; cnt < 16; cnt++) 1551 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1552 + 1553 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF70); 1554 + dmp_reg = &reg->iobase_window; 1555 + for (cnt = 0; cnt < 16; cnt++) 1556 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1557 + 1558 + iter_reg = fw->rseq_0_reg; 1559 + WRT_REG_DWORD(&reg->iobase_addr, 0xFFC0); 1560 + dmp_reg = &reg->iobase_window; 1561 + for (cnt = 0; cnt < 16; cnt++) 1562 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1563 + 1564 + WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0); 1565 + dmp_reg = &reg->iobase_window; 1566 + for (cnt = 0; cnt < 16; cnt++) 1567 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1568 + 1569 + WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0); 1570 + dmp_reg = &reg->iobase_window; 1571 + for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) 1572 + fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1573 + 1574 + WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0); 1575 + dmp_reg = &reg->iobase_window; 1576 + for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) 1577 + fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1578 + 1579 + /* Auxiliary sequence registers. */ 1580 + iter_reg = fw->aseq_gp_reg; 1581 + WRT_REG_DWORD(&reg->iobase_addr, 0xB000); 1582 + dmp_reg = &reg->iobase_window; 1583 + for (cnt = 0; cnt < 16; cnt++) 1584 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1585 + 1586 + WRT_REG_DWORD(&reg->iobase_addr, 0xB010); 1587 + dmp_reg = &reg->iobase_window; 1588 + for (cnt = 0; cnt < 16; cnt++) 1589 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1590 + 1591 + WRT_REG_DWORD(&reg->iobase_addr, 0xB020); 1592 + dmp_reg = &reg->iobase_window; 1593 + for (cnt = 0; cnt < 16; cnt++) 1594 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1595 + 1596 + WRT_REG_DWORD(&reg->iobase_addr, 0xB030); 1597 + dmp_reg = &reg->iobase_window; 1598 + for (cnt = 0; cnt < 16; cnt++) 1599 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1600 + 1601 + WRT_REG_DWORD(&reg->iobase_addr, 0xB040); 1602 + dmp_reg = &reg->iobase_window; 1603 + for (cnt = 0; cnt < 16; cnt++) 1604 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1605 + 1606 + WRT_REG_DWORD(&reg->iobase_addr, 0xB050); 1607 + dmp_reg = &reg->iobase_window; 1608 + for (cnt = 0; cnt < 16; cnt++) 1609 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1610 + 1611 + WRT_REG_DWORD(&reg->iobase_addr, 0xB060); 1612 + dmp_reg = &reg->iobase_window; 1613 + for (cnt = 0; cnt < 16; cnt++) 1614 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1615 + 1616 + WRT_REG_DWORD(&reg->iobase_addr, 0xB070); 1617 + dmp_reg = &reg->iobase_window; 1618 + for (cnt = 0; cnt < 16; cnt++) 1619 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1620 + 1621 + iter_reg = fw->aseq_0_reg; 1622 + WRT_REG_DWORD(&reg->iobase_addr, 0xB0C0); 1623 + dmp_reg = &reg->iobase_window; 1624 + for (cnt = 0; cnt < 16; cnt++) 1625 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1626 + 1627 + WRT_REG_DWORD(&reg->iobase_addr, 0xB0D0); 1628 + dmp_reg = &reg->iobase_window; 1629 + for (cnt = 0; cnt < 16; cnt++) 1630 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1631 + 1632 + WRT_REG_DWORD(&reg->iobase_addr, 0xB0E0); 1633 + dmp_reg = &reg->iobase_window; 1634 + for (cnt = 0; cnt < sizeof(fw->aseq_1_reg) / 4; cnt++) 1635 + fw->aseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1636 + 1637 + WRT_REG_DWORD(&reg->iobase_addr, 0xB0F0); 1638 + dmp_reg = &reg->iobase_window; 1639 + for (cnt = 0; cnt < sizeof(fw->aseq_2_reg) / 4; cnt++) 1640 + fw->aseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1641 + 1642 + /* Command DMA registers. */ 1643 + WRT_REG_DWORD(&reg->iobase_addr, 0x7100); 1644 + dmp_reg = &reg->iobase_window; 1645 + for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) 1646 + fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1647 + 1648 + /* Queues. */ 1649 + iter_reg = fw->req0_dma_reg; 1650 + WRT_REG_DWORD(&reg->iobase_addr, 0x7200); 1651 + dmp_reg = &reg->iobase_window; 1652 + for (cnt = 0; cnt < 8; cnt++) 1653 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1654 + 1655 + dmp_reg = &reg->iobase_q; 1656 + for (cnt = 0; cnt < 7; cnt++) 1657 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1658 + 1659 + iter_reg = fw->resp0_dma_reg; 1660 + WRT_REG_DWORD(&reg->iobase_addr, 0x7300); 1661 + dmp_reg = &reg->iobase_window; 1662 + for (cnt = 0; cnt < 8; cnt++) 1663 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1664 + 1665 + dmp_reg = &reg->iobase_q; 1666 + for (cnt = 0; cnt < 7; cnt++) 1667 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1668 + 1669 + iter_reg = fw->req1_dma_reg; 1670 + WRT_REG_DWORD(&reg->iobase_addr, 0x7400); 1671 + dmp_reg = &reg->iobase_window; 1672 + for (cnt = 0; cnt < 8; cnt++) 1673 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1674 + 1675 + dmp_reg = &reg->iobase_q; 1676 + for (cnt = 0; cnt < 7; cnt++) 1677 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1678 + 1679 + /* Transmit DMA registers. */ 1680 + iter_reg = fw->xmt0_dma_reg; 1681 + WRT_REG_DWORD(&reg->iobase_addr, 0x7600); 1682 + dmp_reg = &reg->iobase_window; 1683 + for (cnt = 0; cnt < 16; cnt++) 1684 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1685 + 1686 + WRT_REG_DWORD(&reg->iobase_addr, 0x7610); 1687 + dmp_reg = &reg->iobase_window; 1688 + for (cnt = 0; cnt < 16; cnt++) 1689 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1690 + 1691 + iter_reg = fw->xmt1_dma_reg; 1692 + WRT_REG_DWORD(&reg->iobase_addr, 0x7620); 1693 + dmp_reg = &reg->iobase_window; 1694 + for (cnt = 0; cnt < 16; cnt++) 1695 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1696 + 1697 + WRT_REG_DWORD(&reg->iobase_addr, 0x7630); 1698 + dmp_reg = &reg->iobase_window; 1699 + for (cnt = 0; cnt < 16; cnt++) 1700 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1701 + 1702 + iter_reg = fw->xmt2_dma_reg; 1703 + WRT_REG_DWORD(&reg->iobase_addr, 0x7640); 1704 + dmp_reg = &reg->iobase_window; 1705 + for (cnt = 0; cnt < 16; cnt++) 1706 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1707 + 1708 + WRT_REG_DWORD(&reg->iobase_addr, 0x7650); 1709 + dmp_reg = &reg->iobase_window; 1710 + for (cnt = 0; cnt < 16; cnt++) 1711 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1712 + 1713 + iter_reg = fw->xmt3_dma_reg; 1714 + WRT_REG_DWORD(&reg->iobase_addr, 0x7660); 1715 + dmp_reg = &reg->iobase_window; 1716 + for (cnt = 0; cnt < 16; cnt++) 1717 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1718 + 1719 + WRT_REG_DWORD(&reg->iobase_addr, 0x7670); 1720 + dmp_reg = &reg->iobase_window; 1721 + for (cnt = 0; cnt < 16; cnt++) 1722 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1723 + 1724 + iter_reg = fw->xmt4_dma_reg; 1725 + WRT_REG_DWORD(&reg->iobase_addr, 0x7680); 1726 + dmp_reg = &reg->iobase_window; 1727 + for (cnt = 0; cnt < 16; cnt++) 1728 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1729 + 1730 + WRT_REG_DWORD(&reg->iobase_addr, 0x7690); 1731 + dmp_reg = &reg->iobase_window; 1732 + for (cnt = 0; cnt < 16; cnt++) 1733 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1734 + 1735 + WRT_REG_DWORD(&reg->iobase_addr, 0x76A0); 1736 + dmp_reg = &reg->iobase_window; 1737 + for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) 1738 + fw->xmt_data_dma_reg[cnt] = 1739 + htonl(RD_REG_DWORD(dmp_reg++)); 1740 + 1741 + /* Receive DMA registers. */ 1742 + iter_reg = fw->rcvt0_data_dma_reg; 1743 + WRT_REG_DWORD(&reg->iobase_addr, 0x7700); 1744 + dmp_reg = &reg->iobase_window; 1745 + for (cnt = 0; cnt < 16; cnt++) 1746 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1747 + 1748 + WRT_REG_DWORD(&reg->iobase_addr, 0x7710); 1749 + dmp_reg = &reg->iobase_window; 1750 + for (cnt = 0; cnt < 16; cnt++) 1751 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1752 + 1753 + iter_reg = fw->rcvt1_data_dma_reg; 1754 + WRT_REG_DWORD(&reg->iobase_addr, 0x7720); 1755 + dmp_reg = &reg->iobase_window; 1756 + for (cnt = 0; cnt < 16; cnt++) 1757 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1758 + 1759 + WRT_REG_DWORD(&reg->iobase_addr, 0x7730); 1760 + dmp_reg = &reg->iobase_window; 1761 + for (cnt = 0; cnt < 16; cnt++) 1762 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1763 + 1764 + /* RISC registers. */ 1765 + iter_reg = fw->risc_gp_reg; 1766 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F00); 1767 + dmp_reg = &reg->iobase_window; 1768 + for (cnt = 0; cnt < 16; cnt++) 1769 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1770 + 1771 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F10); 1772 + dmp_reg = &reg->iobase_window; 1773 + for (cnt = 0; cnt < 16; cnt++) 1774 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1775 + 1776 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F20); 1777 + dmp_reg = &reg->iobase_window; 1778 + for (cnt = 0; cnt < 16; cnt++) 1779 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1780 + 1781 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F30); 1782 + dmp_reg = &reg->iobase_window; 1783 + for (cnt = 0; cnt < 16; cnt++) 1784 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1785 + 1786 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F40); 1787 + dmp_reg = &reg->iobase_window; 1788 + for (cnt = 0; cnt < 16; cnt++) 1789 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1790 + 1791 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F50); 1792 + dmp_reg = &reg->iobase_window; 1793 + for (cnt = 0; cnt < 16; cnt++) 1794 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1795 + 1796 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F60); 1797 + dmp_reg = &reg->iobase_window; 1798 + for (cnt = 0; cnt < 16; cnt++) 1799 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1800 + 1801 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 1802 + dmp_reg = &reg->iobase_window; 1803 + for (cnt = 0; cnt < 16; cnt++) 1804 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1805 + 1806 + /* Local memory controller registers. */ 1807 + iter_reg = fw->lmc_reg; 1808 + WRT_REG_DWORD(&reg->iobase_addr, 0x3000); 1809 + dmp_reg = &reg->iobase_window; 1810 + for (cnt = 0; cnt < 16; cnt++) 1811 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1812 + 1813 + WRT_REG_DWORD(&reg->iobase_addr, 0x3010); 1814 + dmp_reg = &reg->iobase_window; 1815 + for (cnt = 0; cnt < 16; cnt++) 1816 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1817 + 1818 + WRT_REG_DWORD(&reg->iobase_addr, 0x3020); 1819 + dmp_reg = &reg->iobase_window; 1820 + for (cnt = 0; cnt < 16; cnt++) 1821 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1822 + 1823 + WRT_REG_DWORD(&reg->iobase_addr, 0x3030); 1824 + dmp_reg = &reg->iobase_window; 1825 + for (cnt = 0; cnt < 16; cnt++) 1826 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1827 + 1828 + WRT_REG_DWORD(&reg->iobase_addr, 0x3040); 1829 + dmp_reg = &reg->iobase_window; 1830 + for (cnt = 0; cnt < 16; cnt++) 1831 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1832 + 1833 + WRT_REG_DWORD(&reg->iobase_addr, 0x3050); 1834 + dmp_reg = &reg->iobase_window; 1835 + for (cnt = 0; cnt < 16; cnt++) 1836 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1837 + 1838 + WRT_REG_DWORD(&reg->iobase_addr, 0x3060); 1839 + dmp_reg = &reg->iobase_window; 1840 + for (cnt = 0; cnt < 16; cnt++) 1841 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1842 + 1843 + WRT_REG_DWORD(&reg->iobase_addr, 0x3070); 1844 + dmp_reg = &reg->iobase_window; 1845 + for (cnt = 0; cnt < 16; cnt++) 1846 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1847 + 1848 + /* Fibre Protocol Module registers. */ 1849 + iter_reg = fw->fpm_hdw_reg; 1850 + WRT_REG_DWORD(&reg->iobase_addr, 0x4000); 1851 + dmp_reg = &reg->iobase_window; 1852 + for (cnt = 0; cnt < 16; cnt++) 1853 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1854 + 1855 + WRT_REG_DWORD(&reg->iobase_addr, 0x4010); 1856 + dmp_reg = &reg->iobase_window; 1857 + for (cnt = 0; cnt < 16; cnt++) 1858 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1859 + 1860 + WRT_REG_DWORD(&reg->iobase_addr, 0x4020); 1861 + dmp_reg = &reg->iobase_window; 1862 + for (cnt = 0; cnt < 16; cnt++) 1863 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1864 + 1865 + WRT_REG_DWORD(&reg->iobase_addr, 0x4030); 1866 + dmp_reg = &reg->iobase_window; 1867 + for (cnt = 0; cnt < 16; cnt++) 1868 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1869 + 1870 + WRT_REG_DWORD(&reg->iobase_addr, 0x4040); 1871 + dmp_reg = &reg->iobase_window; 1872 + for (cnt = 0; cnt < 16; cnt++) 1873 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1874 + 1875 + WRT_REG_DWORD(&reg->iobase_addr, 0x4050); 1876 + dmp_reg = &reg->iobase_window; 1877 + for (cnt = 0; cnt < 16; cnt++) 1878 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1879 + 1880 + WRT_REG_DWORD(&reg->iobase_addr, 0x4060); 1881 + dmp_reg = &reg->iobase_window; 1882 + for (cnt = 0; cnt < 16; cnt++) 1883 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1884 + 1885 + WRT_REG_DWORD(&reg->iobase_addr, 0x4070); 1886 + dmp_reg = &reg->iobase_window; 1887 + for (cnt = 0; cnt < 16; cnt++) 1888 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1889 + 1890 + WRT_REG_DWORD(&reg->iobase_addr, 0x4080); 1891 + dmp_reg = &reg->iobase_window; 1892 + for (cnt = 0; cnt < 16; cnt++) 1893 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1894 + 1895 + WRT_REG_DWORD(&reg->iobase_addr, 0x4090); 1896 + dmp_reg = &reg->iobase_window; 1897 + for (cnt = 0; cnt < 16; cnt++) 1898 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1899 + 1900 + WRT_REG_DWORD(&reg->iobase_addr, 0x40A0); 1901 + dmp_reg = &reg->iobase_window; 1902 + for (cnt = 0; cnt < 16; cnt++) 1903 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1904 + 1905 + WRT_REG_DWORD(&reg->iobase_addr, 0x40B0); 1906 + dmp_reg = &reg->iobase_window; 1907 + for (cnt = 0; cnt < 16; cnt++) 1908 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1909 + 1910 + /* Frame Buffer registers. */ 1911 + iter_reg = fw->fb_hdw_reg; 1912 + WRT_REG_DWORD(&reg->iobase_addr, 0x6000); 1913 + dmp_reg = &reg->iobase_window; 1914 + for (cnt = 0; cnt < 16; cnt++) 1915 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1916 + 1917 + WRT_REG_DWORD(&reg->iobase_addr, 0x6010); 1918 + dmp_reg = &reg->iobase_window; 1919 + for (cnt = 0; cnt < 16; cnt++) 1920 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1921 + 1922 + WRT_REG_DWORD(&reg->iobase_addr, 0x6020); 1923 + dmp_reg = &reg->iobase_window; 1924 + for (cnt = 0; cnt < 16; cnt++) 1925 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1926 + 1927 + WRT_REG_DWORD(&reg->iobase_addr, 0x6030); 1928 + dmp_reg = &reg->iobase_window; 1929 + for (cnt = 0; cnt < 16; cnt++) 1930 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1931 + 1932 + WRT_REG_DWORD(&reg->iobase_addr, 0x6040); 1933 + dmp_reg = &reg->iobase_window; 1934 + for (cnt = 0; cnt < 16; cnt++) 1935 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1936 + 1937 + WRT_REG_DWORD(&reg->iobase_addr, 0x6100); 1938 + dmp_reg = &reg->iobase_window; 1939 + for (cnt = 0; cnt < 16; cnt++) 1940 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1941 + 1942 + WRT_REG_DWORD(&reg->iobase_addr, 0x6130); 1943 + dmp_reg = &reg->iobase_window; 1944 + for (cnt = 0; cnt < 16; cnt++) 1945 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1946 + 1947 + WRT_REG_DWORD(&reg->iobase_addr, 0x6150); 1948 + dmp_reg = &reg->iobase_window; 1949 + for (cnt = 0; cnt < 16; cnt++) 1950 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1951 + 1952 + WRT_REG_DWORD(&reg->iobase_addr, 0x6170); 1953 + dmp_reg = &reg->iobase_window; 1954 + for (cnt = 0; cnt < 16; cnt++) 1955 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1956 + 1957 + WRT_REG_DWORD(&reg->iobase_addr, 0x6190); 1958 + dmp_reg = &reg->iobase_window; 1959 + for (cnt = 0; cnt < 16; cnt++) 1960 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1961 + 1962 + WRT_REG_DWORD(&reg->iobase_addr, 0x61B0); 1963 + dmp_reg = &reg->iobase_window; 1964 + for (cnt = 0; cnt < 16; cnt++) 1965 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1966 + 1967 + WRT_REG_DWORD(&reg->iobase_addr, 0x6F00); 1968 + dmp_reg = &reg->iobase_window; 1969 + for (cnt = 0; cnt < 16; cnt++) 1970 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1971 + 1972 + /* Reset RISC. */ 1973 + WRT_REG_DWORD(&reg->ctrl_status, 1974 + CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 1975 + for (cnt = 0; cnt < 30000; cnt++) { 1976 + if ((RD_REG_DWORD(&reg->ctrl_status) & 1977 + CSRX_DMA_ACTIVE) == 0) 1978 + break; 1979 + 1980 + udelay(10); 1981 + } 1982 + 1983 + WRT_REG_DWORD(&reg->ctrl_status, 1984 + CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 1985 + pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 1986 + 1987 + udelay(100); 1988 + /* Wait for firmware to complete NVRAM accesses. */ 1989 + mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1990 + for (cnt = 10000 ; cnt && mb0; cnt--) { 1991 + udelay(5); 1992 + mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1993 + barrier(); 1994 + } 1995 + 1996 + /* Wait for soft-reset to complete. */ 1997 + for (cnt = 0; cnt < 30000; cnt++) { 1998 + if ((RD_REG_DWORD(&reg->ctrl_status) & 1999 + CSRX_ISP_SOFT_RESET) == 0) 2000 + break; 2001 + 2002 + udelay(10); 2003 + } 2004 + WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET); 2005 + RD_REG_DWORD(&reg->hccr); /* PCI Posting. */ 2006 + } 2007 + 2008 + for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 && 2009 + rval == QLA_SUCCESS; cnt--) { 2010 + if (cnt) 2011 + udelay(100); 2012 + else 2013 + rval = QLA_FUNCTION_TIMEOUT; 2014 + } 2015 + 2016 + if (rval == QLA_SUCCESS) 2017 + rval = qla2xxx_dump_memory(ha, fw->code_ram, 2018 + sizeof(fw->code_ram), fw->ext_mem, &nxt); 2019 + 2020 + if (rval == QLA_SUCCESS) { 2021 + nxt = qla2xxx_copy_queues(ha, nxt); 2022 + if (ha->eft) 2023 + memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size)); 2024 + } 2025 + 2026 + if (rval != QLA_SUCCESS) { 2027 + qla_printk(KERN_WARNING, ha, 2028 + "Failed to dump firmware (%x)!!!\n", rval); 2029 + ha->fw_dumped = 0; 2030 + 2031 + } else { 2032 + qla_printk(KERN_INFO, ha, 2033 + "Firmware dump saved to temp buffer (%ld/%p).\n", 2034 + ha->host_no, ha->fw_dump); 2035 + ha->fw_dumped = 1; 2036 + } 2037 + 2038 + qla25xx_fw_dump_failed: 1339 2039 if (!hardware_locked) 1340 2040 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1341 2041 }

+38

drivers/scsi/qla2xxx/qla_dbg.h

··· 213 213 uint32_t ext_mem[1]; 214 214 }; 215 215 216 + struct qla25xx_fw_dump { 217 + uint32_t host_status; 218 + uint32_t host_reg[32]; 219 + uint32_t shadow_reg[11]; 220 + uint32_t risc_io_reg; 221 + uint16_t mailbox_reg[32]; 222 + uint32_t xseq_gp_reg[128]; 223 + uint32_t xseq_0_reg[48]; 224 + uint32_t xseq_1_reg[16]; 225 + uint32_t rseq_gp_reg[128]; 226 + uint32_t rseq_0_reg[32]; 227 + uint32_t rseq_1_reg[16]; 228 + uint32_t rseq_2_reg[16]; 229 + uint32_t aseq_gp_reg[128]; 230 + uint32_t aseq_0_reg[32]; 231 + uint32_t aseq_1_reg[16]; 232 + uint32_t aseq_2_reg[16]; 233 + uint32_t cmd_dma_reg[16]; 234 + uint32_t req0_dma_reg[15]; 235 + uint32_t resp0_dma_reg[15]; 236 + uint32_t req1_dma_reg[15]; 237 + uint32_t xmt0_dma_reg[32]; 238 + uint32_t xmt1_dma_reg[32]; 239 + uint32_t xmt2_dma_reg[32]; 240 + uint32_t xmt3_dma_reg[32]; 241 + uint32_t xmt4_dma_reg[32]; 242 + uint32_t xmt_data_dma_reg[16]; 243 + uint32_t rcvt0_data_dma_reg[32]; 244 + uint32_t rcvt1_data_dma_reg[32]; 245 + uint32_t risc_gp_reg[128]; 246 + uint32_t lmc_reg[128]; 247 + uint32_t fpm_hdw_reg[192]; 248 + uint32_t fb_hdw_reg[192]; 249 + uint32_t code_ram[0x2000]; 250 + uint32_t ext_mem[1]; 251 + }; 252 + 216 253 #define EFT_NUM_BUFFERS 4 217 254 #define EFT_BYTES_PER_BUFFER 0x4000 218 255 #define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS)) ··· 283 246 struct qla2100_fw_dump isp21; 284 247 struct qla2300_fw_dump isp23; 285 248 struct qla24xx_fw_dump isp24; 249 + struct qla25xx_fw_dump isp25; 286 250 } isp; 287 251 };

+7 -1

drivers/scsi/qla2xxx/qla_def.h

··· 2209 2209 #define SWITCH_FOUND BIT_3 2210 2210 #define DFLG_NO_CABLE BIT_4 2211 2211 2212 + #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 2212 2213 uint32_t device_type; 2213 2214 #define DT_ISP2100 BIT_0 2214 2215 #define DT_ISP2200 BIT_1 ··· 2222 2221 #define DT_ISP2432 BIT_8 2223 2222 #define DT_ISP5422 BIT_9 2224 2223 #define DT_ISP5432 BIT_10 2225 - #define DT_ISP_LAST (DT_ISP5432 << 1) 2224 + #define DT_ISP2532 BIT_11 2225 + #define DT_ISP_LAST (DT_ISP2532 << 1) 2226 2226 2227 2227 #define DT_IIDMA BIT_26 2228 2228 #define DT_FWI2 BIT_27 ··· 2244 2242 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 2245 2243 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 2246 2244 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 2245 + #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 2247 2246 2248 2247 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 2249 2248 IS_QLA6312(ha) || IS_QLA6322(ha)) 2250 2249 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 2251 2250 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 2251 + #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 2252 2252 2253 2253 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 2254 2254 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) ··· 2314 2310 #define PORT_SPEED_1GB 0x00 2315 2311 #define PORT_SPEED_2GB 0x01 2316 2312 #define PORT_SPEED_4GB 0x03 2313 + #define PORT_SPEED_8GB 0x04 2317 2314 uint16_t link_data_rate; /* F/W operating speed */ 2318 2315 2319 2316 uint8_t current_topology; ··· 2581 2576 #define OPTROM_SIZE_2300 0x20000 2582 2577 #define OPTROM_SIZE_2322 0x100000 2583 2578 #define OPTROM_SIZE_24XX 0x100000 2579 + #define OPTROM_SIZE_25XX 0x200000 2584 2580 2585 2581 #include "qla_gbl.h" 2586 2582 #include "qla_dbg.h"

+33 -3

drivers/scsi/qla2xxx/qla_fw.h

··· 8 8 #define __QLA_FW_H 9 9 10 10 #define MBS_CHECKSUM_ERROR 0x4010 11 + #define MBS_INVALID_PRODUCT_KEY 0x4020 11 12 12 13 /* 13 14 * Firmware Options. 14 15 */ 15 16 #define FO1_ENABLE_PUREX BIT_10 16 17 #define FO1_DISABLE_LED_CTRL BIT_6 18 + #define FO1_ENABLE_8016 BIT_0 17 19 #define FO2_ENABLE_SEL_CLASS2 BIT_5 18 20 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14 21 + #define FO3_HOLD_STS_IOCB BIT_12 19 22 20 23 /* 21 24 * Port Database structure definition for ISP 24xx. ··· 344 341 * BIT 10 = Reserved 345 342 * BIT 11 = Enable FC-SP Security 346 343 * BIT 12 = FC Tape Enable 347 - * BIT 13-31 = Reserved 344 + * BIT 13 = Reserved 345 + * BIT 14 = Enable Target PRLI Control 346 + * BIT 15-31 = Reserved 348 347 */ 349 348 uint32_t firmware_options_2; 350 349 ··· 368 363 * BIT 13 = Data Rate bit 0 369 364 * BIT 14 = Data Rate bit 1 370 365 * BIT 15 = Data Rate bit 2 371 - * BIT 16-31 = Reserved 366 + * BIT 16 = Enable 75 ohm Termination Select 367 + * BIT 17-31 = Reserved 372 368 */ 373 369 uint32_t firmware_options_3; 374 370 ··· 441 435 #define TMF_LUN_RESET BIT_12 442 436 #define TMF_CLEAR_TASK_SET BIT_10 443 437 #define TMF_ABORT_TASK_SET BIT_9 438 + #define TMF_DSD_LIST_ENABLE BIT_2 444 439 #define TMF_READ_DATA BIT_1 445 440 #define TMF_WRITE_DATA BIT_0 446 441 ··· 596 589 #define EST_SOFI3 (1 << 4) 597 590 #define EST_SOFI2 (3 << 4) 598 591 599 - uint32_t rx_xchg_address[2]; /* Receive exchange address. */ 592 + uint32_t rx_xchg_address; /* Receive exchange address. */ 600 593 uint16_t rx_dsd_count; 601 594 602 595 uint8_t opcode; ··· 657 650 658 651 uint16_t control_flags; /* Control flags. */ 659 652 /* Modifiers. */ 653 + #define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */ 660 654 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ 661 655 #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ 662 656 #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ ··· 787 779 #define FA_RISC_CODE_ADDR 0x20000 788 780 #define FA_RISC_CODE_SEGMENTS 2 789 781 782 + #define FA_FW_AREA_ADDR 0x40000 783 + #define FA_VPD_NVRAM_ADDR 0x48000 784 + #define FA_FEATURE_ADDR 0x4C000 785 + #define FA_FLASH_DESCR_ADDR 0x50000 786 + #define FA_HW_EVENT_ADDR 0x54000 787 + #define FA_BOOT_LOG_ADDR 0x58000 788 + #define FA_FW_DUMP0_ADDR 0x60000 789 + #define FA_FW_DUMP1_ADDR 0x70000 790 + 790 791 uint32_t flash_data; /* Flash/NVRAM BIOS data. */ 791 792 792 793 uint32_t ctrl_status; /* Control/Status. */ ··· 876 859 #define HCCRX_CLR_RISC_INT 0xA0000000 877 860 878 861 uint32_t gpiod; /* GPIO Data register. */ 862 + 879 863 /* LED update mask. */ 880 864 #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) 881 865 /* Data update mask. */ 882 866 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) 867 + /* Data update mask. */ 868 + #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 883 869 /* LED control mask. */ 884 870 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) 885 871 /* LED bit values. Color names as ··· 897 877 uint32_t gpioe; /* GPIO Enable register. */ 898 878 /* Enable update mask. */ 899 879 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) 880 + /* Enable update mask. */ 881 + #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 900 882 /* Enable. */ 901 883 #define GPEX_ENABLE (BIT_1|BIT_0) 902 884 ··· 938 916 uint16_t mailbox29; 939 917 uint16_t mailbox30; 940 918 uint16_t mailbox31; 919 + 920 + uint32_t iobase_window; 921 + uint32_t unused_4[8]; /* Gap. */ 922 + uint32_t iobase_q; 923 + uint32_t unused_5[2]; /* Gap. */ 924 + uint32_t iobase_select; 925 + uint32_t unused_6[2]; /* Gap. */ 926 + uint32_t iobase_sdata; 941 927 }; 942 928 943 929 /* MID Support ***************************************************************/

+6

drivers/scsi/qla2xxx/qla_gbl.h

··· 17 17 extern int qla2100_pci_config(struct scsi_qla_host *); 18 18 extern int qla2300_pci_config(struct scsi_qla_host *); 19 19 extern int qla24xx_pci_config(scsi_qla_host_t *); 20 + extern int qla25xx_pci_config(scsi_qla_host_t *); 20 21 extern void qla2x00_reset_chip(struct scsi_qla_host *); 21 22 extern void qla24xx_reset_chip(struct scsi_qla_host *); 22 23 extern int qla2x00_chip_diag(struct scsi_qla_host *); ··· 282 281 uint32_t); 283 282 extern int qla24xx_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t, 284 283 uint32_t); 284 + extern uint8_t *qla25xx_read_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t, 285 + uint32_t); 286 + extern int qla25xx_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t, 287 + uint32_t); 285 288 286 289 extern int qla2x00_beacon_on(struct scsi_qla_host *); 287 290 extern int qla2x00_beacon_off(struct scsi_qla_host *); ··· 312 307 extern void qla2100_fw_dump(scsi_qla_host_t *, int); 313 308 extern void qla2300_fw_dump(scsi_qla_host_t *, int); 314 309 extern void qla24xx_fw_dump(scsi_qla_host_t *, int); 310 + extern void qla25xx_fw_dump(scsi_qla_host_t *, int); 315 311 extern void qla2x00_dump_regs(scsi_qla_host_t *); 316 312 extern void qla2x00_dump_buffer(uint8_t *, uint32_t); 317 313 extern void qla2x00_print_scsi_cmd(struct scsi_cmnd *);

+9 -1

drivers/scsi/qla2xxx/qla_gs.c

··· 1532 1532 eiter = (struct ct_fdmi_port_attr *) (entries + size); 1533 1533 eiter->type = __constant_cpu_to_be16(FDMI_PORT_SUPPORT_SPEED); 1534 1534 eiter->len = __constant_cpu_to_be16(4 + 4); 1535 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 1535 + if (IS_QLA25XX(ha)) 1536 + eiter->a.sup_speed = __constant_cpu_to_be32( 1537 + FDMI_PORT_SPEED_1GB|FDMI_PORT_SPEED_2GB| 1538 + FDMI_PORT_SPEED_4GB|FDMI_PORT_SPEED_8GB); 1539 + else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 1536 1540 eiter->a.sup_speed = __constant_cpu_to_be32( 1537 1541 FDMI_PORT_SPEED_1GB|FDMI_PORT_SPEED_2GB| 1538 1542 FDMI_PORT_SPEED_4GB); ··· 1567 1563 case PORT_SPEED_4GB: 1568 1564 eiter->a.cur_speed = 1569 1565 __constant_cpu_to_be32(FDMI_PORT_SPEED_4GB); 1566 + break; 1567 + case PORT_SPEED_8GB: 1568 + eiter->a.cur_speed = 1569 + __constant_cpu_to_be32(FDMI_PORT_SPEED_8GB); 1570 1570 break; 1571 1571 default: 1572 1572 eiter->a.cur_speed =

+37 -1

drivers/scsi/qla2xxx/qla_init.c

··· 287 287 } 288 288 289 289 /** 290 + * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. 291 + * @ha: HA context 292 + * 293 + * Returns 0 on success. 294 + */ 295 + int 296 + qla25xx_pci_config(scsi_qla_host_t *ha) 297 + { 298 + uint16_t w; 299 + uint32_t d; 300 + 301 + pci_set_master(ha->pdev); 302 + pci_try_set_mwi(ha->pdev); 303 + 304 + pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 305 + w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 306 + w &= ~PCI_COMMAND_INTX_DISABLE; 307 + pci_write_config_word(ha->pdev, PCI_COMMAND, w); 308 + 309 + /* PCIe -- adjust Maximum Read Request Size (2048). */ 310 + if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP)) 311 + pcie_set_readrq(ha->pdev, 2048); 312 + 313 + /* Reset expansion ROM address decode enable */ 314 + pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d); 315 + d &= ~PCI_ROM_ADDRESS_ENABLE; 316 + pci_write_config_dword(ha->pdev, PCI_ROM_ADDRESS, d); 317 + 318 + ha->chip_revision = ha->pdev->revision; 319 + 320 + return QLA_SUCCESS; 321 + } 322 + 323 + /** 290 324 * qla2x00_isp_firmware() - Choose firmware image. 291 325 * @ha: HA context 292 326 * ··· 751 717 mem_size = (ha->fw_memory_size - 0x11000 + 1) * 752 718 sizeof(uint16_t); 753 719 } else if (IS_FWI2_CAPABLE(ha)) { 754 - fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); 720 + fixed_size = IS_QLA25XX(ha) ? 721 + offsetof(struct qla25xx_fw_dump, ext_mem): 722 + offsetof(struct qla24xx_fw_dump, ext_mem); 755 723 mem_size = (ha->fw_memory_size - 0x100000 + 1) * 756 724 sizeof(uint32_t); 757 725

+5 -5

drivers/scsi/qla2xxx/qla_isr.c

··· 247 247 qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb) 248 248 { 249 249 #define LS_UNKNOWN 2 250 - static char *link_speeds[5] = { "1", "2", "?", "4", "10" }; 250 + static char *link_speeds[5] = { "1", "2", "?", "4", "8" }; 251 251 char *link_speed; 252 252 uint16_t handle_cnt; 253 253 uint16_t cnt; ··· 1758 1758 int ret; 1759 1759 1760 1760 /* If possible, enable MSI-X. */ 1761 - if (!IS_QLA2432(ha)) 1761 + if (!IS_QLA2432(ha) && !IS_QLA2532(ha)) 1762 1762 goto skip_msix; 1763 1763 1764 - if (ha->chip_revision < QLA_MSIX_CHIP_REV_24XX || 1765 - !QLA_MSIX_FW_MODE_1(ha->fw_attributes)) { 1764 + if (IS_QLA2432(ha) && (ha->chip_revision < QLA_MSIX_CHIP_REV_24XX || 1765 + !QLA_MSIX_FW_MODE_1(ha->fw_attributes))) { 1766 1766 DEBUG2(qla_printk(KERN_WARNING, ha, 1767 1767 "MSI-X: Unsupported ISP2432 (0x%X, 0x%X).\n", 1768 1768 ha->chip_revision, ha->fw_attributes)); ··· 1781 1781 "MSI-X: Falling back-to INTa mode -- %d.\n", ret); 1782 1782 skip_msix: 1783 1783 1784 - if (!IS_QLA24XX(ha)) 1784 + if (!IS_QLA24XX(ha) && !IS_QLA2532(ha)) 1785 1785 goto skip_msi; 1786 1786 1787 1787 ret = pci_enable_msi(ha->pdev);

+68 -2

drivers/scsi/qla2xxx/qla_os.c

··· 265 265 strcpy(str, "PCIe ("); 266 266 if (lspeed == 1) 267 267 strcat(str, "2.5Gb/s "); 268 + else if (lspeed == 2) 269 + strcat(str, "5.0Gb/s "); 268 270 else 269 271 strcat(str, "<unknown> "); 270 272 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); ··· 345 343 strcat(str, "[IP] "); 346 344 if (ha->fw_attributes & BIT_2) 347 345 strcat(str, "[Multi-ID] "); 346 + if (ha->fw_attributes & BIT_3) 347 + strcat(str, "[SB-2] "); 348 + if (ha->fw_attributes & BIT_4) 349 + strcat(str, "[T10 CRC] "); 350 + if (ha->fw_attributes & BIT_5) 351 + strcat(str, "[VI] "); 348 352 if (ha->fw_attributes & BIT_13) 349 353 strcat(str, "[Experimental]"); 350 354 return str; ··· 1356 1348 .get_flash_version = qla24xx_get_flash_version, 1357 1349 }; 1358 1350 1351 + static struct isp_operations qla25xx_isp_ops = { 1352 + .pci_config = qla25xx_pci_config, 1353 + .reset_chip = qla24xx_reset_chip, 1354 + .chip_diag = qla24xx_chip_diag, 1355 + .config_rings = qla24xx_config_rings, 1356 + .reset_adapter = qla24xx_reset_adapter, 1357 + .nvram_config = qla24xx_nvram_config, 1358 + .update_fw_options = qla24xx_update_fw_options, 1359 + .load_risc = qla24xx_load_risc, 1360 + .pci_info_str = qla24xx_pci_info_str, 1361 + .fw_version_str = qla24xx_fw_version_str, 1362 + .intr_handler = qla24xx_intr_handler, 1363 + .enable_intrs = qla24xx_enable_intrs, 1364 + .disable_intrs = qla24xx_disable_intrs, 1365 + .abort_command = qla24xx_abort_command, 1366 + .abort_target = qla24xx_abort_target, 1367 + .fabric_login = qla24xx_login_fabric, 1368 + .fabric_logout = qla24xx_fabric_logout, 1369 + .calc_req_entries = NULL, 1370 + .build_iocbs = NULL, 1371 + .prep_ms_iocb = qla24xx_prep_ms_iocb, 1372 + .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1373 + .read_nvram = qla25xx_read_nvram_data, 1374 + .write_nvram = qla25xx_write_nvram_data, 1375 + .fw_dump = qla25xx_fw_dump, 1376 + .beacon_on = qla24xx_beacon_on, 1377 + .beacon_off = qla24xx_beacon_off, 1378 + .beacon_blink = qla24xx_beacon_blink, 1379 + .read_optrom = qla24xx_read_optrom_data, 1380 + .write_optrom = qla24xx_write_optrom_data, 1381 + .get_flash_version = qla24xx_get_flash_version, 1382 + }; 1383 + 1359 1384 static inline void 1360 1385 qla2x00_set_isp_flags(scsi_qla_host_t *ha) 1361 1386 { ··· 1452 1411 case PCI_DEVICE_ID_QLOGIC_ISP5432: 1453 1412 ha->device_type |= DT_ISP5432; 1454 1413 ha->device_type |= DT_FWI2; 1414 + ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1415 + break; 1416 + case PCI_DEVICE_ID_QLOGIC_ISP2532: 1417 + ha->device_type |= DT_ISP2532; 1418 + ha->device_type |= DT_ZIO_SUPPORTED; 1419 + ha->device_type |= DT_FWI2; 1420 + ha->device_type |= DT_IIDMA; 1455 1421 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1456 1422 break; 1457 1423 } ··· 1575 1527 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 1576 1528 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 1577 1529 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 1578 - pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432) 1530 + pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 1531 + pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532) 1579 1532 sht = &qla24xx_driver_template; 1580 1533 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 1581 1534 if (host == NULL) { ··· 1658 1609 ha->gid_list_info_size = 8; 1659 1610 ha->optrom_size = OPTROM_SIZE_24XX; 1660 1611 ha->isp_ops = &qla24xx_isp_ops; 1612 + } else if (IS_QLA25XX(ha)) { 1613 + host->max_id = MAX_TARGETS_2200; 1614 + ha->mbx_count = MAILBOX_REGISTER_COUNT; 1615 + ha->request_q_length = REQUEST_ENTRY_CNT_24XX; 1616 + ha->response_q_length = RESPONSE_ENTRY_CNT_2300; 1617 + ha->last_loop_id = SNS_LAST_LOOP_ID_2300; 1618 + ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 1619 + ha->mgmt_svr_loop_id = 10 + ha->vp_idx; 1620 + ha->gid_list_info_size = 8; 1621 + ha->optrom_size = OPTROM_SIZE_25XX; 1622 + ha->isp_ops = &qla25xx_isp_ops; 1661 1623 } 1662 1624 host->can_queue = ha->request_q_length + 128; 1663 1625 ··· 2725 2665 2726 2666 /* Firmware interface routines. */ 2727 2667 2728 - #define FW_BLOBS 5 2668 + #define FW_BLOBS 6 2729 2669 #define FW_ISP21XX 0 2730 2670 #define FW_ISP22XX 1 2731 2671 #define FW_ISP2300 2 2732 2672 #define FW_ISP2322 3 2733 2673 #define FW_ISP24XX 4 2674 + #define FW_ISP25XX 5 2734 2675 2735 2676 #define FW_FILE_ISP21XX "ql2100_fw.bin" 2736 2677 #define FW_FILE_ISP22XX "ql2200_fw.bin" 2737 2678 #define FW_FILE_ISP2300 "ql2300_fw.bin" 2738 2679 #define FW_FILE_ISP2322 "ql2322_fw.bin" 2739 2680 #define FW_FILE_ISP24XX "ql2400_fw.bin" 2681 + #define FW_FILE_ISP25XX "ql2500_fw.bin" 2740 2682 2741 2683 static DECLARE_MUTEX(qla_fw_lock); 2742 2684 ··· 2748 2686 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 2749 2687 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 2750 2688 { .name = FW_FILE_ISP24XX, }, 2689 + { .name = FW_FILE_ISP25XX, }, 2751 2690 }; 2752 2691 2753 2692 struct fw_blob * ··· 2767 2704 blob = &qla_fw_blobs[FW_ISP2322]; 2768 2705 } else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 2769 2706 blob = &qla_fw_blobs[FW_ISP24XX]; 2707 + } else if (IS_QLA25XX(ha)) { 2708 + blob = &qla_fw_blobs[FW_ISP25XX]; 2770 2709 } 2771 2710 2772 2711 down(&qla_fw_lock); ··· 2812 2747 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 2813 2748 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 2814 2749 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 2750 + { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 2815 2751 { 0 }, 2816 2752 }; 2817 2753 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);

+23

drivers/scsi/qla2xxx/qla_sup.c

··· 766 766 return ret; 767 767 } 768 768 769 + uint8_t * 770 + qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 771 + uint32_t bytes) 772 + { 773 + uint32_t i; 774 + uint32_t *dwptr; 775 + 776 + /* Dword reads to flash. */ 777 + dwptr = (uint32_t *)buf; 778 + for (i = 0; i < bytes >> 2; i++, naddr++) 779 + dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 780 + flash_data_to_access_addr(FA_VPD_NVRAM_ADDR | naddr))); 781 + 782 + return buf; 783 + } 784 + 785 + int 786 + qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 787 + uint32_t bytes) 788 + { 789 + return qla24xx_write_flash_data(ha, (uint32_t *)buf, 790 + FA_VPD_NVRAM_ADDR | naddr, bytes >> 2); 791 + } 769 792 770 793 static inline void 771 794 qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)