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dt-bindings: memory: tegra: Add Tegra234 support
Document the variant of the memory controller and external memory
controllers found on Tegra234 and add some memory client and SMMU
stream ID definitions for use in device tree files.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
+61
+20
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+20
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
···
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- enum:
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- nvidia,tegra186-mc
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- nvidia,tegra194-mc
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- nvidia,tegra234-mc
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reg:
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minItems: 1
···
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- enum:
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- nvidia,tegra186-emc
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- nvidia,tegra194-emc
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- nvidia,tegra234-emc
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reg:
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minItems: 1
···
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reg:
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minItems: 2
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- if:
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properties:
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compatible:
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const: nvidia,tegra234-emc
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then:
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properties:
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reg:
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minItems: 2
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+
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additionalProperties: false
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required:
···
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properties:
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compatible:
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const: nvidia,tegra194-mc
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then:
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properties:
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reg:
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minItems: 3
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+
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- if:
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properties:
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compatible:
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const: nvidia,tegra234-mc
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then:
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properties:
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reg:
+9
include/dt-bindings/clock/tegra234-clock.h
+9
include/dt-bindings/clock/tegra234-clock.h
···
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* @defgroup bpmp_clock_ids Clock ID's
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* @{
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*/
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/**
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* @brief controls the EMC clock frequency.
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* @details Doing a clk_set_rate on this clock will select the
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* appropriate clock source, program the source rate and execute a
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* specific sequence to switch to the new clock source for both memory
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* controllers. This can be used to control the balance between memory
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* throughput and memory controller power.
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*/
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#define TEGRA234_CLK_EMC 31U
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/** @brief output of gate CLK_ENB_FUSE */
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#define TEGRA234_CLK_FUSE 40U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
+32
include/dt-bindings/memory/tegra234-mc.h
+32
include/dt-bindings/memory/tegra234-mc.h
···
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+
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA234_MC_H
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/* special clients */
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#define TEGRA234_SID_INVALID 0x00
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#define TEGRA234_SID_PASSTHROUGH 0x7f
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/* NISO1 stream IDs */
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#define TEGRA234_SID_SDMMC4 0x02
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#define TEGRA234_SID_BPMP 0x10
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/*
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* memory client IDs
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*/
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/* sdmmcd memory read client */
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#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
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/* sdmmcd memory write client */
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#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
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/* BPMP read client */
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#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
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/* BPMP write client */
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#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94
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/* BPMPDMA read client */
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#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
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/* BPMPDMA write client */
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#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
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#endif