Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/i915: Add VM to pin

To verbalize it, one can say, "pin an object into the given address
space." The semantics of pinning remain the same otherwise.

Certain objects will always have to be bound into the global GTT.
Therefore, global GTT is a special case, and keep a special interface
around for it (i915_gem_obj_ggtt_pin).

v2: s/i915_gem_ggtt_pin/i915_gem_obj_ggtt_pin

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

authored by

Ben Widawsky and committed by
Daniel Vetter
c37e2204 fcb4a578

+27 -13
+11
drivers/gpu/drm/i915/i915_drv.h
··· 1710 1710 void i915_gem_vma_destroy(struct i915_vma *vma); 1711 1711 1712 1712 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 1713 + struct i915_address_space *vm, 1713 1714 uint32_t alignment, 1714 1715 bool map_and_fenceable, 1715 1716 bool nonblocking); ··· 1895 1894 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) 1896 1895 { 1897 1896 return i915_gem_obj_size(obj, obj_to_ggtt(obj)); 1897 + } 1898 + 1899 + static inline int __must_check 1900 + i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 1901 + uint32_t alignment, 1902 + bool map_and_fenceable, 1903 + bool nonblocking) 1904 + { 1905 + return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, 1906 + map_and_fenceable, nonblocking); 1898 1907 } 1899 1908 #undef obj_to_ggtt 1900 1909
+5 -4
drivers/gpu/drm/i915/i915_gem.c
··· 592 592 char __user *user_data; 593 593 int page_offset, page_length, ret; 594 594 595 - ret = i915_gem_object_pin(obj, 0, true, true); 595 + ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); 596 596 if (ret) 597 597 goto out; 598 598 ··· 1346 1346 } 1347 1347 1348 1348 /* Now bind it into the GTT if needed */ 1349 - ret = i915_gem_object_pin(obj, 0, true, false); 1349 + ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); 1350 1350 if (ret) 1351 1351 goto unlock; 1352 1352 ··· 3488 3488 * (e.g. libkms for the bootup splash), we have to ensure that we 3489 3489 * always use map_and_fenceable for all scanout buffers. 3490 3490 */ 3491 - ret = i915_gem_object_pin(obj, alignment, true, false); 3491 + ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false); 3492 3492 if (ret) 3493 3493 return ret; 3494 3494 ··· 3631 3631 3632 3632 int 3633 3633 i915_gem_object_pin(struct drm_i915_gem_object *obj, 3634 + struct i915_address_space *vm, 3634 3635 uint32_t alignment, 3635 3636 bool map_and_fenceable, 3636 3637 bool nonblocking) ··· 3721 3720 } 3722 3721 3723 3722 if (obj->user_pin_count == 0) { 3724 - ret = i915_gem_object_pin(obj, args->alignment, true, false); 3723 + ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false); 3725 3724 if (ret) 3726 3725 goto out; 3727 3726 }
+2 -2
drivers/gpu/drm/i915/i915_gem_context.c
··· 214 214 * default context. 215 215 */ 216 216 dev_priv->ring[RCS].default_context = ctx; 217 - ret = i915_gem_object_pin(ctx->obj, CONTEXT_ALIGN, false, false); 217 + ret = i915_gem_obj_ggtt_pin(ctx->obj, CONTEXT_ALIGN, false, false); 218 218 if (ret) { 219 219 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); 220 220 goto err_destroy; ··· 400 400 if (from == to) 401 401 return 0; 402 402 403 - ret = i915_gem_object_pin(to->obj, CONTEXT_ALIGN, false, false); 403 + ret = i915_gem_obj_ggtt_pin(to->obj, CONTEXT_ALIGN, false, false); 404 404 if (ret) 405 405 return ret; 406 406
+3 -1
drivers/gpu/drm/i915/i915_gem_execbuffer.c
··· 409 409 obj->tiling_mode != I915_TILING_NONE; 410 410 need_mappable = need_fence || need_reloc_mappable(obj); 411 411 412 - ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false); 412 + /* FIXME: vm plubming */ 413 + ret = i915_gem_object_pin(obj, &dev_priv->gtt.base, entry->alignment, 414 + need_mappable, false); 413 415 if (ret) 414 416 return ret; 415 417
+1 -1
drivers/gpu/drm/i915/intel_overlay.c
··· 1352 1352 } 1353 1353 overlay->flip_addr = reg_bo->phys_obj->handle->busaddr; 1354 1354 } else { 1355 - ret = i915_gem_object_pin(reg_bo, PAGE_SIZE, true, false); 1355 + ret = i915_gem_obj_ggtt_pin(reg_bo, PAGE_SIZE, true, false); 1356 1356 if (ret) { 1357 1357 DRM_ERROR("failed to pin overlay register bo\n"); 1358 1358 goto out_free_bo;
+1 -1
drivers/gpu/drm/i915/intel_pm.c
··· 2886 2886 return NULL; 2887 2887 } 2888 2888 2889 - ret = i915_gem_object_pin(ctx, 4096, true, false); 2889 + ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false); 2890 2890 if (ret) { 2891 2891 DRM_ERROR("failed to pin power context: %d\n", ret); 2892 2892 goto err_unref;
+4 -4
drivers/gpu/drm/i915/intel_ringbuffer.c
··· 501 501 502 502 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); 503 503 504 - ret = i915_gem_object_pin(obj, 4096, true, false); 504 + ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false); 505 505 if (ret) 506 506 goto err_unref; 507 507 ··· 1224 1224 1225 1225 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); 1226 1226 1227 - ret = i915_gem_object_pin(obj, 4096, true, false); 1227 + ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false); 1228 1228 if (ret != 0) { 1229 1229 goto err_unref; 1230 1230 } ··· 1307 1307 1308 1308 ring->obj = obj; 1309 1309 1310 - ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false); 1310 + ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false); 1311 1311 if (ret) 1312 1312 goto err_unref; 1313 1313 ··· 1828 1828 return -ENOMEM; 1829 1829 } 1830 1830 1831 - ret = i915_gem_object_pin(obj, 0, true, false); 1831 + ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); 1832 1832 if (ret != 0) { 1833 1833 drm_gem_object_unreference(&obj->base); 1834 1834 DRM_ERROR("Failed to ping batch bo\n");