tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'omap-for-v5.3/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes

Fixes for omap variants for v5.3-rc cycle

We have another fix to disable voltage switching for am57xx SDIO as
the bootrom cannot handle all the voltages after a reset that thought
I had already sent a pull request for earlier but forgot. And we also
update dra74x iodelay configuration for mmc3 to use the recommended
values.

Then I noticed we had introduced few new boot warnings with the various
recent ti-sysc changes and wanted to fix those. I also noticed we still
have too many warnings to be able to spot the real ones easily and fixed
up few of those. Sure some of the warnings have been around for a long
time and few of the fixes could have waited for the merge window, but
having more usable dmesg log level output is a valuable.

Other fixes are IO size correction for am335x UARTs that cause issues
for at least FreeBSD using the same device tree file that checks that
the child IO range is not larger than the parent has.

For omap1 ams-delta keyboard we need to fix a irq ack that broke with
all the recent gpio changes.

And there are also few static checker warning fixes for recent am335x
PM changes and ti-sysc driver and one switch fall-though update.

* tag 'omap-for-v5.3/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
soc: ti: pm33xx: Make two symbols static
soc: ti: pm33xx: Fix static checker warnings
ARM: OMAP: dma: Mark expected switch fall-throughs
ARM: dts: Fix incomplete dts data for am3 and am4 mmc
bus: ti-sysc: Simplify cleanup upon failures in sysc_probe()
ARM: OMAP1: ams-delta-fiq: Fix missing irq_ack
ARM: dts: dra74x: Fix iodelay configuration for mmc3
ARM: dts: am335x: Fix UARTs length
ARM: OMAP2+: Fix omap4 errata warning on other SoCs
ARM: dts: Fix incorrect dcan register mapping for am3, am4 and dra7
ARM: dts: Fix flags for gpio7
bus: ti-sysc: Fix using configured sysc mask value
bus: ti-sysc: Fix handling of forced idle
ARM: OMAP2+: Fix missing SYSC_HAS_RESET_STATUS for dra7 epwmss
ARM: dts: am57xx: Disable voltage switching for SD card

Link: https://lore.kernel.org/r/pull-1565844391-332885@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann c372740c ebc52623

+133 -103
+10 -6
arch/arm/boot/dts/am33xx-l4.dtsi
··· 185 185 uart0: serial@0 { 186 186 compatible = "ti,am3352-uart", "ti,omap3-uart"; 187 187 clock-frequency = <48000000>; 188 - reg = <0x0 0x2000>; 188 + reg = <0x0 0x1000>; 189 189 interrupts = <72>; 190 190 status = "disabled"; 191 191 dmas = <&edma 26 0>, <&edma 27 0>; ··· 934 934 uart1: serial@0 { 935 935 compatible = "ti,am3352-uart", "ti,omap3-uart"; 936 936 clock-frequency = <48000000>; 937 - reg = <0x0 0x2000>; 937 + reg = <0x0 0x1000>; 938 938 interrupts = <73>; 939 939 status = "disabled"; 940 940 dmas = <&edma 28 0>, <&edma 29 0>; ··· 966 966 uart2: serial@0 { 967 967 compatible = "ti,am3352-uart", "ti,omap3-uart"; 968 968 clock-frequency = <48000000>; 969 - reg = <0x0 0x2000>; 969 + reg = <0x0 0x1000>; 970 970 interrupts = <74>; 971 971 status = "disabled"; 972 972 dmas = <&edma 30 0>, <&edma 31 0>; ··· 1614 1614 uart3: serial@0 { 1615 1615 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1616 1616 clock-frequency = <48000000>; 1617 - reg = <0x0 0x2000>; 1617 + reg = <0x0 0x1000>; 1618 1618 interrupts = <44>; 1619 1619 status = "disabled"; 1620 1620 }; ··· 1644 1644 uart4: serial@0 { 1645 1645 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1646 1646 clock-frequency = <48000000>; 1647 - reg = <0x0 0x2000>; 1647 + reg = <0x0 0x1000>; 1648 1648 interrupts = <45>; 1649 1649 status = "disabled"; 1650 1650 }; ··· 1674 1674 uart5: serial@0 { 1675 1675 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1676 1676 clock-frequency = <48000000>; 1677 - reg = <0x0 0x2000>; 1677 + reg = <0x0 0x1000>; 1678 1678 interrupts = <46>; 1679 1679 status = "disabled"; 1680 1680 }; ··· 1758 1758 1759 1759 target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ 1760 1760 compatible = "ti,sysc-omap4", "ti,sysc"; 1761 + reg = <0xcc020 0x4>; 1762 + reg-names = "rev"; 1761 1763 ti,hwmods = "d_can0"; 1762 1764 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1763 1765 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, ··· 1782 1780 1783 1781 target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ 1784 1782 compatible = "ti,sysc-omap4", "ti,sysc"; 1783 + reg = <0xd0020 0x4>; 1784 + reg-names = "rev"; 1785 1785 ti,hwmods = "d_can1"; 1786 1786 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1787 1787 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
+26 -6
arch/arm/boot/dts/am33xx.dtsi
··· 234 234 interrupt-names = "edma3_tcerrint"; 235 235 }; 236 236 237 - mmc3: mmc@47810000 { 238 - compatible = "ti,omap4-hsmmc"; 237 + target-module@47810000 { 238 + compatible = "ti,sysc-omap2", "ti,sysc"; 239 239 ti,hwmods = "mmc3"; 240 - ti,needs-special-reset; 241 - interrupts = <29>; 242 - reg = <0x47810000 0x1000>; 243 - status = "disabled"; 240 + reg = <0x478102fc 0x4>, 241 + <0x47810110 0x4>, 242 + <0x47810114 0x4>; 243 + reg-names = "rev", "sysc", "syss"; 244 + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 245 + SYSC_OMAP2_ENAWAKEUP | 246 + SYSC_OMAP2_SOFTRESET | 247 + SYSC_OMAP2_AUTOIDLE)>; 248 + ti,sysc-sidle = <SYSC_IDLE_FORCE>, 249 + <SYSC_IDLE_NO>, 250 + <SYSC_IDLE_SMART>; 251 + ti,syss-mask = <1>; 252 + clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>; 253 + clock-names = "fck"; 254 + #address-cells = <1>; 255 + #size-cells = <1>; 256 + ranges = <0x0 0x47810000 0x1000>; 257 + 258 + mmc3: mmc@0 { 259 + compatible = "ti,omap4-hsmmc"; 260 + ti,needs-special-reset; 261 + interrupts = <29>; 262 + reg = <0x0 0x1000>; 263 + }; 244 264 }; 245 265 246 266 usb: usb@47400000 {
+26 -6
arch/arm/boot/dts/am4372.dtsi
··· 228 228 interrupt-names = "edma3_tcerrint"; 229 229 }; 230 230 231 - mmc3: mmc@47810000 { 232 - compatible = "ti,omap4-hsmmc"; 233 - reg = <0x47810000 0x1000>; 231 + target-module@47810000 { 232 + compatible = "ti,sysc-omap2", "ti,sysc"; 234 233 ti,hwmods = "mmc3"; 235 - ti,needs-special-reset; 236 - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 237 - status = "disabled"; 234 + reg = <0x478102fc 0x4>, 235 + <0x47810110 0x4>, 236 + <0x47810114 0x4>; 237 + reg-names = "rev", "sysc", "syss"; 238 + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 239 + SYSC_OMAP2_ENAWAKEUP | 240 + SYSC_OMAP2_SOFTRESET | 241 + SYSC_OMAP2_AUTOIDLE)>; 242 + ti,sysc-sidle = <SYSC_IDLE_FORCE>, 243 + <SYSC_IDLE_NO>, 244 + <SYSC_IDLE_SMART>; 245 + ti,syss-mask = <1>; 246 + clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>; 247 + clock-names = "fck"; 248 + #address-cells = <1>; 249 + #size-cells = <1>; 250 + ranges = <0x0 0x47810000 0x1000>; 251 + 252 + mmc3: mmc@0 { 253 + compatible = "ti,omap4-hsmmc"; 254 + ti,needs-special-reset; 255 + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 256 + reg = <0x0 0x1000>; 257 + }; 238 258 }; 239 259 240 260 sham: sham@53100000 {
+4
arch/arm/boot/dts/am437x-l4.dtsi
··· 1574 1574 1575 1575 target-module@cc000 { /* 0x481cc000, ap 50 46.0 */ 1576 1576 compatible = "ti,sysc-omap4", "ti,sysc"; 1577 + reg = <0xcc020 0x4>; 1578 + reg-names = "rev"; 1577 1579 ti,hwmods = "d_can0"; 1578 1580 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1579 1581 clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>; ··· 1595 1593 1596 1594 target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */ 1597 1595 compatible = "ti,sysc-omap4", "ti,sysc"; 1596 + reg = <0xd0020 0x4>; 1597 + reg-names = "rev"; 1598 1598 ti,hwmods = "d_can1"; 1599 1599 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1600 1600 clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>;
+1 -6
arch/arm/boot/dts/am571x-idk.dts
··· 175 175 }; 176 176 177 177 &mmc1 { 178 - pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; 178 + pinctrl-names = "default", "hs"; 179 179 pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; 180 180 pinctrl-1 = <&mmc1_pins_hs>; 181 - pinctrl-2 = <&mmc1_pins_sdr12>; 182 - pinctrl-3 = <&mmc1_pins_sdr25>; 183 - pinctrl-4 = <&mmc1_pins_sdr50>; 184 - pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; 185 - pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; 186 181 }; 187 182 188 183 &mmc2 {
+1 -6
arch/arm/boot/dts/am572x-idk.dts
··· 16 16 }; 17 17 18 18 &mmc1 { 19 - pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; 19 + pinctrl-names = "default", "hs"; 20 20 pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; 21 21 pinctrl-1 = <&mmc1_pins_hs>; 22 - pinctrl-2 = <&mmc1_pins_sdr12>; 23 - pinctrl-3 = <&mmc1_pins_sdr25>; 24 - pinctrl-4 = <&mmc1_pins_sdr50>; 25 - pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; 26 - pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; 27 22 }; 28 23 29 24 &mmc2 {
+1 -6
arch/arm/boot/dts/am574x-idk.dts
··· 24 24 }; 25 25 26 26 &mmc1 { 27 - pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; 27 + pinctrl-names = "default", "hs"; 28 28 pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; 29 29 pinctrl-1 = <&mmc1_pins_hs>; 30 - pinctrl-2 = <&mmc1_pins_default>; 31 - pinctrl-3 = <&mmc1_pins_hs>; 32 - pinctrl-4 = <&mmc1_pins_sdr50>; 33 - pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_conf>; 34 - pinctrl-6 = <&mmc1_pins_ddr50 &mmc1_iodelay_sdr104_conf>; 35 30 }; 36 31 37 32 &mmc2 {
+2 -1
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
··· 379 379 }; 380 380 }; 381 381 382 - &gpio7 { 382 + &gpio7_target { 383 383 ti,no-reset-on-init; 384 384 ti,no-idle-on-init; 385 385 }; ··· 430 430 431 431 bus-width = <4>; 432 432 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ 433 + no-1-8-v; 433 434 }; 434 435 435 436 &mmc2 {
+1 -6
arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
··· 16 16 }; 17 17 18 18 &mmc1 { 19 - pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; 19 + pinctrl-names = "default", "hs"; 20 20 pinctrl-0 = <&mmc1_pins_default>; 21 21 pinctrl-1 = <&mmc1_pins_hs>; 22 - pinctrl-2 = <&mmc1_pins_sdr12>; 23 - pinctrl-3 = <&mmc1_pins_sdr25>; 24 - pinctrl-4 = <&mmc1_pins_sdr50>; 25 - pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; 26 - pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; 27 22 vmmc-supply = <&vdd_3v3>; 28 23 vqmmc-supply = <&ldo1_reg>; 29 24 };
+1 -6
arch/arm/boot/dts/am57xx-beagle-x15-revc.dts
··· 16 16 }; 17 17 18 18 &mmc1 { 19 - pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; 19 + pinctrl-names = "default", "hs"; 20 20 pinctrl-0 = <&mmc1_pins_default>; 21 21 pinctrl-1 = <&mmc1_pins_hs>; 22 - pinctrl-2 = <&mmc1_pins_sdr12>; 23 - pinctrl-3 = <&mmc1_pins_sdr25>; 24 - pinctrl-4 = <&mmc1_pins_sdr50>; 25 - pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; 26 - pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; 27 22 vmmc-supply = <&vdd_3v3>; 28 23 vqmmc-supply = <&ldo1_reg>; 29 24 };
+1 -1
arch/arm/boot/dts/dra7-evm.dts
··· 498 498 phy-supply = <&ldousb_reg>; 499 499 }; 500 500 501 - &gpio7 { 501 + &gpio7_target { 502 502 ti,no-reset-on-init; 503 503 ti,no-idle-on-init; 504 504 };
+3 -3
arch/arm/boot/dts/dra7-l4.dtsi
··· 1261 1261 }; 1262 1262 }; 1263 1263 1264 - target-module@51000 { /* 0x48051000, ap 45 2e.0 */ 1264 + gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */ 1265 1265 compatible = "ti,sysc-omap2", "ti,sysc"; 1266 1266 ti,hwmods = "gpio7"; 1267 1267 reg = <0x51000 0x4>, ··· 3025 3025 3026 3026 target-module@80000 { /* 0x48480000, ap 31 16.0 */ 3027 3027 compatible = "ti,sysc-omap4", "ti,sysc"; 3028 - reg = <0x80000 0x4>; 3028 + reg = <0x80020 0x4>; 3029 3029 reg-names = "rev"; 3030 3030 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>; 3031 3031 clock-names = "fck"; ··· 4577 4577 4578 4578 target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */ 4579 4579 compatible = "ti,sysc-omap4", "ti,sysc"; 4580 - reg = <0xc000 0x4>; 4580 + reg = <0xc020 0x4>; 4581 4581 reg-names = "rev"; 4582 4582 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>; 4583 4583 clock-names = "fck";
+25 -25
arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
··· 32 32 * 33 33 * Datamanual Revisions: 34 34 * 35 - * AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016 35 + * AM572x Silicon Revision 2.0: SPRS953F, Revised May 2019 36 36 * AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016 37 37 * 38 38 */ ··· 229 229 230 230 mmc3_pins_default: mmc3_pins_default { 231 231 pinctrl-single,pins = < 232 - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 233 - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 234 - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 235 - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 236 - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 237 - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 232 + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 233 + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 234 + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 235 + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 236 + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 237 + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 238 238 >; 239 239 }; 240 240 241 241 mmc3_pins_hs: mmc3_pins_hs { 242 242 pinctrl-single,pins = < 243 - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 244 - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 245 - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 246 - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 247 - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 248 - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 243 + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 244 + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 245 + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 246 + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 247 + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 248 + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 249 249 >; 250 250 }; 251 251 252 252 mmc3_pins_sdr12: mmc3_pins_sdr12 { 253 253 pinctrl-single,pins = < 254 - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 255 - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 256 - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 257 - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 258 - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 259 - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 254 + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 255 + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 256 + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 257 + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 258 + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 259 + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 260 260 >; 261 261 }; 262 262 263 263 mmc3_pins_sdr25: mmc3_pins_sdr25 { 264 264 pinctrl-single,pins = < 265 - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 266 - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 267 - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 268 - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 269 - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 270 - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 265 + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 266 + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 267 + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 268 + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 269 + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 270 + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 271 271 >; 272 272 }; 273 273
+2 -1
arch/arm/mach-omap1/ams-delta-fiq-handler.S
··· 126 126 orr r11, r11, r13 @ mask all requested interrupts 127 127 str r11, [r12, #OMAP1510_GPIO_INT_MASK] 128 128 129 + str r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack all requested interrupts 130 + 129 131 ands r10, r13, #KEYBRD_CLK_MASK @ extract keyboard status - set? 130 132 beq hksw @ no - try next source 131 133 ··· 135 133 @@@@@@@@@@@@@@@@@@@@@@ 136 134 @ Keyboard clock FIQ mode interrupt handler 137 135 @ r10 now contains KEYBRD_CLK_MASK, use it 138 - str r10, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack the interrupt 139 136 bic r11, r11, r10 @ unmask it 140 137 str r11, [r12, #OMAP1510_GPIO_INT_MASK] 141 138
+1 -3
arch/arm/mach-omap1/ams-delta-fiq.c
··· 70 70 * interrupts default to since commit 80ac93c27441 71 71 * requires interrupt already acked and unmasked. 72 72 */ 73 - if (irq_chip->irq_ack) 74 - irq_chip->irq_ack(d); 75 - if (irq_chip->irq_unmask) 73 + if (!WARN_ON_ONCE(!irq_chip->irq_unmask)) 76 74 irq_chip->irq_unmask(d); 77 75 } 78 76 for (; irq_counter[gpio] < fiq_count; irq_counter[gpio]++)
+3
arch/arm/mach-omap2/omap4-common.c
··· 127 127 struct device_node *np; 128 128 struct gen_pool *sram_pool; 129 129 130 + if (!soc_is_omap44xx() && !soc_is_omap54xx()) 131 + return 0; 132 + 130 133 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu"); 131 134 if (!np) 132 135 pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
+2 -1
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
··· 379 379 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = { 380 380 .rev_offs = 0x0, 381 381 .sysc_offs = 0x4, 382 - .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, 382 + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 383 + SYSC_HAS_RESET_STATUS, 383 384 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 384 385 .sysc_fields = &omap_hwmod_sysc_type2, 385 386 };
+11 -13
drivers/bus/ti-sysc.c
··· 949 949 *best_mode = SYSC_IDLE_SMART_WKUP; 950 950 else if (idlemodes & BIT(SYSC_IDLE_SMART)) 951 951 *best_mode = SYSC_IDLE_SMART; 952 - else if (idlemodes & SYSC_IDLE_FORCE) 952 + else if (idlemodes & BIT(SYSC_IDLE_FORCE)) 953 953 *best_mode = SYSC_IDLE_FORCE; 954 954 else 955 955 return -EINVAL; ··· 1267 1267 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), 1268 1268 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, 1269 1269 0xffff00f0, 0), 1270 - SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0), 1270 + SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0), 1271 + SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0), 1271 1272 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0), 1272 1273 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0), 1273 1274 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0), ··· 1693 1692 if (error) 1694 1693 return 0; 1695 1694 1696 - if (val) 1697 - ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; 1698 - else 1699 - ddata->cfg.sysc_val = ddata->cap->sysc_mask; 1695 + ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; 1700 1696 1701 1697 return 0; 1702 1698 } ··· 2383 2385 2384 2386 error = sysc_init_dts_quirks(ddata); 2385 2387 if (error) 2386 - goto unprepare; 2388 + return error; 2387 2389 2388 2390 error = sysc_map_and_check_registers(ddata); 2389 2391 if (error) 2390 - goto unprepare; 2392 + return error; 2391 2393 2392 2394 error = sysc_init_sysc_mask(ddata); 2393 2395 if (error) 2394 - goto unprepare; 2396 + return error; 2395 2397 2396 2398 error = sysc_init_idlemodes(ddata); 2397 2399 if (error) 2398 - goto unprepare; 2400 + return error; 2399 2401 2400 2402 error = sysc_init_syss_mask(ddata); 2401 2403 if (error) 2402 - goto unprepare; 2404 + return error; 2403 2405 2404 2406 error = sysc_init_pdata(ddata); 2405 2407 if (error) 2406 - goto unprepare; 2408 + return error; 2407 2409 2408 2410 sysc_init_early_quirks(ddata); 2409 2411 ··· 2413 2415 2414 2416 error = sysc_init_resets(ddata); 2415 2417 if (error) 2416 - return error; 2418 + goto unprepare; 2417 2419 2418 2420 error = sysc_init_module(ddata); 2419 2421 if (error)
+12 -7
drivers/soc/ti/pm33xx.c
··· 141 141 } 142 142 143 143 #ifdef CONFIG_SUSPEND 144 - struct wkup_m3_wakeup_src rtc_wake_src(void) 144 + static struct wkup_m3_wakeup_src rtc_wake_src(void) 145 145 { 146 146 u32 i; 147 147 ··· 157 157 return rtc_ext_wakeup; 158 158 } 159 159 160 - int am33xx_rtc_only_idle(unsigned long wfi_flags) 160 + static int am33xx_rtc_only_idle(unsigned long wfi_flags) 161 161 { 162 162 omap_rtc_power_off_program(&omap_rtc->dev); 163 163 am33xx_do_wfi_sram(wfi_flags); ··· 252 252 if (state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) { 253 253 nvmem = devm_nvmem_device_get(&omap_rtc->dev, 254 254 "omap_rtc_scratch0"); 255 - if (nvmem) 255 + if (!IS_ERR(nvmem)) 256 256 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4, 257 257 (void *)&rtc_magic_val); 258 258 rtc_only_idle = 1; ··· 278 278 struct nvmem_device *nvmem; 279 279 280 280 nvmem = devm_nvmem_device_get(&omap_rtc->dev, "omap_rtc_scratch0"); 281 + if (IS_ERR(nvmem)) 282 + return; 283 + 281 284 m3_ipc->ops->finish_low_power(m3_ipc); 282 285 if (rtc_only_idle) { 283 - if (retrigger_irq) 286 + if (retrigger_irq) { 284 287 /* 285 288 * 32 bits of Interrupt Set-Pending correspond to 32 286 289 * 32 interrupts. Compute the bit offset of the ··· 294 291 writel_relaxed(1 << (retrigger_irq & 31), 295 292 gic_dist_base + GIC_INT_SET_PENDING_BASE 296 293 + retrigger_irq / 32 * 4); 297 - nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4, 298 - (void *)&val); 294 + } 295 + 296 + nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4, 297 + (void *)&val); 299 298 } 300 299 301 300 rtc_only_idle = 0; ··· 420 415 421 416 nvmem = devm_nvmem_device_get(&omap_rtc->dev, 422 417 "omap_rtc_scratch0"); 423 - if (nvmem) { 418 + if (!IS_ERR(nvmem)) { 424 419 nvmem_device_read(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 425 420 4, (void *)&rtc_magic_val); 426 421 if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC)