commit c3310e7766ebe7491910715c3161a4f29fa0112e · tjh.dev/kernel

tjh.dev / kernel

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc:
powerpc/ps3: Fix build error on UP
powerpc/cell: Select PCI for IBM_CELL_BLADE AND CELLEB
powerpc: ppc32 needs elf_read_implies_exec()
powerpc/86xx: Add device_type entry to soc for ppc9a
powerpc/44x: Correct memory size calculation for denali-based boards
maintainers: Fix PowerPC 4xx git tree
powerpc: fix for long standing bug noticed by gcc 4.4.0
Revert "powerpc: Add support for early tlbilx opcode"

Linus Torvalds 16 years ago c3310e77 13beadd9

+54 -50

10 changed files

expand all

unified split

MAINTAINERS

arch

powerpc

boot

4xx.c

dts

gef_ppc9a.dts

include

asm

elf.h

mmu.h

ppc-opcode.h

kernel

cputable.c

tlb_nohash_low.S

platforms

cell

Kconfig

ps3

setup.c

+1 -1

MAINTAINERS

··· 3448 3448 M: mporter@kernel.crashing.org 3449 3449 W: http://www.penguinppc.org/ 3450 3450 L: linuxppc-dev@ozlabs.org 3451 - T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc.git 3451 + T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git 3452 3452 S: Maintained 3453 3453 3454 3454 LINUX FOR POWERPC EMBEDDED XILINX VIRTEX

+43 -13

arch/powerpc/boot/4xx.c

··· 158 158 159 159 #define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask)) 160 160 161 + /* 162 + * Some U-Boot versions set the number of chipselects to two 163 + * for Sequoia/Rainier boards while they only have one chipselect 164 + * hardwired. Hardcode the number of chipselects to one 165 + * for sequioa/rainer board models or read the actual value 166 + * from the memory controller register DDR0_10 otherwise. 167 + */ 168 + static inline u32 ibm4xx_denali_get_cs(void) 169 + { 170 + void *devp; 171 + char model[64]; 172 + u32 val, cs; 173 + 174 + devp = finddevice("/"); 175 + if (!devp) 176 + goto read_cs; 177 + 178 + if (getprop(devp, "model", model, sizeof(model)) <= 0) 179 + goto read_cs; 180 + 181 + model[sizeof(model)-1] = 0; 182 + 183 + if (!strcmp(model, "amcc,sequoia") || 184 + !strcmp(model, "amcc,rainier")) 185 + return 1; 186 + 187 + read_cs: 188 + /* get CS value */ 189 + val = SDRAM0_READ(DDR0_10); 190 + 191 + val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT); 192 + cs = 0; 193 + while (val) { 194 + if (val & 0x1) 195 + cs++; 196 + val = val >> 1; 197 + } 198 + return cs; 199 + } 200 + 161 201 void ibm4xx_denali_fixup_memsize(void) 162 202 { 163 203 u32 val, max_cs, max_col, max_row; ··· 213 173 max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT); 214 174 max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT); 215 175 216 - /* get CS value */ 217 - val = SDRAM0_READ(DDR0_10); 218 - 219 - val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT); 220 - cs = 0; 221 - while (val) { 222 - if (val & 0x1) 223 - cs++; 224 - val = val >> 1; 225 - } 226 - 176 + cs = ibm4xx_denali_get_cs(); 227 177 if (!cs) 228 178 fatal("No memory installed\n"); 229 179 if (cs > max_cs) ··· 223 193 val = SDRAM0_READ(DDR0_14); 224 194 225 195 if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT)) 226 - dpath = 8; /* 64 bits */ 227 - else 228 196 dpath = 4; /* 32 bits */ 197 + else 198 + dpath = 8; /* 64 bits */ 229 199 230 200 /* get address pins (rows) */ 231 201 val = SDRAM0_READ(DDR0_42);

arch/powerpc/boot/dts/gef_ppc9a.dts

··· 161 161 #address-cells = <1>; 162 162 #size-cells = <1>; 163 163 #interrupt-cells = <2>; 164 + device_type = "soc"; 164 165 compatible = "fsl,mpc8641-soc", "simple-bus"; 165 166 ranges = <0x0 0xfef00000 0x00100000>; 166 167 reg = <0xfef00000 0x100000>; // CCSRBAR 1M

arch/powerpc/include/asm/elf.h

··· 260 260 #else 261 261 # define SET_PERSONALITY(ex) \ 262 262 set_personality(PER_LINUX | (current->personality & (~PER_MASK))) 263 + # define elf_read_implies_exec(ex, exec_stk) (exec_stk != EXSTACK_DISABLE_X) 263 264 #endif /* __powerpc64__ */ 264 265 265 266 extern int dcache_bsize;

-6

arch/powerpc/include/asm/mmu.h

··· 52 52 */ 53 53 #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) 54 54 55 - /* This indicates that the processor uses the wrong opcode for tlbilx 56 - * instructions. During the ISA 2.06 development the opcode for tlbilx 57 - * changed and some early implementations used to old opcode 58 - */ 59 - #define MMU_FTR_TLBILX_EARLY_OPCODE ASM_CONST(0x00400000) 60 - 61 55 #ifndef __ASSEMBLY__ 62 56 #include <asm/cputable.h> 63 57

+1 -10

arch/powerpc/include/asm/ppc-opcode.h

··· 44 44 #define PPC_INST_STSWI 0x7c0005aa 45 45 #define PPC_INST_STSWX 0x7c00052a 46 46 #define PPC_INST_TLBILX 0x7c000024 47 - #define PPC_INST_TLBILX_EARLY 0x7c000626 48 47 #define PPC_INST_WAIT 0x7c00007c 49 48 50 49 /* macros to insert fields into opcodes */ ··· 63 64 #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) 64 65 #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) 65 66 #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ 66 - __PPC_T_TLB(t) | \ 67 - __PPC_RA(a) | __PPC_RB(b)) 67 + __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b)) 68 68 #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) 69 69 #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) 70 70 #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) 71 - 72 - #define PPC_TLBILX_EARLY(t, a, b) stringify_in_c(.long PPC_INST_TLBILX_EARLY | \ 73 - __PPC_T_TLB(t) | \ 74 - __PPC_RA(a) | __PPC_RB(b)) 75 - #define PPC_TLBILX_ALL_EARLY(a, b) PPC_TLBILX_EARLY(0, a, b) 76 - #define PPC_TLBILX_PID_EARLY(a, b) PPC_TLBILX_EARLY(1, a, b) 77 - #define PPC_TLBILX_VA_EARLY(a, b) PPC_TLBILX_EARLY(3, a, b) 78 71 #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ 79 72 __PPC_WC(w)) 80 73

+1 -1

arch/powerpc/kernel/cputable.c

··· 1766 1766 .cpu_features = CPU_FTRS_E500MC, 1767 1767 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1768 1768 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | 1769 - MMU_FTR_USE_TLBILX | MMU_FTR_TLBILX_EARLY_OPCODE, 1769 + MMU_FTR_USE_TLBILX, 1770 1770 .icache_bsize = 64, 1771 1771 .dcache_bsize = 64, 1772 1772 .num_pmcs = 4,

+2 -14

arch/powerpc/mm/tlb_nohash_low.S

··· 138 138 andi. r3,r3,MMUCSR0_TLBFI@l 139 139 bne 1b 140 140 MMU_FTR_SECTION_ELSE 141 - BEGIN_MMU_FTR_SECTION_NESTED(96) 142 - PPC_TLBILX_ALL(0,r3) 143 - MMU_FTR_SECTION_ELSE_NESTED(96) 144 - PPC_TLBILX_ALL_EARLY(0,r3) 145 - ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) 141 + PPC_TLBILX_ALL(0,0) 146 142 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) 147 143 msync 148 144 isync ··· 151 155 wrteei 0 152 156 mfspr r4,SPRN_MAS6 /* save MAS6 */ 153 157 mtspr SPRN_MAS6,r3 154 - BEGIN_MMU_FTR_SECTION_NESTED(96) 155 158 PPC_TLBILX_PID(0,0) 156 - MMU_FTR_SECTION_ELSE_NESTED(96) 157 - PPC_TLBILX_PID_EARLY(0,0) 158 - ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) 159 159 mtspr SPRN_MAS6,r4 /* restore MAS6 */ 160 160 wrtee r10 161 161 MMU_FTR_SECTION_ELSE ··· 185 193 mtspr SPRN_MAS1,r4 186 194 tlbwe 187 195 MMU_FTR_SECTION_ELSE 188 - BEGIN_MMU_FTR_SECTION_NESTED(96) 189 196 PPC_TLBILX_VA(0,r3) 190 - MMU_FTR_SECTION_ELSE_NESTED(96) 191 - PPC_TLBILX_VA_EARLY(0,r3) 192 - ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) 193 197 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) 194 198 msync 195 199 isync 196 200 1: wrtee r10 197 201 blr 198 - #elif 202 + #else 199 203 #error Unsupported processor type ! 200 204 #endif

+4 -1

arch/powerpc/platforms/cell/Kconfig

··· 13 13 config PPC_CELL_NATIVE 14 14 bool 15 15 select PPC_CELL_COMMON 16 - select PPC_OF_PLATFORM_PCI 17 16 select MPIC 18 17 select IBM_NEW_EMAC_EMAC4 19 18 select IBM_NEW_EMAC_RGMII ··· 24 25 bool "IBM Cell Blade" 25 26 depends on PPC64 && PPC_BOOK3S 26 27 select PPC_CELL_NATIVE 28 + select PPC_OF_PLATFORM_PCI 29 + select PCI 27 30 select MMIO_NVRAM 28 31 select PPC_UDBG_16550 29 32 select UDBG_RTAS_CONSOLE ··· 34 33 bool "Toshiba's Cell Reference Set 'Celleb' Architecture" 35 34 depends on PPC64 && PPC_BOOK3S 36 35 select PPC_CELL_NATIVE 36 + select PPC_OF_PLATFORM_PCI 37 + select PCI 37 38 select HAS_TXX9_SERIAL 38 39 select PPC_UDBG_BEAT 39 40 select USB_OHCI_BIG_ENDIAN_MMIO

-4

arch/powerpc/platforms/ps3/setup.c

··· 45 45 DEFINE_MUTEX(ps3_gpu_mutex); 46 46 EXPORT_SYMBOL_GPL(ps3_gpu_mutex); 47 47 48 - #if !defined(CONFIG_SMP) 49 - static void smp_send_stop(void) {} 50 - #endif 51 - 52 48 static union ps3_firmware_version ps3_firmware_version; 53 49 54 50 void ps3_get_firmware_version(union ps3_firmware_version *v)