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kernel
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linux
clk: qcom: clk-alpha-pll: Add support for zonda ole pll configure
Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add
support for it.
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-6-7fb08c861c7c@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Rajendra Nayak
and committed by
Bjorn Andersson
c32f4f4a
78654850
+20
+16
drivers/clk/qcom/clk-alpha-pll.c
+16
drivers/clk/qcom/clk-alpha-pll.c
···
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#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
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#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
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#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
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+
#define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2])
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#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
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#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
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#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
···
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[PLL_OFF_STATUS] = 0x1c,
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[PLL_OFF_ALPHA_VAL] = 0x24,
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[PLL_OFF_ALPHA_VAL_U] = 0x28,
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+
},
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[CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = {
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[PLL_OFF_L_VAL] = 0x04,
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+
[PLL_OFF_ALPHA_VAL] = 0x08,
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[PLL_OFF_USER_CTL] = 0x0c,
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[PLL_OFF_USER_CTL_U] = 0x10,
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[PLL_OFF_CONFIG_CTL] = 0x14,
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[PLL_OFF_CONFIG_CTL_U] = 0x18,
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[PLL_OFF_CONFIG_CTL_U1] = 0x1c,
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+
[PLL_OFF_CONFIG_CTL_U2] = 0x20,
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[PLL_OFF_TEST_CTL] = 0x24,
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+
[PLL_OFF_TEST_CTL_U] = 0x28,
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[PLL_OFF_TEST_CTL_U1] = 0x2c,
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[PLL_OFF_OPMODE] = 0x30,
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[PLL_OFF_STATUS] = 0x3c,
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},
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
+4
drivers/clk/qcom/clk-alpha-pll.h
+4
drivers/clk/qcom/clk-alpha-pll.h
···
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CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
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CLK_ALPHA_PLL_TYPE_AGERA,
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CLK_ALPHA_PLL_TYPE_ZONDA,
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+
CLK_ALPHA_PLL_TYPE_ZONDA_OLE,
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CLK_ALPHA_PLL_TYPE_LUCID_EVO,
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CLK_ALPHA_PLL_TYPE_LUCID_OLE,
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CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
···
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PLL_OFF_CONFIG_CTL,
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PLL_OFF_CONFIG_CTL_U,
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PLL_OFF_CONFIG_CTL_U1,
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+
PLL_OFF_CONFIG_CTL_U2,
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PLL_OFF_TEST_CTL,
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PLL_OFF_TEST_CTL_U,
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PLL_OFF_TEST_CTL_U1,
···
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u32 config_ctl_val;
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u32 config_ctl_hi_val;
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u32 config_ctl_hi1_val;
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u32 config_ctl_hi2_val;
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u32 user_ctl_val;
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u32 user_ctl_hi_val;
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u32 user_ctl_hi1_val;
···
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extern const struct clk_ops clk_alpha_pll_zonda_ops;
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#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
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+
#define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops
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extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
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extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;